OV - exec - Function hypre_IJMatrixSetValuesOMPParCSR._omp

	Function: hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1	Module: exec	Source: IJMatrix_parcsr.c:3240-3500 [...]	Coverage (incl. loops): 0.18% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3500

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

3284:          }

3285: #ifdef HYPRE_USING_OPENMP

3286: #pragma omp barrier

3287: #endif

3288:          indx = 0;

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

[...]

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

3353:                      local_j = aux_j[row_local];

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

3378: 	          cnt_diag = diag_indx;

3379: 	          cnt_offd = offd_indx;

3380: 	          diag_space = diag_i[row_local+1];

3381: 	          offd_space = offd_i[row_local+1];

3382: 	          not_found = 1;

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

3391: 		           {

3392:                               offd_data[j] = values[indx];

3393: 		              not_found = 0;

3394: 		              break;

3395: 		           }

3396: 	                }

3397: 	                if (not_found)

3398: 	                {

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

3411: 	    	              if (print_level)

3412:                                  hypre_printf("Error in row %d ! Too many elements!\n",

[...]

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

3425: 		           {

3426:                               diag_data[j] = values[indx];

3427: 		              not_found = 0;

3428: 		              break;

3429: 		           }

3430: 	                }

3431: 	                if (not_found)

3432: 	                {

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

3445: 	    	              if (print_level)

3446:                                  hypre_printf("Error in row %d ! Too many elements !\n",

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

[...]

3500: 		        col_indx += row_len;

0x500f20 STP	X29, X30, [SP, #688]!

0x500f24 ORR	X12, XZR, X0

0x500f28 ADD	X29, SP, #0

0x500f2c STP	X19, X20, [SP, #16]

0x500f30 STP	X21, X22, [SP, #32]

0x500f34 STP	X23, X24, [SP, #48]

0x500f38 STP	X25, X26, [SP, #64]

0x500f3c STP	X27, X28, [SP, #80]

0x500f40 LDR	X11, [X12, #40]

0x500f44 LDP	X28, X5, [X12, #24]

0x500f48 LDP	X8, X7, [X12, #56]

0x500f4c LDP	X22, X0, [X0]

0x500f50 STP	X7, X8, [SP, #240]

0x500f54 STP	X11, X5, [SP, #256]

0x500f58 LDR	X1, [X12, #16]

0x500f5c STR	X12, [SP, #104]

0x500f60 LDR	X2, [X12, #48]

0x500f64 STR	X0, [SP, #120]

0x500f68 LDR	X3, [X12, #72]

0x500f6c STR	X1, [SP, #128]

0x500f70 LDR	X4, [X12, #80]

0x500f74 STR	X2, [SP, #136]

0x500f78 LDR	X6, [X12, #88]

0x500f7c STR	X3, [SP, #208]

0x500f80 LDR	X9, [X12, #96]

0x500f84 STR	X4, [SP, #200]

0x500f88 STR	X6, [SP, #184]

0x500f8c STR	X9, [SP, #216]

0x500f90 LDR	X10, [X12, #104]

0x500f94 LDP	X18, X23, [X12, #136]

0x500f98 LDP	X21, X20, [X12, #192]

0x500f9c STR	X18, [SP, #144]

0x500fa0 LDR	X13, [X12, #112]

0x500fa4 STR	X10, [SP, #176]

0x500fa8 LDR	X14, [X12, #128]

0x500fac LDR	X15, [X12, #152]

0x500fb0 STR	X13, [SP, #192]

0x500fb4 LDR	X16, [X12, #160]

0x500fb8 STR	X14, [SP, #232]

0x500fbc LDR	X17, [X12, #168]

0x500fc0 STR	X15, [SP, #224]

0x500fc4 LDR	X19, [X12, #176]

0x500fc8 STR	X16, [SP, #112]

0x500fcc LDR	X25, [X12, #184]

0x500fd0 STR	X17, [SP, #152]

0x500fd4 LDR	X27, [X12, #208]

0x500fd8 STR	X19, [SP, #160]

0x500fdc LDR	X24, [X12, #120]

0x500fe0 STR	X25, [SP, #168]

0x500fe4 LDR	X26, [X12, #216]

0x500fe8 STR	X27, [SP, #280]

0x500fec BL	527b20

0x500ff0 ORR	X19, XZR, X0

0x500ff4 BL	527b40

0x500ff8 SDIV	X1, X22, X19

0x500ffc LDR	X12, [SP, #104]

0x501000 ORR	X25, XZR, X0

0x501004 LDP	X7, X8, [SP, #240]

0x501008 LDP	X11, X5, [SP, #256]

0x50100c LDR	X6, [SP, #144]

0x501010 MSUB	X22, X1, X19, X22

0x501014 CMP	X0, X22

0x501018 B.GE	501d70

0x50101c MADD	X27, X1, X0, X0

0x501020 ADD	X2, X1, #1

0x501024 UBFM	X19, X25, #61, #60

0x501028 ADD	X22, X21, X25,LSL #3

0x50102c STR	XZR, [X21, X19]

0x501030 ADD	X3, X2, X27

0x501034 STR	X3, [SP, #104]

0x501038 CMP	X27, X3

0x50103c B.GE	501d98

0x501040 LDR	X4, [SP, #120]

0x501044 MOVZ	X0, #0

0x501048 ADD	X1, X4, X27,LSL #3

0x50104c ADD	X9, X4, X3,LSL #3

0x501050 SUB	X10, X9, X1

0x501054 SUB	X18, X10, #8

0x501058 UBFM	X13, X18, #3, #63

0x50105c ADD	X14, X13, #1

0x501060 ANDS	X15, X14, #0x7

0x501064 B.EQ	5010e8

0x501068 CMP	X15, #1

0x50106c B.EQ	5010d4

0x501070 CMP	X15, #2

0x501074 B.EQ	5010c8

0x501078 CMP	X15, #3

0x50107c B.EQ	5010bc

0x501080 CMP	X15, #4

0x501084 B.EQ	5010b0

0x501088 CMP	X15, #5

0x50108c B.EQ	5010a4

0x501090 CMP	X15, #6

0x501094 B.NE	501ef8

0x501098 LDR	X16, [X1], #8

0x50109c ADD	X0, X0, X16

0x5010a0 STR	X0, [X22]

0x5010a4 LDR	X17, [X1], #8

0x5010a8 ADD	X0, X0, X17

0x5010ac STR	X0, [X22]

0x5010b0 LDR	X30, [X1], #8

0x5010b4 ADD	X0, X0, X30

0x5010b8 STR	X0, [X22]

0x5010bc LDR	X2, [X1], #8

0x5010c0 ADD	X0, X0, X2

0x5010c4 STR	X0, [X22]

0x5010c8 LDR	X3, [X1], #8

0x5010cc ADD	X0, X0, X3

0x5010d0 STR	X0, [X22]

0x5010d4 LDR	X4, [X1], #8

0x5010d8 ADD	X0, X0, X4

0x5010dc STR	X0, [X22]

0x5010e0 CMP	X1, X9

0x5010e4 B.EQ	501158

(2942) 0x5010e8 ORR	X10, XZR, X1

(2942) 0x5010ec ADD	X1, X1, #64

(2942) 0x5010f0 LDR	X18, [X10], #8

(2942) 0x5010f4 ADD	X13, X0, X18

(2942) 0x5010f8 STR	X13, [X22]

(2942) 0x5010fc LDUR	X14, [X1, #456]

(2942) 0x501100 ADD	X15, X13, X14

(2942) 0x501104 STR	X15, [X22]

(2942) 0x501108 LDR	X16, [X10, #8]

(2942) 0x50110c ADD	X17, X15, X16

(2942) 0x501110 STR	X17, [X22]

(2942) 0x501114 LDUR	X30, [X1, #472]

(2942) 0x501118 ADD	X3, X17, X30

(2942) 0x50111c STR	X3, [X22]

(2942) 0x501120 LDUR	X2, [X1, #480]

(2942) 0x501124 ADD	X4, X3, X2

(2942) 0x501128 STR	X4, [X22]

(2942) 0x50112c LDUR	X0, [X1, #488]

(2942) 0x501130 ADD	X10, X4, X0

(2942) 0x501134 STR	X10, [X22]

(2942) 0x501138 LDUR	X18, [X1, #496]

(2942) 0x50113c ADD	X13, X10, X18

(2942) 0x501140 STR	X13, [X22]

(2942) 0x501144 LDUR	X14, [X1, #504]

(2942) 0x501148 ADD	X0, X13, X14

(2942) 0x50114c STR	X0, [X22]

(2942) 0x501150 CMP	X1, X9

(2942) 0x501154 B.NE	5010e8

0x501158 STR	X6, [SP, #144]

0x50115c STP	X7, X8, [SP, #240]

0x501160 STP	X11, X5, [SP, #256]

0x501164 STR	X12, [SP, #272]

0x501168 BL	4102a0

0x50116c LDR	X9, [SP, #144]

0x501170 LDP	X7, X8, [SP, #240]

0x501174 LDP	X11, X5, [SP, #256]

0x501178 LDR	X12, [SP, #272]

0x50117c CBNZ	X25, 501e58

0x501180 CMP	X26, #0

0x501184 B.LE	50129c

0x501188 ORR	X0, XZR, X21

0x50118c UBFM	X21, X26, #61, #60

0x501190 LDR	X18, [X0], #8

0x501194 SUB	X25, X21, #8

0x501198 UBFM	X6, X25, #3, #63

0x50119c ADD	X22, X6, #1

0x5011a0 ANDS	X15, X22, #0x7

0x5011a4 ADD	X26, X0, X26,LSL #3

0x5011a8 B.EQ	501238

0x5011ac CMP	X15, #1

0x5011b0 B.EQ	501224

0x5011b4 CMP	X15, #2

0x5011b8 B.EQ	501218

0x5011bc CMP	X15, #3

0x5011c0 B.EQ	50120c

0x5011c4 CMP	X15, #4

0x5011c8 B.EQ	501200

0x5011cc CMP	X15, #5

0x5011d0 B.EQ	5011f4

0x5011d4 CMP	X15, #6

0x5011d8 B.EQ	5011e8

0x5011dc LDR	X16, [X0]

0x5011e0 ADD	X18, X18, X16

0x5011e4 STR	X18, [X0], #8

0x5011e8 LDR	X17, [X0]

0x5011ec ADD	X18, X18, X17

0x5011f0 STR	X18, [X0], #8

0x5011f4 LDR	X30, [X0]

0x5011f8 ADD	X18, X18, X30

0x5011fc STR	X18, [X0], #8

0x501200 LDR	X3, [X0]

0x501204 ADD	X18, X18, X3

0x501208 STR	X18, [X0], #8

0x50120c LDR	X2, [X0]

0x501210 ADD	X18, X18, X2

0x501214 STR	X18, [X0], #8

0x501218 LDR	X4, [X0]

0x50121c ADD	X18, X18, X4

0x501220 STR	X18, [X0], #8

0x501224 LDR	X10, [X0]

0x501228 ADD	X18, X18, X10

0x50122c STR	X18, [X0], #8

0x501230 CMP	X0, X26

0x501234 B.EQ	50129c

(2955) 0x501238 LDR	X14, [X0]

(2955) 0x50123c ORR	X13, XZR, X0

(2955) 0x501240 ADD	X1, X18, X14

(2955) 0x501244 STR	X1, [X13], #8

(2955) 0x501248 LDR	X21, [X0, #8]

(2955) 0x50124c ADD	X25, X1, X21

(2955) 0x501250 STR	X25, [X0, #8]

(2955) 0x501254 LDR	X6, [X13, #8]

(2955) 0x501258 ADD	X22, X25, X6

(2955) 0x50125c STR	X22, [X13, #8]

(2955) 0x501260 LDP	X15, X16, [X0, #24]

(2955) 0x501264 ADD	X0, X0, #64

(2955) 0x501268 LDUR	X17, [X0, #488]

(2955) 0x50126c ADD	X30, X22, X15

(2955) 0x501270 LDUR	X2, [X0, #496]

(2955) 0x501274 ADD	X3, X30, X16

(2955) 0x501278 LDUR	X18, [X0, #504]

(2955) 0x50127c ADD	X4, X3, X17

(2955) 0x501280 STP	X30, X3, [X0, #984]

(2955) 0x501284 ADD	X10, X4, X2

(2955) 0x501288 ADD	X18, X10, X18

(2955) 0x50128c STP	X4, X10, [X0, #1000]

(2955) 0x501290 STUR	X18, [X0, #504]

(2955) 0x501294 CMP	X0, X26

(2955) 0x501298 B.NE	501238

0x50129c STR	X9, [SP, #144]

0x5012a0 MOVZ	X21, #0

0x5012a4 STP	X7, X8, [SP, #240]

0x5012a8 STP	X11, X5, [SP, #256]

0x5012ac STR	X12, [SP, #272]

0x5012b0 BL	4102a0

0x5012b4 LDR	X18, [SP, #144]

0x5012b8 LDP	X7, X8, [SP, #240]

0x5012bc LDP	X11, X5, [SP, #256]

0x5012c0 LDR	X12, [SP, #272]

0x5012c4 LDR	X9, [SP, #104]

0x5012c8 CMP	X27, X9

0x5012cc B.GE	501558

0x5012d0 LDR	X1, [SP, #152]

0x5012d4 MOVZ	X9, #0

0x5012d8 MOVN	X22, #0

0x5012dc ORR	X26, XZR, X5

0x5012e0 LDR	X13, [SP, #112]

0x5012e4 LDR	X14, [SP, #136]

0x5012e8 SUB	X25, X1, #1

0x5012ec LDR	X17, [SP, #160]

0x5012f0 UBFM	X15, X25, #1, #63

0x5012f4 LDR	X5, [SP, #224]

0x5012f8 ADD	X6, X14, X13,LSL #3

0x5012fc STR	X12, [SP, #224]

0x501300 ADD	X30, X17, #16

0x501304 ADD	X3, X6, #8

0x501308 ADD	X4, X30, X15,LSL #4

0x50130c STP	X6, X3, [SP, #136]

(2943) 0x501310 LDR	X0, [SP, #136]

(2943) 0x501314 LDP	X2, X10, [SP, #120]

(2943) 0x501318 LDR	X13, [X0]

(2943) 0x50131c LDR	X25, [X10, X27,LSL #3]

(2943) 0x501320 LDR	X12, [X2, X27,LSL #3]

(2943) 0x501324 CMP	X25, X13

(2943) 0x501328 B.LT	5016f0

(2943) 0x50132c LDR	X14, [SP, #144]

(2943) 0x501330 LDR	X1, [X14]

(2943) 0x501334 CMP	X25, X1

(2943) 0x501338 B.GE	5016f0

(2943) 0x50133c LDR	X16, [SP, #176]

(2943) 0x501340 SUB	X30, X25, X13

(2943) 0x501344 UBFM	X13, X30, #61, #60

(2943) 0x501348 CBNZ	X16, 501a30

(2943) 0x50134c LDP	X1, X0, [X11, #56]

(2943) 0x501350 ADD	X17, X13, #8

(2943) 0x501354 ADD	X16, X21, X12

(2943) 0x501358 LDR	X10, [SP, #192]

(2943) 0x50135c ADD	X6, X0, X13

(2943) 0x501360 LDR	X2, [X0, X13]

(2943) 0x501364 ADD	X0, X1, X13

(2943) 0x501368 LDR	X3, [X1, X13]

(2943) 0x50136c LDR	X30, [X18, X17]

(2943) 0x501370 ORR	X14, XZR, X2

(2943) 0x501374 LDR	X17, [X10, X17]

(2943) 0x501378 ORR	X15, XZR, X3

(2943) 0x50137c CMP	X12, #0

(2943) 0x501380 B.LE	50215c

(2943) 0x501384 LDR	X10, [SP, #192]

(2943) 0x501388 STP	X25, X6, [SP, #240]

(2943) 0x50138c ORR	X6, XZR, X0

(2943) 0x501390 LDR	X12, [SP, #232]

(2943) 0x501394 HINT	#0

(2943) 0x501398 HINT	#0

(2943) 0x50139c HINT	#0

  (2952) 0x5013a0 LDR	X1, [X28, X21,LSL #3]

  (2952) 0x5013a4 CMP	X8, X1

  (2952) 0x5013a8 CCMP	X7, X1, #1, #13

  (2952) 0x5013ac B.GE	501574

  (2952) 0x5013b0 LDR	X0, [X18, X13]

  (2952) 0x5013b4 CMP	X2, X0

  (2952) 0x5013b8 B.LE	50150c

  (2952) 0x5013bc SUB	X25, X2, X0

  (2952) 0x5013c0 ANDS	X25, X25, #0x7

  (2952) 0x5013c4 B.EQ	501470

  (2952) 0x5013c8 CMP	X25, #1

  (2952) 0x5013cc B.EQ	501458

  (2952) 0x5013d0 CMP	X25, #2

  (2952) 0x5013d4 B.EQ	501448

  (2952) 0x5013d8 CMP	X25, #3

  (2952) 0x5013dc B.EQ	501438

  (2952) 0x5013e0 CMP	X25, #4

  (2952) 0x5013e4 B.EQ	501428

  (2952) 0x5013e8 CMP	X25, #5

  (2952) 0x5013ec B.EQ	501418

  (2952) 0x5013f0 CMP	X25, #6

  (2952) 0x5013f4 B.EQ	501408

  (2952) 0x5013f8 LDR	X25, [X23, X0,LSL #3]

  (2952) 0x5013fc CMP	X1, X25

  (2952) 0x501400 B.EQ	501a10

  (2952) 0x501404 ADD	X0, X0, #1

  (2952) 0x501408 LDR	X25, [X23, X0,LSL #3]

  (2952) 0x50140c CMP	X1, X25

  (2952) 0x501410 B.EQ	501a10

  (2952) 0x501414 ADD	X0, X0, #1

  (2952) 0x501418 LDR	X25, [X23, X0,LSL #3]

  (2952) 0x50141c CMP	X1, X25

  (2952) 0x501420 B.EQ	501a10

  (2952) 0x501424 ADD	X0, X0, #1

  (2952) 0x501428 LDR	X25, [X23, X0,LSL #3]

  (2952) 0x50142c CMP	X1, X25

  (2952) 0x501430 B.EQ	501a10

  (2952) 0x501434 ADD	X0, X0, #1

  (2952) 0x501438 LDR	X25, [X23, X0,LSL #3]

  (2952) 0x50143c CMP	X1, X25

  (2952) 0x501440 B.EQ	501a10

  (2952) 0x501444 ADD	X0, X0, #1

  (2952) 0x501448 LDR	X25, [X23, X0,LSL #3]

  (2952) 0x50144c CMP	X1, X25

  (2952) 0x501450 B.EQ	501a10

  (2952) 0x501454 ADD	X0, X0, #1

  (2952) 0x501458 LDR	X25, [X23, X0,LSL #3]

  (2952) 0x50145c CMP	X1, X25

  (2952) 0x501460 B.EQ	501a10

  (2952) 0x501464 ADD	X0, X0, #1

  (2952) 0x501468 CMP	X2, X0

  (2952) 0x50146c B.EQ	50150c

  (2952) 0x501470 ORR	X25, XZR, X9

  (2952) 0x501474 STR	X3, [SP, #112]

    (2954) 0x501478 LDR	X9, [X23, X0,LSL #3]

    (2954) 0x50147c CMP	X1, X9

    (2954) 0x501480 B.EQ	501a08

    (2954) 0x501484 ADD	X0, X0, #1

    (2954) 0x501488 LDR	X3, [X23, X0,LSL #3]

    (2954) 0x50148c ORR	X9, XZR, X0

    (2954) 0x501490 CMP	X1, X3

    (2954) 0x501494 B.EQ	501a08

    (2954) 0x501498 ADD	X0, X0, #1

    (2954) 0x50149c LDR	X3, [X23, X0,LSL #3]

    (2954) 0x5014a0 CMP	X1, X3

    (2954) 0x5014a4 B.EQ	501a08

    (2954) 0x5014a8 ADD	X0, X9, #2

    (2954) 0x5014ac LDR	X3, [X23, X0,LSL #3]

    (2954) 0x5014b0 CMP	X1, X3

    (2954) 0x5014b4 B.EQ	501a08

    (2954) 0x5014b8 ADD	X0, X9, #3

    (2954) 0x5014bc LDR	X3, [X23, X0,LSL #3]

    (2954) 0x5014c0 CMP	X1, X3

    (2954) 0x5014c4 B.EQ	501a08

    (2954) 0x5014c8 ADD	X0, X9, #4

    (2954) 0x5014cc LDR	X3, [X23, X0,LSL #3]

    (2954) 0x5014d0 CMP	X1, X3

    (2954) 0x5014d4 B.EQ	501a08

    (2954) 0x5014d8 ADD	X0, X9, #5

    (2954) 0x5014dc LDR	X3, [X23, X0,LSL #3]

    (2954) 0x5014e0 CMP	X1, X3

    (2954) 0x5014e4 B.EQ	501a08

    (2954) 0x5014e8 ADD	X0, X9, #6

    (2954) 0x5014ec LDR	X3, [X23, X0,LSL #3]

    (2954) 0x5014f0 CMP	X1, X3

    (2954) 0x5014f4 B.EQ	501a08

    (2954) 0x5014f8 ADD	X0, X9, #7

    (2954) 0x5014fc CMP	X2, X0

    (2954) 0x501500 B.NE	501478

  (2952) 0x501504 LDR	X3, [SP, #112]

  (2952) 0x501508 ORR	X9, XZR, X25

  (2952) 0x50150c CMP	X30, X14

  (2952) 0x501510 B.LE	501e84

  (2952) 0x501514 LDR	D1, [X26, X21,LSL #3]

  (2952) 0x501518 UBFM	X25, X14, #61, #60

  (2952) 0x50151c ADD	X14, X14, #1

  (2952) 0x501520 STR	X1, [X23, X25]

  (2952) 0x501524 STR	D1, [X5, X25]

  (2952) 0x501528 ADD	X21, X21, #1

  (2952) 0x50152c CMP	X21, X16

  (2952) 0x501530 B.NE	5013a0

(2943) 0x501534 ORR	X0, XZR, X6

(2943) 0x501538 LDR	X6, [SP, #248]

(2943) 0x50153c STR	X15, [X0]

(2943) 0x501540 ADD	X27, X27, #1

(2943) 0x501544 ORR	X21, XZR, X16

(2943) 0x501548 LDR	X12, [SP, #104]

(2943) 0x50154c STR	X14, [X6]

(2943) 0x501550 CMP	X12, X27

(2943) 0x501554 B.NE	501310

0x501558 LDP	X19, X20, [SP, #16]

0x50155c LDP	X21, X22, [SP, #32]

0x501560 LDP	X23, X24, [SP, #48]

0x501564 LDP	X25, X26, [SP, #64]

0x501568 LDP	X27, X28, [SP, #80]

0x50156c LDP	X29, X30, [SP], #336

0x501570 RET

  (2952) 0x501574 LDR	X0, [X10, X13]

  (2952) 0x501578 CMP	X3, X0

  (2952) 0x50157c B.LE	5016d0

  (2952) 0x501580 SUB	X25, X3, X0

  (2952) 0x501584 ANDS	X25, X25, #0x7

  (2952) 0x501588 B.EQ	501634

  (2952) 0x50158c CMP	X25, #1

  (2952) 0x501590 B.EQ	50161c

  (2952) 0x501594 CMP	X25, #2

  (2952) 0x501598 B.EQ	50160c

  (2952) 0x50159c CMP	X25, #3

  (2952) 0x5015a0 B.EQ	5015fc

  (2952) 0x5015a4 CMP	X25, #4

  (2952) 0x5015a8 B.EQ	5015ec

  (2952) 0x5015ac CMP	X25, #5

  (2952) 0x5015b0 B.EQ	5015dc

  (2952) 0x5015b4 CMP	X25, #6

  (2952) 0x5015b8 B.EQ	5015cc

  (2952) 0x5015bc LDR	X25, [X24, X0,LSL #3]

  (2952) 0x5015c0 CMP	X1, X25

  (2952) 0x5015c4 B.EQ	501a24

  (2952) 0x5015c8 ADD	X0, X0, #1

  (2952) 0x5015cc LDR	X25, [X24, X0,LSL #3]

  (2952) 0x5015d0 CMP	X1, X25

  (2952) 0x5015d4 B.EQ	501a24

  (2952) 0x5015d8 ADD	X0, X0, #1

  (2952) 0x5015dc LDR	X25, [X24, X0,LSL #3]

  (2952) 0x5015e0 CMP	X1, X25

  (2952) 0x5015e4 B.EQ	501a24

  (2952) 0x5015e8 ADD	X0, X0, #1

  (2952) 0x5015ec LDR	X25, [X24, X0,LSL #3]

  (2952) 0x5015f0 CMP	X1, X25

  (2952) 0x5015f4 B.EQ	501a24

  (2952) 0x5015f8 ADD	X0, X0, #1

  (2952) 0x5015fc LDR	X25, [X24, X0,LSL #3]

  (2952) 0x501600 CMP	X1, X25

  (2952) 0x501604 B.EQ	501a24

  (2952) 0x501608 ADD	X0, X0, #1

  (2952) 0x50160c LDR	X25, [X24, X0,LSL #3]

  (2952) 0x501610 CMP	X1, X25

  (2952) 0x501614 B.EQ	501a24

  (2952) 0x501618 ADD	X0, X0, #1

  (2952) 0x50161c LDR	X25, [X24, X0,LSL #3]

  (2952) 0x501620 CMP	X1, X25

  (2952) 0x501624 B.EQ	501a24

  (2952) 0x501628 ADD	X0, X0, #1

  (2952) 0x50162c CMP	X3, X0

  (2952) 0x501630 B.EQ	5016d0

  (2952) 0x501634 ORR	X25, XZR, X9

  (2952) 0x501638 STR	X2, [SP, #112]

    (2953) 0x50163c LDR	X9, [X24, X0,LSL #3]

    (2953) 0x501640 CMP	X1, X9

    (2953) 0x501644 B.EQ	501a1c

    (2953) 0x501648 ADD	X0, X0, #1

    (2953) 0x50164c LDR	X2, [X24, X0,LSL #3]

    (2953) 0x501650 ORR	X9, XZR, X0

    (2953) 0x501654 CMP	X1, X2

    (2953) 0x501658 B.EQ	501a1c

    (2953) 0x50165c ADD	X0, X0, #1

    (2953) 0x501660 LDR	X2, [X24, X0,LSL #3]

    (2953) 0x501664 CMP	X1, X2

    (2953) 0x501668 B.EQ	501a1c

    (2953) 0x50166c ADD	X0, X9, #2

    (2953) 0x501670 LDR	X2, [X24, X0,LSL #3]

    (2953) 0x501674 CMP	X1, X2

    (2953) 0x501678 B.EQ	501a1c

    (2953) 0x50167c ADD	X0, X9, #3

    (2953) 0x501680 LDR	X2, [X24, X0,LSL #3]

    (2953) 0x501684 CMP	X1, X2

    (2953) 0x501688 B.EQ	501a1c

    (2953) 0x50168c ADD	X0, X9, #4

    (2953) 0x501690 LDR	X2, [X24, X0,LSL #3]

    (2953) 0x501694 CMP	X1, X2

    (2953) 0x501698 B.EQ	501a1c

    (2953) 0x50169c ADD	X0, X9, #5

    (2953) 0x5016a0 LDR	X2, [X24, X0,LSL #3]

    (2953) 0x5016a4 CMP	X1, X2

    (2953) 0x5016a8 B.EQ	501a1c

    (2953) 0x5016ac ADD	X0, X9, #6

    (2953) 0x5016b0 LDR	X2, [X24, X0,LSL #3]

    (2953) 0x5016b4 CMP	X1, X2

    (2953) 0x5016b8 B.EQ	501a1c

    (2953) 0x5016bc ADD	X0, X9, #7

    (2953) 0x5016c0 CMP	X3, X0

    (2953) 0x5016c4 B.NE	50163c

  (2952) 0x5016c8 LDR	X2, [SP, #112]

  (2952) 0x5016cc ORR	X9, XZR, X25

  (2952) 0x5016d0 CMP	X17, X15

  (2952) 0x5016d4 B.LE	501f58

  (2952) 0x5016d8 LDR	D31, [X26, X21,LSL #3]

  (2952) 0x5016dc UBFM	X0, X15, #61, #60

  (2952) 0x5016e0 ADD	X15, X15, #1

  (2952) 0x5016e4 STR	X1, [X24, X0]

  (2952) 0x5016e8 STR	D31, [X12, X0]

  (2952) 0x5016ec B	501528

(2943) 0x5016f0 CBNZ	X11, 501724

(2943) 0x5016f4 ADD	X21, X21, X12

(2943) 0x5016f8 LDR	X12, [SP, #104]

(2943) 0x5016fc ADD	X27, X27, #1

(2943) 0x501700 CMP	X12, X27

(2943) 0x501704 B.NE	501310

0x501708 LDP	X19, X20, [SP, #16]

0x50170c LDP	X21, X22, [SP, #32]

0x501710 LDP	X23, X24, [SP, #48]

0x501714 LDP	X25, X26, [SP, #64]

0x501718 LDP	X27, X28, [SP, #80]

0x50171c LDP	X29, X30, [SP], #336

0x501720 RET

(2943) 0x501724 LDR	X6, [SP, #152]

(2943) 0x501728 CMP	X6, #0

(2943) 0x50172c B.LE	5016f4

(2943) 0x501730 LDP	X2, X0, [SP, #160]

(2943) 0x501734 ADD	X15, X28, X12,LSL #3

(2943) 0x501738 MOVZ	X14, #0

(2943) 0x50173c B	50174c

  (2944) 0x501740 ADD	X2, X2, #16

  (2944) 0x501744 CMP	X2, X4

  (2944) 0x501748 B.EQ	5016f4

  (2944) 0x50174c LDP	X17, X30, [X2]

  (2944) 0x501750 ORR	X16, XZR, X14

  (2944) 0x501754 ADD	X14, X14, X30

  (2944) 0x501758 CMP	X25, X17

  (2944) 0x50175c B.NE	501740

  (2944) 0x501760 CMP	X12, #0

  (2944) 0x501764 B.LE	501740

  (2944) 0x501768 CMP	X30, #0

  (2944) 0x50176c B.LE	501740

  (2944) 0x501770 ADD	X10, X0, X16,LSL #3

  (2944) 0x501774 ORR	X3, XZR, X28

  (2944) 0x501778 ADD	X6, X0, X14,LSL #3

  (2944) 0x50177c HINT	#0

    (2946) 0x501780 SUB	X16, X6, X10

    (2946) 0x501784 ORR	X1, XZR, X10

    (2946) 0x501788 SUB	X17, X16, #8

    (2946) 0x50178c UBFM	X30, X17, #3, #63

    (2946) 0x501790 ADD	X13, X30, #1

    (2946) 0x501794 ANDS	X16, X13, #0x7

    (2946) 0x501798 B.EQ	501870

    (2946) 0x50179c CMP	X16, #1

    (2946) 0x5017a0 B.EQ	501844

    (2946) 0x5017a4 CMP	X16, #2

    (2946) 0x5017a8 B.EQ	501830

    (2946) 0x5017ac CMP	X16, #3

    (2946) 0x5017b0 B.EQ	50181c

    (2946) 0x5017b4 CMP	X16, #4

    (2946) 0x5017b8 B.EQ	501808

    (2946) 0x5017bc CMP	X16, #5

    (2946) 0x5017c0 B.EQ	5017f4

    (2946) 0x5017c4 CMP	X16, #6

    (2946) 0x5017c8 B.EQ	5017e0

    (2946) 0x5017cc LDR	X17, [X3]

    (2946) 0x5017d0 LDR	X1, [X10]

    (2946) 0x5017d4 CMP	X17, X1

    (2946) 0x5017d8 B.EQ	5019f4

    (2946) 0x5017dc ADD	X1, X10, #8

    (2946) 0x5017e0 LDR	X17, [X1]

    (2946) 0x5017e4 LDR	X16, [X3]

    (2946) 0x5017e8 CMP	X16, X17

    (2946) 0x5017ec B.EQ	5019e0

    (2946) 0x5017f0 ADD	X1, X1, #8

    (2946) 0x5017f4 LDR	X17, [X1]

    (2946) 0x5017f8 LDR	X16, [X3]

    (2946) 0x5017fc CMP	X16, X17

    (2946) 0x501800 B.EQ	5019cc

    (2946) 0x501804 ADD	X1, X1, #8

    (2946) 0x501808 LDR	X17, [X1]

    (2946) 0x50180c LDR	X16, [X3]

    (2946) 0x501810 CMP	X16, X17

    (2946) 0x501814 B.EQ	5019b8

    (2946) 0x501818 ADD	X1, X1, #8

    (2946) 0x50181c LDR	X17, [X1]

    (2946) 0x501820 LDR	X16, [X3]

    (2946) 0x501824 CMP	X16, X17

    (2946) 0x501828 B.EQ	5019a4

    (2946) 0x50182c ADD	X1, X1, #8

    (2946) 0x501830 LDR	X17, [X1]

    (2946) 0x501834 LDR	X16, [X3]

    (2946) 0x501838 CMP	X16, X17

    (2946) 0x50183c B.EQ	501990

    (2946) 0x501840 ADD	X1, X1, #8

    (2946) 0x501844 LDR	X17, [X1]

    (2946) 0x501848 LDR	X16, [X3]

    (2946) 0x50184c CMP	X16, X17

    (2946) 0x501850 B.NE	501864

    (2946) 0x501854 STR	X22, [X1]

    (2946) 0x501858 LDR	X30, [X20, X19]

    (2946) 0x50185c ADD	X13, X30, #1

    (2946) 0x501860 STR	X13, [X20, X19]

    (2946) 0x501864 ADD	X1, X1, #8

    (2946) 0x501868 CMP	X6, X1

    (2946) 0x50186c B.EQ	501980

      (2945) 0x501870 LDR	X17, [X1]

      (2945) 0x501874 LDR	X16, [X3]

      (2945) 0x501878 CMP	X16, X17

      (2945) 0x50187c B.NE	501890

      (2945) 0x501880 STR	X22, [X1]

      (2945) 0x501884 LDR	X30, [X20, X19]

      (2945) 0x501888 ADD	X13, X30, #1

      (2945) 0x50188c STR	X13, [X20, X19]

      (2945) 0x501890 LDR	X17, [X3]

      (2945) 0x501894 ADD	X30, X1, #8

      (2945) 0x501898 LDR	X16, [X1, #8]

      (2945) 0x50189c CMP	X17, X16

      (2945) 0x5018a0 B.NE	5018b4

      (2945) 0x5018a4 STR	X22, [X1, #8]

      (2945) 0x5018a8 LDR	X1, [X20, X19]

      (2945) 0x5018ac ADD	X13, X1, #1

      (2945) 0x5018b0 STR	X13, [X20, X19]

      (2945) 0x5018b4 LDR	X16, [X3]

      (2945) 0x5018b8 LDR	X17, [X30, #8]

      (2945) 0x5018bc CMP	X16, X17

      (2945) 0x5018c0 B.NE	5018d4

      (2945) 0x5018c4 STR	X22, [X30, #8]

      (2945) 0x5018c8 LDR	X1, [X20, X19]

      (2945) 0x5018cc ADD	X13, X1, #1

      (2945) 0x5018d0 STR	X13, [X20, X19]

      (2945) 0x5018d4 LDR	X16, [X3]

      (2945) 0x5018d8 LDR	X17, [X30, #16]

      (2945) 0x5018dc CMP	X16, X17

      (2945) 0x5018e0 B.NE	5018f4

      (2945) 0x5018e4 STR	X22, [X30, #16]

      (2945) 0x5018e8 LDR	X1, [X20, X19]

      (2945) 0x5018ec ADD	X13, X1, #1

      (2945) 0x5018f0 STR	X13, [X20, X19]

      (2945) 0x5018f4 LDR	X16, [X3]

      (2945) 0x5018f8 LDR	X17, [X30, #24]

      (2945) 0x5018fc CMP	X16, X17

      (2945) 0x501900 B.NE	501914

      (2945) 0x501904 STR	X22, [X30, #24]

      (2945) 0x501908 LDR	X1, [X20, X19]

      (2945) 0x50190c ADD	X13, X1, #1

      (2945) 0x501910 STR	X13, [X20, X19]

      (2945) 0x501914 LDR	X16, [X3]

      (2945) 0x501918 LDR	X17, [X30, #32]

      (2945) 0x50191c CMP	X16, X17

      (2945) 0x501920 B.NE	501934

      (2945) 0x501924 STR	X22, [X30, #32]

      (2945) 0x501928 LDR	X1, [X20, X19]

      (2945) 0x50192c ADD	X13, X1, #1

      (2945) 0x501930 STR	X13, [X20, X19]

      (2945) 0x501934 LDR	X16, [X3]

      (2945) 0x501938 LDR	X17, [X30, #40]

      (2945) 0x50193c CMP	X16, X17

      (2945) 0x501940 B.NE	501954

      (2945) 0x501944 STR	X22, [X30, #40]

      (2945) 0x501948 LDR	X1, [X20, X19]

      (2945) 0x50194c ADD	X13, X1, #1

      (2945) 0x501950 STR	X13, [X20, X19]

      (2945) 0x501954 LDR	X16, [X3]

      (2945) 0x501958 LDR	X17, [X30, #48]

      (2945) 0x50195c CMP	X16, X17

      (2945) 0x501960 B.NE	501974

      (2945) 0x501964 STR	X22, [X30, #48]

      (2945) 0x501968 LDR	X1, [X20, X19]

      (2945) 0x50196c ADD	X13, X1, #1

      (2945) 0x501970 STR	X13, [X20, X19]

      (2945) 0x501974 ADD	X1, X30, #56

      (2945) 0x501978 CMP	X6, X1

      (2945) 0x50197c B.NE	501870

    (2946) 0x501980 ADD	X3, X3, #8

    (2946) 0x501984 CMP	X3, X15

    (2946) 0x501988 B.NE	501780

  (2944) 0x50198c B	501740

    (2946) 0x501990 STR	X22, [X1]

    (2946) 0x501994 LDR	X30, [X20, X19]

    (2946) 0x501998 ADD	X13, X30, #1

    (2946) 0x50199c STR	X13, [X20, X19]

    (2946) 0x5019a0 B	501840

    (2946) 0x5019a4 STR	X22, [X1]

    (2946) 0x5019a8 LDR	X30, [X20, X19]

    (2946) 0x5019ac ADD	X13, X30, #1

    (2946) 0x5019b0 STR	X13, [X20, X19]

    (2946) 0x5019b4 B	50182c

    (2946) 0x5019b8 STR	X22, [X1]

    (2946) 0x5019bc LDR	X30, [X20, X19]

    (2946) 0x5019c0 ADD	X13, X30, #1

    (2946) 0x5019c4 STR	X13, [X20, X19]

    (2946) 0x5019c8 B	501818

    (2946) 0x5019cc STR	X22, [X1]

    (2946) 0x5019d0 LDR	X30, [X20, X19]

    (2946) 0x5019d4 ADD	X13, X30, #1

    (2946) 0x5019d8 STR	X13, [X20, X19]

    (2946) 0x5019dc B	501804

    (2946) 0x5019e0 STR	X22, [X1]

    (2946) 0x5019e4 LDR	X30, [X20, X19]

    (2946) 0x5019e8 ADD	X13, X30, #1

    (2946) 0x5019ec STR	X13, [X20, X19]

    (2946) 0x5019f0 B	5017f0

    (2946) 0x5019f4 STR	X22, [X10]

    (2946) 0x5019f8 LDR	X30, [X20, X19]

    (2946) 0x5019fc ADD	X13, X30, #1

    (2946) 0x501a00 STR	X13, [X20, X19]

    (2946) 0x501a04 B	5017dc

  (2952) 0x501a08 LDR	X3, [SP, #112]

  (2952) 0x501a0c ORR	X9, XZR, X25

  (2952) 0x501a10 LDR	D2, [X26, X21,LSL #3]

  (2952) 0x501a14 STR	D2, [X5, X0,LSL #3]

  (2952) 0x501a18 B	501528

  (2952) 0x501a1c LDR	X2, [SP, #112]

  (2952) 0x501a20 ORR	X9, XZR, X25

  (2952) 0x501a24 LDR	D0, [X26, X21,LSL #3]

  (2952) 0x501a28 STR	D0, [X12, X0,LSL #3]

  (2952) 0x501a2c B	501528

(2943) 0x501a30 LDR	X3, [SP, #184]

(2943) 0x501a34 LDR	X15, [SP, #216]

(2943) 0x501a38 LDR	X1, [SP, #200]

(2943) 0x501a3c LDR	X2, [X3, X13]

(2943) 0x501a40 LDR	X10, [X15, X13]

(2943) 0x501a44 LDR	X14, [SP, #208]

(2943) 0x501a48 LDR	X6, [X1, X13]

(2943) 0x501a4c SUB	X16, X10, X2

(2943) 0x501a50 LDR	X25, [X14, X13]

(2943) 0x501a54 CMP	X12, X16

(2943) 0x501a58 B.GT	501de4

(2943) 0x501a5c CMP	X12, #0

(2943) 0x501a60 B.LE	5016f8

(2943) 0x501a64 MOVZ	X14, #0

(2943) 0x501a68 MOVZ	X3, #0

(2943) 0x501a6c ADD	X12, X21, X12

(2943) 0x501a70 ORR	X15, XZR, X2

(2943) 0x501a74 HINT	#0

(2943) 0x501a78 HINT	#0

(2943) 0x501a7c HINT	#0

  (2947) 0x501a80 LDR	X1, [X28, X21,LSL #3]

  (2947) 0x501a84 CMP	X2, #0

  (2947) 0x501a88 B.LE	501bcc

    (2950) 0x501a8c ANDS	X17, X2, #0x7

    (2950) 0x501a90 MOVZ	X0, #0

    (2950) 0x501a94 B.EQ	501b40

    (2950) 0x501a98 CMP	X17, #1

    (2950) 0x501a9c B.EQ	501b28

    (2950) 0x501aa0 CMP	X17, #2

    (2950) 0x501aa4 B.EQ	501b18

    (2950) 0x501aa8 CMP	X17, #3

    (2950) 0x501aac B.EQ	501b08

    (2950) 0x501ab0 CMP	X17, #4

    (2950) 0x501ab4 B.EQ	501af8

    (2950) 0x501ab8 CMP	X17, #5

    (2950) 0x501abc B.EQ	501ae8

    (2950) 0x501ac0 CMP	X17, #6

    (2950) 0x501ac4 B.EQ	501ad8

    (2950) 0x501ac8 LDR	X30, [X25]

    (2950) 0x501acc CMP	X1, X30

    (2950) 0x501ad0 B.EQ	501c48

    (2950) 0x501ad4 MOVZ	X0, #1

    (2950) 0x501ad8 LDR	X16, [X25, X0,LSL #3]

    (2950) 0x501adc CMP	X1, X16

    (2950) 0x501ae0 B.EQ	501c48

    (2950) 0x501ae4 ADD	X0, X0, #1

    (2950) 0x501ae8 LDR	X17, [X25, X0,LSL #3]

    (2950) 0x501aec CMP	X1, X17

    (2950) 0x501af0 B.EQ	501c48

    (2950) 0x501af4 ADD	X0, X0, #1

    (2950) 0x501af8 LDR	X30, [X25, X0,LSL #3]

    (2950) 0x501afc CMP	X1, X30

    (2950) 0x501b00 B.EQ	501c48

    (2950) 0x501b04 ADD	X0, X0, #1

    (2950) 0x501b08 LDR	X16, [X25, X0,LSL #3]

    (2950) 0x501b0c CMP	X1, X16

    (2950) 0x501b10 B.EQ	501c48

    (2950) 0x501b14 ADD	X0, X0, #1

    (2950) 0x501b18 LDR	X17, [X25, X0,LSL #3]

    (2950) 0x501b1c CMP	X1, X17

    (2950) 0x501b20 B.EQ	501c48

    (2950) 0x501b24 ADD	X0, X0, #1

    (2950) 0x501b28 LDR	X30, [X25, X0,LSL #3]

    (2950) 0x501b2c CMP	X1, X30

    (2950) 0x501b30 B.EQ	501c48

    (2950) 0x501b34 ADD	X0, X0, #1

    (2950) 0x501b38 CMP	X2, X0

    (2950) 0x501b3c B.EQ	501bcc

      (2951) 0x501b40 LDR	X16, [X25, X0,LSL #3]

      (2951) 0x501b44 CMP	X1, X16

      (2951) 0x501b48 B.EQ	501c48

      (2951) 0x501b4c ADD	X0, X0, #1

      (2951) 0x501b50 LDR	X17, [X25, X0,LSL #3]

      (2951) 0x501b54 ORR	X30, XZR, X0

      (2951) 0x501b58 CMP	X1, X17

      (2951) 0x501b5c B.EQ	501c48

      (2951) 0x501b60 ADD	X0, X0, #1

      (2951) 0x501b64 LDR	X16, [X25, X0,LSL #3]

      (2951) 0x501b68 CMP	X1, X16

      (2951) 0x501b6c B.EQ	501c48

      (2951) 0x501b70 ADD	X0, X30, #2

      (2951) 0x501b74 LDR	X17, [X25, X0,LSL #3]

      (2951) 0x501b78 CMP	X1, X17

      (2951) 0x501b7c B.EQ	501c48

      (2951) 0x501b80 ADD	X0, X30, #3

      (2951) 0x501b84 LDR	X16, [X25, X0,LSL #3]

      (2951) 0x501b88 CMP	X1, X16

      (2951) 0x501b8c B.EQ	501c48

      (2951) 0x501b90 ADD	X0, X30, #4

      (2951) 0x501b94 LDR	X17, [X25, X0,LSL #3]

      (2951) 0x501b98 CMP	X1, X17

      (2951) 0x501b9c B.EQ	501c48

      (2951) 0x501ba0 ADD	X0, X30, #5

      (2951) 0x501ba4 LDR	X16, [X25, X0,LSL #3]

      (2951) 0x501ba8 CMP	X1, X16

      (2951) 0x501bac B.EQ	501c48

      (2951) 0x501bb0 ADD	X0, X30, #6

      (2951) 0x501bb4 LDR	X17, [X25, X0,LSL #3]

      (2951) 0x501bb8 CMP	X1, X17

      (2951) 0x501bbc B.EQ	501c48

      (2951) 0x501bc0 ADD	X0, X30, #7

      (2951) 0x501bc4 CMP	X2, X0

      (2951) 0x501bc8 B.NE	501b40

  (2947) 0x501bcc LDR	D3, [X26, X21,LSL #3]

  (2947) 0x501bd0 CMP	X10, X15

  (2947) 0x501bd4 B.LE	501c64

  (2947) 0x501bd8 UBFM	X16, X15, #61, #60

  (2947) 0x501bdc ADD	X15, X15, #1

  (2947) 0x501be0 STR	X1, [X25, X16]

  (2947) 0x501be4 STR	D3, [X6, X16]

  (2947) 0x501be8 ADD	X21, X21, #1

  (2947) 0x501bec CMP	X21, X12

  (2947) 0x501bf0 B.NE	501a80

(2943) 0x501bf4 LDR	X1, [SP, #184]

(2943) 0x501bf8 ADD	X21, X3, X15

(2943) 0x501bfc STR	X21, [X1, X13]

(2943) 0x501c00 CBNZ	X3, 501c78

(2943) 0x501c04 ORR	X21, XZR, X12

(2943) 0x501c08 CBZ	X14, 5016f8

(2943) 0x501c0c ORR	X0, XZR, X14

(2943) 0x501c10 STR	X9, [SP, #112]

(2943) 0x501c14 STP	X4, X5, [SP, #240]

(2943) 0x501c18 STP	X18, X7, [SP, #256]

(2943) 0x501c1c STR	X8, [SP, #272]

(2943) 0x501c20 STR	X11, [SP, #288]

(2943) 0x501c24 BL	524f40

(2943) 0x501c28 LDR	X0, [SP, #112]

(2943) 0x501c2c BL	524f40

(2943) 0x501c30 LDR	X8, [SP, #272]

(2943) 0x501c34 MOVZ	X9, #0

(2943) 0x501c38 LDP	X4, X5, [SP, #240]

(2943) 0x501c3c LDP	X18, X7, [SP, #256]

(2943) 0x501c40 LDR	X11, [SP, #288]

(2943) 0x501c44 B	5016f8

    (2950) 0x501c48 LDR	D4, [X26, X21,LSL #3]

    (2950) 0x501c4c ADD	X21, X21, #1

    (2950) 0x501c50 STR	D4, [X6, X0,LSL #3]

    (2950) 0x501c54 CMP	X21, X12

    (2950) 0x501c58 B.EQ	501bf4

    (2950) 0x501c5c LDR	X1, [X28, X21,LSL #3]

    (2950) 0x501c60 B	501a8c

  (2947) 0x501c64 UBFM	X30, X3, #61, #60

  (2947) 0x501c68 ADD	X3, X3, #1

  (2947) 0x501c6c STR	X1, [X14, X30]

  (2947) 0x501c70 STR	D3, [X9, X30]

  (2947) 0x501c74 B	501be8

(2943) 0x501c78 LDR	X6, [SP, #208]

(2943) 0x501c7c UBFM	X25, X21, #61, #60

(2943) 0x501c80 ORR	X1, XZR, X25

(2943) 0x501c84 STR	X13, [SP, #112]

(2943) 0x501c88 STR	X9, [SP, #272]

(2943) 0x501c8c LDR	X0, [X6, X13]

(2943) 0x501c90 STP	X14, X15, [SP, #240]

(2943) 0x501c94 STP	X3, X12, [SP, #256]

(2943) 0x501c98 STP	X4, X5, [SP, #288]

(2943) 0x501c9c STP	X18, X7, [SP, #304]

(2943) 0x501ca0 STP	X8, X11, [SP, #320]

(2943) 0x501ca4 BL	524ee8

(2943) 0x501ca8 LDR	X14, [SP, #112]

(2943) 0x501cac ORR	X1, XZR, X25

(2943) 0x501cb0 ORR	X9, XZR, X0

(2943) 0x501cb4 LDP	X10, X25, [SP, #200]

(2943) 0x501cb8 LDR	X0, [X10, X14]

(2943) 0x501cbc STR	X9, [X25, X14]

(2943) 0x501cc0 BL	524ee8

(2943) 0x501cc4 LDP	X14, X15, [SP, #240]

(2943) 0x501cc8 ORR	X17, XZR, X0

(2943) 0x501ccc MOVZ	X1, #0

(2943) 0x501cd0 LDP	X12, X9, [SP, #264]

(2943) 0x501cd4 ADD	X0, X0, X15,LSL #3

(2943) 0x501cd8 ADD	X6, X14, #8

(2943) 0x501cdc LDP	X4, X5, [SP, #288]

(2943) 0x501ce0 ADD	X2, X9, #8

(2943) 0x501ce4 SUB	X30, X0, X2

(2943) 0x501ce8 LDP	X18, X7, [SP, #304]

(2943) 0x501cec LDP	X8, X11, [SP, #320]

(2943) 0x501cf0 LDR	X13, [SP, #112]

(2943) 0x501cf4 LDR	X3, [SP, #200]

(2943) 0x501cf8 LDR	X2, [SP, #216]

(2943) 0x501cfc LDR	X16, [X25, X13]

(2943) 0x501d00 UBFM	X25, X15, #61, #60

(2943) 0x501d04 ADD	X10, X25, #8

(2943) 0x501d08 STR	X17, [X3, X13]

(2943) 0x501d0c LDR	X3, [SP, #256]

(2943) 0x501d10 STR	X21, [X2, X13]

(2943) 0x501d14 CNTB	X21, ALL

(2943) 0x501d18 ADD	X13, X16, X10

(2943) 0x501d1c ADD	X15, X16, X15,LSL #3

(2943) 0x501d20 SUB	X10, X21, #16

(2943) 0x501d24 SUB	X2, X0, X13

(2943) 0x501d28 CMP	X2, X30

(2943) 0x501d2c SUB	X21, X15, X6

(2943) 0x501d30 CSEL	X30, X2, X30, #9

(2943) 0x501d34 CMP	X30, X21

(2943) 0x501d38 CSEL	X13, X30, X21, #9

(2943) 0x501d3c CNTD	X2, ALL

(2943) 0x501d40 WHILELO	P7.D, XZR, X3

(2943) 0x501d44 CMP	X13, X10

(2943) 0x501d48 B.LS	501fe0

  (2949) 0x501d4c LD1D	{Z30.D}, P7/Z, [X14, X1,LSL #3]

  (2949) 0x501d50 ST1D	{Z30.D}, P7, [X15, X1,LSL #3]

  (2949) 0x501d54 LD1D	{Z5.D}, P7/Z, [X9, X1,LSL #3]

  (2949) 0x501d58 ST1D	{Z5.D}, P7, [X0, X1,LSL #3]

  (2949) 0x501d5c ADD	X1, X1, X2

  (2949) 0x501d60 WHILELO	P7.D, X1, X3

  (2949) 0x501d64 B.NE	501d4c

(2943) 0x501d68 ORR	X21, XZR, X12

(2943) 0x501d6c B	501c08

0x501d70 MUL	X30, X0, X1

0x501d74 UBFM	X19, X25, #61, #60

0x501d78 STR	XZR, [X21, X19]

0x501d7c ADD	X0, X1, X30

0x501d80 ADD	X27, X30, X22

0x501d84 ADD	X3, X0, X22

0x501d88 ADD	X22, X21, X25,LSL #3

0x501d8c STR	X3, [SP, #104]

0x501d90 CMP	X27, X3

0x501d94 B.LT	501040

0x501d98 STR	X6, [SP, #144]

0x501d9c STP	X7, X8, [SP, #240]

0x501da0 STP	X11, X5, [SP, #256]

0x501da4 STR	X12, [SP, #272]

0x501da8 BL	4102a0

0x501dac LDR	X9, [SP, #144]

0x501db0 LDP	X7, X8, [SP, #240]

0x501db4 LDP	X11, X5, [SP, #256]

0x501db8 LDR	X12, [SP, #272]

0x501dbc CBNZ	X25, 501dc8

0x501dc0 CMP	X26, #0

0x501dc4 B.GT	501188

0x501dc8 LDP	X19, X20, [SP, #16]

0x501dcc LDP	X21, X22, [SP, #32]

0x501dd0 LDP	X23, X24, [SP, #48]

0x501dd4 LDP	X25, X26, [SP, #64]

0x501dd8 LDP	X27, X28, [SP, #80]

0x501ddc LDP	X29, X30, [SP], #336

0x501de0 B	4102a0

(2943) 0x501de4 SUB	X9, X12, X16

(2943) 0x501de8 MOVZ	X1, #8

(2943) 0x501dec STP	X12, X6, [SP, #240]

(2943) 0x501df0 ORR	X0, XZR, X9

(2943) 0x501df4 STR	X9, [SP, #112]

(2943) 0x501df8 STP	X10, X2, [SP, #256]

(2943) 0x501dfc STR	X13, [SP, #272]

(2943) 0x501e00 STP	X4, X5, [SP, #288]

(2943) 0x501e04 STP	X18, X7, [SP, #304]

(2943) 0x501e08 STP	X8, X11, [SP, #320]

(2943) 0x501e0c BL	524ea8

(2943) 0x501e10 ORR	X7, XZR, X0

(2943) 0x501e14 LDR	X0, [SP, #112]

(2943) 0x501e18 MOVZ	X1, #8

(2943) 0x501e1c STR	X7, [SP, #112]

(2943) 0x501e20 BL	524ea8

(2943) 0x501e24 LDP	X12, X6, [SP, #240]

(2943) 0x501e28 ORR	X9, XZR, X0

(2943) 0x501e2c LDP	X10, X2, [SP, #256]

(2943) 0x501e30 LDP	X4, X5, [SP, #288]

(2943) 0x501e34 LDP	X18, X7, [SP, #304]

(2943) 0x501e38 LDP	X8, X11, [SP, #320]

(2943) 0x501e3c LDR	X14, [SP, #112]

(2943) 0x501e40 LDR	X13, [SP, #272]

(2943) 0x501e44 CMP	X12, #0

(2943) 0x501e48 B.GT	501a68

(2943) 0x501e4c LDR	X25, [SP, #184]

(2943) 0x501e50 STR	X2, [X25, X13]

(2943) 0x501e54 B	501c08

0x501e58 STR	X9, [SP, #144]

0x501e5c STP	X7, X8, [SP, #240]

0x501e60 STP	X11, X5, [SP, #256]

0x501e64 STR	X12, [SP, #272]

0x501e68 BL	4102a0

0x501e6c LDUR	X21, [X22, #504]

0x501e70 LDP	X7, X8, [SP, #240]

0x501e74 LDP	X11, X5, [SP, #256]

0x501e78 LDR	X18, [SP, #144]

0x501e7c LDR	X12, [SP, #272]

0x501e80 B	5012c4

(2943) 0x501e84 ADRP	X30,

(2943) 0x501e88 MOVZ	X3, #0

(2943) 0x501e8c LDR	X25, [SP, #240]

(2943) 0x501e90 ADD	X0, X30, #3176

(2943) 0x501e94 MOVZ	X2, #1

(2943) 0x501e98 STR	X13, [SP, #112]

(2943) 0x501e9c MOVZ	X1, #3406

(2943) 0x501ea0 STP	X11, X8, [SP, #248]

(2943) 0x501ea4 STP	X7, X18, [SP, #264]

(2943) 0x501ea8 STP	X5, X4, [SP, #288]

(2943) 0x501eac STP	X14, X15, [SP, #304]

(2943) 0x501eb0 STR	X9, [SP, #320]

(2943) 0x501eb4 BL	5289c0

(2943) 0x501eb8 LDR	X18, [SP, #224]

(2943) 0x501ebc MOVZ	X4, #1

(2943) 0x501ec0 LDR	X5, [X18, #224]

(2943) 0x501ec4 LDADD	X4, X1, [X5]

(2943) 0x501ec8 LDP	X10, X5, [SP, #280]

(2943) 0x501ecc LDP	X11, X8, [SP, #248]

(2943) 0x501ed0 LDP	X7, X18, [SP, #264]

(2943) 0x501ed4 LDP	X4, X14, [SP, #296]

(2943) 0x501ed8 LDP	X15, X9, [SP, #312]

(2943) 0x501edc LDR	X13, [SP, #112]

(2943) 0x501ee0 CBNZ	X10, 501f04

(2943) 0x501ee4 ORR	X16, XZR, X21

(2943) 0x501ee8 LDP	X21, X17, [X11, #56]

(2943) 0x501eec ADD	X0, X21, X13

(2943) 0x501ef0 ADD	X6, X17, X13

(2943) 0x501ef4 B	50153c

0x501ef8 LDR	X0, [X1], #8

0x501efc STR	X0, [X22]

0x501f00 B	501098

(2943) 0x501f04 ADRP	X16,

(2943) 0x501f08 ORR	X1, XZR, X25

(2943) 0x501f0c STR	X15, [SP, #112]

(2943) 0x501f10 ADD	X0, X16, #3336

(2943) 0x501f14 STP	X14, X13, [SP, #240]

(2943) 0x501f18 STP	X9, X4, [SP, #256]

(2943) 0x501f1c STR	X5, [SP, #272]

(2943) 0x501f20 STP	X18, X7, [SP, #288]

(2943) 0x501f24 STP	X8, X11, [SP, #304]

(2943) 0x501f28 BL	5250e0

(2943) 0x501f2c LDP	X8, X11, [SP, #304]

(2943) 0x501f30 ORR	X16, XZR, X21

(2943) 0x501f34 LDP	X14, X2, [SP, #240]

(2943) 0x501f38 LDP	X12, X1, [X11, #56]

(2943) 0x501f3c LDP	X9, X4, [SP, #256]

(2943) 0x501f40 ADD	X0, X12, X2

(2943) 0x501f44 ADD	X6, X1, X2

(2943) 0x501f48 LDP	X18, X7, [SP, #288]

(2943) 0x501f4c LDR	X15, [SP, #112]

(2943) 0x501f50 LDR	X5, [SP, #272]

(2943) 0x501f54 B	50153c

(2943) 0x501f58 ADRP	X12,

(2943) 0x501f5c MOVZ	X3, #0

(2943) 0x501f60 LDR	X25, [SP, #240]

(2943) 0x501f64 ADD	X0, X12, #3176

(2943) 0x501f68 MOVZ	X2, #1

(2943) 0x501f6c STR	X13, [SP, #112]

(2943) 0x501f70 MOVZ	X1, #3440

(2943) 0x501f74 STP	X11, X8, [SP, #248]

(2943) 0x501f78 STP	X7, X18, [SP, #264]

(2943) 0x501f7c STP	X5, X4, [SP, #288]

(2943) 0x501f80 STP	X14, X15, [SP, #304]

(2943) 0x501f84 STR	X9, [SP, #320]

(2943) 0x501f88 BL	5289c0

(2943) 0x501f8c LDR	X8, [SP, #224]

(2943) 0x501f90 MOVZ	X7, #1

(2943) 0x501f94 LDR	X11, [X8, #224]

(2943) 0x501f98 LDADD	X7, X1, [X11]

(2943) 0x501f9c LDP	X6, X5, [SP, #280]

(2943) 0x501fa0 LDP	X11, X8, [SP, #248]

(2943) 0x501fa4 LDP	X7, X18, [SP, #264]

(2943) 0x501fa8 LDP	X4, X14, [SP, #296]

(2943) 0x501fac LDP	X15, X9, [SP, #312]

(2943) 0x501fb0 LDR	X13, [SP, #112]

(2943) 0x501fb4 CBZ	X6, 501ee4

(2943) 0x501fb8 ADRP	X3,

(2943) 0x501fbc ORR	X1, XZR, X25

(2943) 0x501fc0 STR	X15, [SP, #112]

(2943) 0x501fc4 ADD	X0, X3, #3376

(2943) 0x501fc8 STP	X14, X13, [SP, #240]

(2943) 0x501fcc STP	X9, X4, [SP, #256]

(2943) 0x501fd0 STR	X5, [SP, #272]

(2943) 0x501fd4 STP	X18, X7, [SP, #288]

(2943) 0x501fd8 STP	X8, X11, [SP, #304]

(2943) 0x501fdc B	501f28

(2943) 0x501fe0 ANDS	X10, X3, #0x7

(2943) 0x501fe4 B.EQ	5020ac

(2943) 0x501fe8 CMP	X10, #1

(2943) 0x501fec B.EQ	502090

(2943) 0x501ff0 CMP	X10, #2

(2943) 0x501ff4 B.EQ	50207c

(2943) 0x501ff8 CMP	X10, #3

(2943) 0x501ffc B.EQ	502068

(2943) 0x502000 CMP	X10, #4

(2943) 0x502004 B.EQ	502054

(2943) 0x502008 CMP	X10, #5

(2943) 0x50200c B.EQ	502040

(2943) 0x502010 CMP	X10, #6

(2943) 0x502014 B.EQ	50202c

(2943) 0x502018 LDR	D6, [X9]

(2943) 0x50201c MOVZ	X1, #1

(2943) 0x502020 LDR	X6, [X14]

(2943) 0x502024 STR	X6, [X16, X25]

(2943) 0x502028 STR	D6, [X17, X25]

(2943) 0x50202c LDR	D7, [X9, X1,LSL #3]

(2943) 0x502030 LDR	X17, [X14, X1,LSL #3]

(2943) 0x502034 STR	X17, [X15, X1,LSL #3]

(2943) 0x502038 STR	D7, [X0, X1,LSL #3]

(2943) 0x50203c ADD	X1, X1, #1

(2943) 0x502040 LDR	D16, [X9, X1,LSL #3]

(2943) 0x502044 LDR	X16, [X14, X1,LSL #3]

(2943) 0x502048 STR	X16, [X15, X1,LSL #3]

(2943) 0x50204c STR	D16, [X0, X1,LSL #3]

(2943) 0x502050 ADD	X1, X1, #1

(2943) 0x502054 LDR	D17, [X9, X1,LSL #3]

(2943) 0x502058 LDR	X25, [X14, X1,LSL #3]

(2943) 0x50205c STR	X25, [X15, X1,LSL #3]

(2943) 0x502060 STR	D17, [X0, X1,LSL #3]

(2943) 0x502064 ADD	X1, X1, #1

(2943) 0x502068 LDR	D18, [X9, X1,LSL #3]

(2943) 0x50206c LDR	X21, [X14, X1,LSL #3]

(2943) 0x502070 STR	X21, [X15, X1,LSL #3]

(2943) 0x502074 STR	D18, [X0, X1,LSL #3]

(2943) 0x502078 ADD	X1, X1, #1

(2943) 0x50207c LDR	D19, [X9, X1,LSL #3]

(2943) 0x502080 LDR	X30, [X14, X1,LSL #3]

(2943) 0x502084 STR	X30, [X15, X1,LSL #3]

(2943) 0x502088 STR	D19, [X0, X1,LSL #3]

(2943) 0x50208c ADD	X1, X1, #1

(2943) 0x502090 LDR	D20, [X9, X1,LSL #3]

(2943) 0x502094 LDR	X13, [X14, X1,LSL #3]

(2943) 0x502098 STR	X13, [X15, X1,LSL #3]

(2943) 0x50209c STR	D20, [X0, X1,LSL #3]

(2943) 0x5020a0 ADD	X1, X1, #1

(2943) 0x5020a4 CMP	X1, X3

(2943) 0x5020a8 B.EQ	502154

  (2948) 0x5020ac LDR	X10, [X14, X1,LSL #3]

  (2948) 0x5020b0 ADD	X2, X1, #1

  (2948) 0x5020b4 ADD	X17, X1, #2

  (2948) 0x5020b8 ADD	X16, X1, #3

  (2948) 0x5020bc ADD	X25, X1, #4

  (2948) 0x5020c0 LDR	D21, [X9, X1,LSL #3]

  (2948) 0x5020c4 STR	X10, [X15, X1,LSL #3]

  (2948) 0x5020c8 ADD	X10, X1, #5

  (2948) 0x5020cc LDR	X6, [X14, X2,LSL #3]

  (2948) 0x5020d0 STR	D21, [X0, X1,LSL #3]

  (2948) 0x5020d4 LDR	D22, [X9, X2,LSL #3]

  (2948) 0x5020d8 STR	X6, [X15, X2,LSL #3]

  (2948) 0x5020dc ADD	X6, X1, #6

  (2948) 0x5020e0 LDR	X21, [X14, X17,LSL #3]

  (2948) 0x5020e4 STR	D22, [X0, X2,LSL #3]

  (2948) 0x5020e8 ADD	X2, X1, #7

  (2948) 0x5020ec ADD	X1, X1, #8

  (2948) 0x5020f0 LDR	D23, [X9, X17,LSL #3]

  (2948) 0x5020f4 STR	X21, [X15, X17,LSL #3]

  (2948) 0x5020f8 LDR	X30, [X14, X16,LSL #3]

  (2948) 0x5020fc STR	D23, [X0, X17,LSL #3]

  (2948) 0x502100 LDR	D24, [X9, X16,LSL #3]

  (2948) 0x502104 STR	X30, [X15, X16,LSL #3]

  (2948) 0x502108 LDR	X13, [X14, X25,LSL #3]

  (2948) 0x50210c STR	D24, [X0, X16,LSL #3]

  (2948) 0x502110 LDR	D25, [X9, X25,LSL #3]

  (2948) 0x502114 STR	X13, [X15, X25,LSL #3]

  (2948) 0x502118 LDR	X16, [X14, X10,LSL #3]

  (2948) 0x50211c STR	D25, [X0, X25,LSL #3]

  (2948) 0x502120 LDR	D26, [X9, X10,LSL #3]

  (2948) 0x502124 STR	X16, [X15, X10,LSL #3]

  (2948) 0x502128 LDR	X17, [X14, X6,LSL #3]

  (2948) 0x50212c STR	D26, [X0, X10,LSL #3]

  (2948) 0x502130 LDR	D27, [X9, X6,LSL #3]

  (2948) 0x502134 STR	X17, [X15, X6,LSL #3]

  (2948) 0x502138 LDR	X25, [X14, X2,LSL #3]

  (2948) 0x50213c STR	D27, [X0, X6,LSL #3]

  (2948) 0x502140 LDR	D28, [X9, X2,LSL #3]

  (2948) 0x502144 STR	X25, [X15, X2,LSL #3]

  (2948) 0x502148 STR	D28, [X0, X2,LSL #3]

  (2948) 0x50214c CMP	X1, X3

  (2948) 0x502150 B.NE	5020ac

(2943) 0x502154 ORR	X21, XZR, X12

(2943) 0x502158 B	501c0c

(2943) 0x50215c ORR	X16, XZR, X21

(2943) 0x502160 B	50153c

Coverage (%)	Name	Source Location	Module
►97.67+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.33+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_IJMatrixSetValuesOMPParC[...]	IJMatrix_parcsr.c:3509	exec
○	BuildIJLaplacian27pt	amg.c:2267	exec
○	main	amg.c:274	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	IJMatrix_parcsr.c:3240-3500
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3322,3329-3353,3359-3368,3376-3412,3422-3446,3454-3458,3466-3484,3500.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 30% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 48.67 to 15.46 cycles (3.15x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256
unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3278
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3286
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3278
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3286

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	256
nb uops	256
loop length	1024
used w registers	0
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	91

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.00 cycles
front end	32.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	17.50	17.50	22.50	22.50	22.50	22.50	0.00	0.00	0.00	0.00	48.67	48.67	48.67	31.00	31.00
cycles	17.50	17.50	22.50	22.50	22.50	22.50	0.00	0.00	0.00	0.00	48.67	48.67	48.67	31.00	31.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	32.00
Dispatch	48.67
DIV/SQRT	5.00-20.00
Overall L1	48.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	33%
store	31%
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 48.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 500f20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #688]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X12, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X12, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X28, X5, [X12, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X7, [X12, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X0, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [X12, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X12, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X12, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X12, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X3, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X12, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X4, [SP, #200]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #216]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X12, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X23, [X12, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X20, [X12, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X18, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X12, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X10, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X12, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X12, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X12, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X12, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X15, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X12, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X25, [X12, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [X12, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X19, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X24, [X12, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X25, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [X12, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X27, [SP, #280]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b20 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
BL 527b40 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X1, X22, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
LDR X12, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X6, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X22, X1, X19, X22	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 501d70 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X27, X1, X0, X0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X2, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X19, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X22, X21, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X21, X19]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X3, X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X3, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X27, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 501d98 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X1, X4, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X9, X4, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X18, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X13, X18, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X15, X14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5010e8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5010d4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5010c8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5010bc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5010b0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5010a4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 501ef8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xfd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 501158 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X6, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X25, 501e58 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 50129c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X21, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X25, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X6, X25, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X22, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X15, X22, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X26, X0, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B.EQ 501238 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 501224 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 501218 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50120c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 501200 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5011f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5011e8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50129c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 501558 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x638>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVN X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X25, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X17, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X15, X25, #1, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X5, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X14, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X12, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X30, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X30, X15,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X6, X3, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #336	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #336	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X30, X0, X1	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X19, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X21, X19]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X27, X30, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X22, X21, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X27, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 501040 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X6, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X25, 501dc8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xea8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GT 501188 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #336	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X21, [X22, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X18, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 5012c4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 501098 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	IJMatrix_parcsr.c:3240-3500
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256
unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3278
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3286
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3278
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3286

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	256
nb uops	256
loop length	1024
used w registers	0
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	91

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.00 cycles
front end	32.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	17.50	17.50	22.50	22.50	22.50	22.50	0.00	0.00	0.00	0.00	48.67	48.67	48.67	31.00	31.00
cycles	17.50	17.50	22.50	22.50	22.50	22.50	0.00	0.00	0.00	0.00	48.67	48.67	48.67	31.00	31.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	32.00
Dispatch	48.67
DIV/SQRT	5.00-20.00
Overall L1	48.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	33%
store	31%
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 48.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 500f20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #688]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X12, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X12, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X28, X5, [X12, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X7, [X12, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X0, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [X12, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X12, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X12, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X12, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X12, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X3, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X12, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X4, [SP, #200]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #216]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X12, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X23, [X12, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X20, [X12, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X18, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X12, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X10, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X12, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X12, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X12, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X12, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X15, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X12, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X25, [X12, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [X12, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X19, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X24, [X12, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X25, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [X12, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X27, [SP, #280]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b20 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
BL 527b40 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X1, X22, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
LDR X12, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X6, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X22, X1, X19, X22	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 501d70 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X27, X1, X0, X0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X2, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X19, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X22, X21, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X21, X19]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X3, X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X3, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X27, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 501d98 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X1, X4, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X9, X4, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X18, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X13, X18, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X15, X14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5010e8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5010d4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5010c8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5010bc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5010b0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5010a4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 501ef8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xfd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 501158 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X6, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X25, 501e58 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 50129c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X21, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X25, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X6, X25, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X22, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X15, X22, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X26, X0, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B.EQ 501238 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 501224 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 501218 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50120c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 501200 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5011f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5011e8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X18, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X18, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50129c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 501558 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x638>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVN X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X25, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X17, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X15, X25, #1, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X5, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X14, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X12, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X30, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X30, X15,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X6, X3, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #336	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #336	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X30, X0, X1	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X19, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X21, X19]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X27, X30, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X22, X21, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X27, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 501040 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X6, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X25, 501dc8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xea8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GT 501188 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #336	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X21, [X22, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X7, X8, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X5, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X18, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 5012c4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 501098 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1–	0.18	0.08
▼Loop 2943 - IJMatrix_parcsr.c:3291-3500 - exec–	0.04	0.01
▼Loop 2952 - IJMatrix_parcsr.c:3383-3484 - exec–	0.14	0.04
○Loop 2953 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 2954 - IJMatrix_parcsr.c:3388-3390 - exec	0.00	0.00
○Loop 2949 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
▼Loop 2947 - IJMatrix_parcsr.c:3316-3341 - exec–	0.00	0.00
▼Loop 2950 - IJMatrix_parcsr.c:3316-3341 - exec–	0.00	0.00
○Loop 2951 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
○Loop 2948 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
▼Loop 2944 - IJMatrix_parcsr.c:3470-3500 - exec–	0.00	0.00
▼Loop 2946 - IJMatrix_parcsr.c:3475-3484 - exec–	0.00	0.00
○Loop 2945 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
○Loop 2942 - IJMatrix_parcsr.c:3274-3275 - exec	0.01	0.00
○Loop 2955 - IJMatrix_parcsr.c:3282-3283 - exec	0.00	0.00

Report Configuration

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Matching between your function (in the source code) and the binary function

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Vector efficiency ratios

Cycles and memory resources usage

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ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code