OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace._omp

	Function: hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6	Module: exec	Source: csr_matvec.c:243-404 [...]	Coverage (incl. loops): 17.91% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 243 - 404

--------------------------------------------------------------------------------

243: #pragma omp parallel private(i,jj,tempx)

244: #endif

245:       {

246:       HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

247:       HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

248:       hypre_assert(iBegin <= iEnd);

249:       hypre_assert(iBegin >= 0 && iBegin <= num_rows);

250:       hypre_assert(iEnd >= 0 && iEnd <= num_rows);

251:

252:       if (0 == temp)

253:       {

254:          if (1 == alpha) // JSP: a common path

255:          {

256:             for (i = iBegin; i < iEnd; i++)

257:             {

258:                tempx = 0.0;

259:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

260:                {

261:                   tempx += A_data[jj] * x_data[A_j[jj]];

262:                }

263:                y_data[i] = tempx;

264:             }

265:          } // y = A*x

266:          else if (-1 == alpha)

267:          {

268:             for (i = iBegin; i < iEnd; i++)

269:             {

270:                tempx = 0.0;

271:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

272:                {

273:                   tempx -= A_data[jj] * x_data[A_j[jj]];

274:                }

275:                y_data[i] = tempx;

276:             }

277:          } // y = -A*x

278:          else

279:          {

280:             for (i = iBegin; i < iEnd; i++)

281:             {

282:                tempx = 0.0;

283:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

284:                {

285:                   tempx += A_data[jj] * x_data[A_j[jj]];

286:                }

287:                y_data[i] = alpha*tempx;

288:             }

289:          } // y = alpha*A*x

290:       } // temp == 0

291:       else if (-1 == temp) // beta == -alpha

292:       {

293:          if (1 == alpha) // JSP: a common path

294:          {

295:             for (i = iBegin; i < iEnd; i++)

296:             {

297:                tempx = -b_data[i];

298:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

299:                {

300:                   tempx += A_data[jj] * x_data[A_j[jj]];

301:                }

302:                y_data[i] = tempx;

303:             }

304:          } // y = A*x - y

305:          else if (-1 == alpha) // JSP: a common path

306:          {

307:             for (i = iBegin; i < iEnd; i++)

308:             {

309:                tempx = b_data[i];

310:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

311:                {

312:                   tempx -= A_data[jj] * x_data[A_j[jj]];

313:                }

314:                y_data[i] = tempx;

315:             }

316:          } // y = -A*x + y

317:          else

318:          {

319:             for (i = iBegin; i < iEnd; i++)

320:             {

321:                tempx = -b_data[i];

322:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

323:                {

324:                   tempx += A_data[jj] * x_data[A_j[jj]];

325:                }

326:                y_data[i] = alpha*tempx;

327:             }

328:          } // y = alpha*(A*x - y)

329:       } // temp == -1

330:       else if (1 == temp)

331:       {

332:          if (1 == alpha) // JSP: a common path

333:          {

334:             for (i = iBegin; i < iEnd; i++)

335:             {

336:                tempx = b_data[i];

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

340:                }

341:                y_data[i] = tempx;

342:             }

343:          } // y = A*x + y

344:          else if (-1 == alpha)

345:          {

346:             for (i = iBegin; i < iEnd; i++)

347:             {

348:                tempx = -b_data[i];

349:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

350:                {

351:                   tempx -= A_data[jj] * x_data[A_j[jj]];

352:                }

353:                y_data[i] = tempx;

354:             }

355:          } // y = -A*x - y

356:          else

357:          {

358:             for (i = iBegin; i < iEnd; i++)

359:             {

360:                tempx = b_data[i];

361:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

362:                {

363:                   tempx += A_data[jj] * x_data[A_j[jj]];

364:                }

365:                y_data[i] = alpha*tempx;

[...]

371:          if (1 == alpha) // JSP: a common path

372:          {

373:             for (i = iBegin; i < iEnd; i++)

374:             {

375:                tempx = b_data[i]*temp;

376:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

377:                {

378:                   tempx += A_data[jj] * x_data[A_j[jj]];

379:                }

380:                y_data[i] = tempx;

381:             }

382:          } // y = A*x + temp*y

383:          else if (-1 == alpha)

384:          {

385:             for (i = iBegin; i < iEnd; i++)

386:             {

387:                tempx = -b_data[i]*temp;

388:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

389:                {

390:                   tempx -= A_data[jj] * x_data[A_j[jj]];

391:                }

392:                y_data[i] = tempx;

393:             }

394:          } // y = -A*x - temp*y

395:          else

396:          {

397:             for (i = iBegin; i < iEnd; i++)

398:             {

399:                tempx = b_data[i]*temp;

400:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

401:                {

402:                   tempx += A_data[jj] * x_data[A_j[jj]];

403:                }

404:                y_data[i] = alpha*tempx;

0x518f00 STP	X29, X30, [SP, #912]!

0x518f04 ORR	X1, XZR, X0

0x518f08 ADD	X29, SP, #0

0x518f0c STP	X19, X20, [SP, #16]

0x518f10 STP	X21, X22, [SP, #32]

0x518f14 STP	X23, X24, [SP, #48]

0x518f18 STP	X25, X26, [SP, #64]

0x518f1c STP	D14, D15, [SP, #96]

0x518f20 LDP	X21, X25, [X0, #8]

0x518f24 LDP	X22, X24, [X1, #24]

0x518f28 LDP	X19, X26, [X1, #48]

0x518f2c LDR	D14, [X0]

0x518f30 ORR	X0, XZR, X21

0x518f34 LDR	D15, [X1, #72]

0x518f38 LDR	X23, [X1, #64]

0x518f3c STR	X27, [SP, #80]

0x518f40 LDR	X27, [X1, #40]

0x518f44 BL	517ba4

0x518f48 ORR	X20, XZR, X0

0x518f4c ORR	X0, XZR, X21

0x518f50 BL	517c48

0x518f54 ORR	X21, XZR, X0

0x518f58 CMP	X20, X0

0x518f5c B.GT	519288

0x518f60 CMP	X20, #0

0x518f64 CCMP	X27, X20, #1, #10

0x518f68 B.LT	519250

0x518f6c CMP	X21, #0

0x518f70 CCMP	X27, X21, #1, #10

0x518f74 B.LT	519218

0x518f78 FCMP	D15, #0

0x518f7c B.EQ	519034

0x518f80 FMOV	D31, #-1.0000000

0x518f84 FCMP	D15, D31

0x518f88 B.NE	51917c

0x518f8c FMOV	D26, #1.0000000

0x518f90 FCMP	D14, D26

0x518f94 B.EQ	5192c0

0x518f98 FCMP	D14, D31

0x518f9c B.EQ	5194f4

0x518fa0 CMP	X20, X21

0x518fa4 B.GE	519014

0x518fa8 ADD	X30, X22, #8

0x518fac CNTD	X27, ALL

(3245) 0x518fb0 LDR	D2, [X26, X20,LSL #3]

(3245) 0x518fb4 LDR	X4, [X22, X20,LSL #3]

(3245) 0x518fb8 LDR	X2, [X30, X20,LSL #3]

(3245) 0x518fbc FNEG	D27, D2

(3245) 0x518fc0 CMP	X4, X2

(3245) 0x518fc4 B.GE	519000

(3245) 0x518fc8 ADD	X5, X25, X4,LSL #3

(3245) 0x518fcc MOVZ	X1, #0

(3245) 0x518fd0 SUB	X6, X2, X4

(3245) 0x518fd4 ADD	X7, X24, X4,LSL #3

(3245) 0x518fd8 WHILELO	P7.D, XZR, X6

(3245) 0x518fdc HINT	#0

  (3246) 0x518fe0 LD1D	{Z25.D}, P7/Z, [X7, X1,LSL #3]

  (3246) 0x518fe4 LD1D	{Z3.D}, P7/Z, [X5, X1,LSL #3]

  (3246) 0x518fe8 LD1D	{Z23.D}, P7/Z, [X19, Z25.D,LSL #3]

  (3246) 0x518fec ADD	X1, X1, X27

  (3246) 0x518ff0 FMUL	Z3.D, P7/M, Z3.D, Z23.D

  (3246) 0x518ff4 FADDA	D27, P7, D27, Z3.D

  (3246) 0x518ff8 WHILELO	P7.D, X1, X6

  (3246) 0x518ffc B.NE	518fe0

(3245) 0x519000 FMUL	D24, D14, D27

(3245) 0x519004 STR	D24, [X23, X20,LSL #3]

(3245) 0x519008 ADD	X20, X20, #1

(3245) 0x51900c CMP	X21, X20

(3245) 0x519010 B.NE	518fb0

0x519014 LDR	X27, [SP, #80]

0x519018 LDP	X19, X20, [SP, #16]

0x51901c LDP	X21, X22, [SP, #32]

0x519020 LDP	X23, X24, [SP, #48]

0x519024 LDP	X25, X26, [SP, #64]

0x519028 LDP	D14, D15, [SP, #96]

0x51902c LDP	X29, X30, [SP], #112

0x519030 RET

0x519034 FMOV	D5, #1.0000000

0x519038 FCMP	D14, D5

0x51903c B.NE	5190d8

0x519040 CMP	X20, X21

0x519044 B.GE	519014

0x519048 ADD	X16, X22, #8

0x51904c LDR	X18, [X22, X20,LSL #3]

0x519050 CNTD	X17, ALL

0x519054 LDR	X30, [X16, X20,LSL #3]

0x519058 CMP	X18, X30

0x51905c B.GE	5190c0

  (3227) 0x519060 MOVI	D27, #0

  (3227) 0x519064 ADD	X27, X25, X18,LSL #3

  (3227) 0x519068 MOVZ	X6, #0

  (3227) 0x51906c ADD	X4, X24, X18,LSL #3

  (3227) 0x519070 SUB	X26, X30, X18

  (3227) 0x519074 WHILELO	P5.D, XZR, X26

  (3227) 0x519078 HINT	#0

  (3227) 0x51907c HINT	#0

    (3226) 0x519080 LD1D	{Z25.D}, P5/Z, [X4, X6,LSL #3]

    (3226) 0x519084 LD1D	{Z2.D}, P5/Z, [X27, X6,LSL #3]

    (3226) 0x519088 LD1D	{Z3.D}, P5/Z, [X19, Z25.D,LSL #3]

    (3226) 0x51908c ADD	X6, X6, X17

    (3226) 0x519090 FMUL	Z2.D, P5/M, Z2.D, Z3.D

    (3226) 0x519094 FADDA	D27, P5, D27, Z2.D

    (3226) 0x519098 WHILELO	P5.D, X6, X26

    (3226) 0x51909c B.NE	519080

  (3227) 0x5190a0 STR	D27, [X23, X20,LSL #3]

  (3227) 0x5190a4 ADD	X20, X20, #1

  (3227) 0x5190a8 CMP	X21, X20

  (3227) 0x5190ac B.EQ	519014

  (3227) 0x5190b0 LDR	X18, [X22, X20,LSL #3]

  (3227) 0x5190b4 LDR	X30, [X16, X20,LSL #3]

  (3227) 0x5190b8 CMP	X18, X30

  (3227) 0x5190bc B.LT	519060

(3228) 0x5190c0 MOVI	D27, #0

(3228) 0x5190c4 STR	D27, [X23, X20,LSL #3]

(3228) 0x5190c8 ADD	X20, X20, #1

(3228) 0x5190cc CMP	X21, X20

(3228) 0x5190d0 B.NE	5190b0

0x5190d4 B	519014

0x5190d8 FMOV	D6, #-1.0000000

0x5190dc FCMP	D14, D6

0x5190e0 B.NE	5193e4

0x5190e4 CMP	X20, X21

0x5190e8 B.GE	519014

0x5190ec ADD	X10, X22, #8

0x5190f0 LDR	X12, [X22, X20,LSL #3]

0x5190f4 CNTD	X11, ALL

0x5190f8 PTRUE	P3.B, ALL

0x5190fc LDR	X13, [X10, X20,LSL #3]

0x519100 CMP	X12, X13

0x519104 B.GE	519164

  (3224) 0x519108 MOVI	D14, #0

  (3224) 0x51910c ADD	X3, X25, X12,LSL #3

  (3224) 0x519110 MOVZ	X15, #0

  (3224) 0x519114 ADD	X0, X24, X12,LSL #3

  (3224) 0x519118 SUB	X14, X13, X12

  (3224) 0x51911c WHILELO	P4.D, XZR, X14

    (3223) 0x519120 LD1D	{Z0.D}, P4/Z, [X0, X15,LSL #3]

    (3223) 0x519124 LD1D	{Z28.D}, P4/Z, [X3, X15,LSL #3]

    (3223) 0x519128 LD1D	{Z26.D}, P4/Z, [X19, Z0.D,LSL #3]

    (3223) 0x51912c ADD	X15, X15, X11

    (3223) 0x519130 FMUL	Z28.D, P4/M, Z28.D, Z26.D

    (3223) 0x519134 FNEG	Z28.D, P3/M, Z28.D

    (3223) 0x519138 FADDA	D14, P4, D14, Z28.D

    (3223) 0x51913c WHILELO	P4.D, X15, X14

    (3223) 0x519140 B.NE	519120

  (3224) 0x519144 STR	D14, [X23, X20,LSL #3]

  (3224) 0x519148 ADD	X20, X20, #1

  (3224) 0x51914c CMP	X21, X20

  (3224) 0x519150 B.EQ	519014

  (3224) 0x519154 LDR	X12, [X22, X20,LSL #3]

  (3224) 0x519158 LDR	X13, [X10, X20,LSL #3]

  (3224) 0x51915c CMP	X12, X13

  (3224) 0x519160 B.LT	519108

(3225) 0x519164 MOVI	D14, #0

(3225) 0x519168 STR	D14, [X23, X20,LSL #3]

(3225) 0x51916c ADD	X20, X20, #1

(3225) 0x519170 CMP	X21, X20

(3225) 0x519174 B.NE	519154

0x519178 B	519014

0x51917c FMOV	D30, #1.0000000

0x519180 FCMP	D15, D30

0x519184 B.NE	519350

0x519188 FCMP	D14, D30

0x51918c B.EQ	519480

0x519190 FCMP	D14, D31

0x519194 B.NE	5195e0

0x519198 CMP	X20, X21

0x51919c B.GE	519014

0x5191a0 ADD	X5, X22, #8

0x5191a4 CNTD	X6, ALL

0x5191a8 PTRUE	P3.B, ALL

(3239) 0x5191ac LDR	D6, [X26, X20,LSL #3]

(3239) 0x5191b0 LDR	X7, [X22, X20,LSL #3]

(3239) 0x5191b4 LDR	X8, [X5, X20,LSL #3]

(3239) 0x5191b8 FNEG	D14, D6

(3239) 0x5191bc CMP	X7, X8

(3239) 0x5191c0 B.GE	519204

(3239) 0x5191c4 ADD	X3, X25, X7,LSL #3

(3239) 0x5191c8 MOVZ	X0, #0

(3239) 0x5191cc SUB	X9, X8, X7

(3239) 0x5191d0 ADD	X10, X24, X7,LSL #3

(3239) 0x5191d4 WHILELO	P4.D, XZR, X9

(3239) 0x5191d8 HINT	#0

(3239) 0x5191dc HINT	#0

  (3240) 0x5191e0 LD1D	{Z15.D}, P4/Z, [X10, X0,LSL #3]

  (3240) 0x5191e4 LD1D	{Z31.D}, P4/Z, [X3, X0,LSL #3]

  (3240) 0x5191e8 LD1D	{Z30.D}, P4/Z, [X19, Z15.D,LSL #3]

  (3240) 0x5191ec ADD	X0, X0, X6

  (3240) 0x5191f0 FMUL	Z31.D, P4/M, Z31.D, Z30.D

  (3240) 0x5191f4 FNEG	Z31.D, P3/M, Z31.D

  (3240) 0x5191f8 FADDA	D14, P4, D14, Z31.D

  (3240) 0x5191fc WHILELO	P4.D, X0, X9

  (3240) 0x519200 B.NE	5191e0

(3239) 0x519204 STR	D14, [X23, X20,LSL #3]

(3239) 0x519208 ADD	X20, X20, #1

(3239) 0x51920c CMP	X21, X20

(3239) 0x519210 B.NE	5191ac

0x519214 B	519014

0x519218 ADRP	X9,

0x51921c ADRP	X10,

0x519220 ADRP	X11,

0x519224 ADD	X2, X9, #1312

0x519228 ADD	X1, X10, #2216

0x51922c LDR	X0, [X11, #1280]

0x519230 BL	525180

0x519234 ADRP	X12,

0x519238 MOVZ	X3, #0

0x51923c ADD	X0, X12, #1344

0x519240 MOVZ	X2, #1

0x519244 MOVZ	X1, #250

0x519248 BL	5289c0

0x51924c B	518f78

0x519250 ADRP	X5,

0x519254 ADRP	X6,

0x519258 ADRP	X7,

0x51925c ADD	X2, X5, #1432

0x519260 ADD	X1, X6, #2216

0x519264 LDR	X0, [X7, #1280]

0x519268 BL	525180

0x51926c ADRP	X8,

0x519270 MOVZ	X3, #0

0x519274 ADD	X0, X8, #1344

0x519278 MOVZ	X2, #1

0x51927c MOVZ	X1, #249

0x519280 BL	5289c0

0x519284 B	518f6c

0x519288 ADRP	X3,

0x51928c ADRP	X2,

0x519290 ADRP	X0,

0x519294 ADD	X1, X3, #2216

0x519298 ADD	X2, X2, #872

0x51929c LDR	X0, [X0, #1280]

0x5192a0 BL	525180

0x5192a4 ADRP	X4,

0x5192a8 MOVZ	X3, #0

0x5192ac ADD	X0, X4, #1344

0x5192b0 MOVZ	X2, #1

0x5192b4 MOVZ	X1, #248

0x5192b8 BL	5289c0

0x5192bc B	518f60

0x5192c0 CMP	X20, X21

0x5192c4 B.GE	519014

0x5192c8 ADD	X14, X22, #8

0x5192cc CNTD	X15, ALL

(3241) 0x5192d0 LDR	D20, [X26, X20,LSL #3]

(3241) 0x5192d4 LDR	X16, [X22, X20,LSL #3]

(3241) 0x5192d8 LDR	X17, [X14, X20,LSL #3]

(3241) 0x5192dc FNEG	D7, D20

(3241) 0x5192e0 CMP	X16, X17

(3241) 0x5192e4 B.GE	519320

(3241) 0x5192e8 ADD	X18, X25, X16,LSL #3

(3241) 0x5192ec MOVZ	X4, #0

(3241) 0x5192f0 SUB	X30, X17, X16

(3241) 0x5192f4 ADD	X27, X24, X16,LSL #3

(3241) 0x5192f8 WHILELO	P1.D, XZR, X30

(3241) 0x5192fc HINT	#0

  (3242) 0x519300 LD1D	{Z17.D}, P1/Z, [X27, X4,LSL #3]

  (3242) 0x519304 LD1D	{Z18.D}, P1/Z, [X18, X4,LSL #3]

  (3242) 0x519308 LD1D	{Z16.D}, P1/Z, [X19, Z17.D,LSL #3]

  (3242) 0x51930c ADD	X4, X4, X15

  (3242) 0x519310 FMUL	Z18.D, P1/M, Z18.D, Z16.D

  (3242) 0x519314 FADDA	D7, P1, D7, Z18.D

  (3242) 0x519318 WHILELO	P1.D, X4, X30

  (3242) 0x51931c B.NE	519300

(3241) 0x519320 STR	D7, [X23, X20,LSL #3]

(3241) 0x519324 ADD	X20, X20, #1

(3241) 0x519328 CMP	X21, X20

(3241) 0x51932c B.NE	5192d0

0x519330 LDR	X27, [SP, #80]

0x519334 LDP	X19, X20, [SP, #16]

0x519338 LDP	X21, X22, [SP, #32]

0x51933c LDP	X23, X24, [SP, #48]

0x519340 LDP	X25, X26, [SP, #64]

0x519344 LDP	D14, D15, [SP, #96]

0x519348 LDP	X29, X30, [SP], #112

0x51934c RET

0x519350 FCMP	D14, D30

0x519354 B.EQ	519568

0x519358 FCMP	D14, D31

0x51935c B.NE	519658

0x519360 CMP	X20, X21

0x519364 B.GE	519014

0x519368 ADD	X27, X22, #8

0x51936c CNTD	X4, ALL

0x519370 PTRUE	P6.B, ALL

0x519374 HINT	#0

0x519378 HINT	#0

0x51937c HINT	#0

(3233) 0x519380 LDR	D27, [X26, X20,LSL #3]

(3233) 0x519384 LDR	X2, [X22, X20,LSL #3]

(3233) 0x519388 LDR	X5, [X27, X20,LSL #3]

(3233) 0x51938c FNMUL	D3, D27, D15

(3233) 0x519390 CMP	X2, X5

(3233) 0x519394 B.GE	5193d0

(3233) 0x519398 ADD	X3, X25, X2,LSL #3

(3233) 0x51939c MOVZ	X0, #0

(3233) 0x5193a0 SUB	X6, X5, X2

(3233) 0x5193a4 ADD	X7, X24, X2,LSL #3

(3233) 0x5193a8 WHILELO	P0.D, XZR, X6

  (3234) 0x5193ac LD1D	{Z25.D}, P0/Z, [X7, X0,LSL #3]

  (3234) 0x5193b0 LD1D	{Z23.D}, P0/Z, [X3, X0,LSL #3]

  (3234) 0x5193b4 LD1D	{Z24.D}, P0/Z, [X19, Z25.D,LSL #3]

  (3234) 0x5193b8 ADD	X0, X0, X4

  (3234) 0x5193bc FMUL	Z23.D, P0/M, Z23.D, Z24.D

  (3234) 0x5193c0 FNEG	Z23.D, P6/M, Z23.D

  (3234) 0x5193c4 FADDA	D3, P0, D3, Z23.D

  (3234) 0x5193c8 WHILELO	P0.D, X0, X6

  (3234) 0x5193cc B.NE	5193ac

(3233) 0x5193d0 STR	D3, [X23, X20,LSL #3]

(3233) 0x5193d4 ADD	X20, X20, #1

(3233) 0x5193d8 CMP	X21, X20

(3233) 0x5193dc B.NE	519380

0x5193e0 B	519014

0x5193e4 CMP	X20, X21

0x5193e8 B.GE	519014

0x5193ec ADD	X26, X22, #8

0x5193f0 LDR	X5, [X22, X20,LSL #3]

0x5193f4 CNTD	X6, ALL

0x5193f8 LDR	X2, [X26, X20,LSL #3]

0x5193fc CMP	X5, X2

0x519400 B.GE	519464

  (3221) 0x519404 MOVI	D15, #0

  (3221) 0x519408 ADD	X7, X25, X5,LSL #3

  (3221) 0x51940c MOVZ	X1, #0

  (3221) 0x519410 ADD	X8, X24, X5,LSL #3

  (3221) 0x519414 SUB	X9, X2, X5

  (3221) 0x519418 WHILELO	P2.D, XZR, X9

  (3221) 0x51941c HINT	#0

    (3220) 0x519420 LD1D	{Z31.D}, P2/Z, [X8, X1,LSL #3]

    (3220) 0x519424 LD1D	{Z30.D}, P2/Z, [X7, X1,LSL #3]

    (3220) 0x519428 LD1D	{Z29.D}, P2/Z, [X19, Z31.D,LSL #3]

    (3220) 0x51942c ADD	X1, X1, X6

    (3220) 0x519430 FMUL	Z30.D, P2/M, Z30.D, Z29.D

    (3220) 0x519434 FADDA	D15, P2, D15, Z30.D

    (3220) 0x519438 WHILELO	P2.D, X1, X9

    (3220) 0x51943c B.NE	519420

  (3221) 0x519440 FMUL	D1, D14, D15

  (3221) 0x519444 STR	D1, [X23, X20,LSL #3]

  (3221) 0x519448 ADD	X20, X20, #1

  (3221) 0x51944c CMP	X21, X20

  (3221) 0x519450 B.EQ	519014

  (3221) 0x519454 LDR	X5, [X22, X20,LSL #3]

  (3221) 0x519458 LDR	X2, [X26, X20,LSL #3]

  (3221) 0x51945c CMP	X5, X2

  (3221) 0x519460 B.LT	519404

(3222) 0x519464 MOVI	D15, #0

(3222) 0x519468 FMUL	D1, D14, D15

(3222) 0x51946c STR	D1, [X23, X20,LSL #3]

(3222) 0x519470 ADD	X20, X20, #1

(3222) 0x519474 CMP	X21, X20

(3222) 0x519478 B.NE	519454

0x51947c B	519014

0x519480 CMP	X20, X21

0x519484 B.GE	519014

0x519488 ADD	X11, X22, #8

0x51948c CNTD	X12, ALL

(3235) 0x519490 LDR	X13, [X22, X20,LSL #3]

(3235) 0x519494 LDR	X14, [X11, X20,LSL #3]

(3235) 0x519498 LDR	D29, [X26, X20,LSL #3]

(3235) 0x51949c CMP	X13, X14

(3235) 0x5194a0 B.GE	5194e0

(3235) 0x5194a4 ADD	X15, X25, X13,LSL #3

(3235) 0x5194a8 MOVZ	X18, #0

(3235) 0x5194ac SUB	X16, X14, X13

(3235) 0x5194b0 ADD	X17, X24, X13,LSL #3

(3235) 0x5194b4 WHILELO	P5.D, XZR, X16

(3235) 0x5194b8 HINT	#0

(3235) 0x5194bc HINT	#0

  (3236) 0x5194c0 LD1D	{Z1.D}, P5/Z, [X17, X18,LSL #3]

  (3236) 0x5194c4 LD1D	{Z0.D}, P5/Z, [X15, X18,LSL #3]

  (3236) 0x5194c8 LD1D	{Z28.D}, P5/Z, [X19, Z1.D,LSL #3]

  (3236) 0x5194cc ADD	X18, X18, X12

  (3236) 0x5194d0 FMUL	Z0.D, P5/M, Z0.D, Z28.D

  (3236) 0x5194d4 FADDA	D29, P5, D29, Z0.D

  (3236) 0x5194d8 WHILELO	P5.D, X18, X16

  (3236) 0x5194dc B.NE	5194c0

(3235) 0x5194e0 STR	D29, [X23, X20,LSL #3]

(3235) 0x5194e4 ADD	X20, X20, #1

(3235) 0x5194e8 CMP	X21, X20

(3235) 0x5194ec B.NE	519490

0x5194f0 B	519014

0x5194f4 CMP	X20, X21

0x5194f8 B.GE	519014

0x5194fc ADD	X8, X22, #8

0x519500 CNTD	X9, ALL

0x519504 PTRUE	P6.B, ALL

(3243) 0x519508 LDR	X10, [X22, X20,LSL #3]

(3243) 0x51950c LDR	X0, [X8, X20,LSL #3]

(3243) 0x519510 LDR	D4, [X26, X20,LSL #3]

(3243) 0x519514 CMP	X10, X0

(3243) 0x519518 B.GE	519554

(3243) 0x51951c ADD	X3, X25, X10,LSL #3

(3243) 0x519520 MOVZ	X13, #0

(3243) 0x519524 SUB	X11, X0, X10

(3243) 0x519528 ADD	X12, X24, X10,LSL #3

(3243) 0x51952c WHILELO	P0.D, XZR, X11

  (3244) 0x519530 LD1D	{Z21.D}, P0/Z, [X12, X13,LSL #3]

  (3244) 0x519534 LD1D	{Z22.D}, P0/Z, [X3, X13,LSL #3]

  (3244) 0x519538 LD1D	{Z19.D}, P0/Z, [X19, Z21.D,LSL #3]

  (3244) 0x51953c ADD	X13, X13, X9

  (3244) 0x519540 FMUL	Z22.D, P0/M, Z22.D, Z19.D

  (3244) 0x519544 FNEG	Z22.D, P6/M, Z22.D

  (3244) 0x519548 FADDA	D4, P0, D4, Z22.D

  (3244) 0x51954c WHILELO	P0.D, X13, X11

  (3244) 0x519550 B.NE	519530

(3243) 0x519554 STR	D4, [X23, X20,LSL #3]

(3243) 0x519558 ADD	X20, X20, #1

(3243) 0x51955c CMP	X21, X20

(3243) 0x519560 B.NE	519508

0x519564 B	519014

0x519568 CMP	X20, X21

0x51956c B.GE	519014

0x519570 ADD	X8, X22, #8

0x519574 CNTD	X9, ALL

0x519578 HINT	#0

0x51957c HINT	#0

(3229) 0x519580 LDR	D22, [X26, X20,LSL #3]

(3229) 0x519584 LDR	X10, [X22, X20,LSL #3]

(3229) 0x519588 LDR	X11, [X8, X20,LSL #3]

(3229) 0x51958c FMUL	D4, D15, D22

(3229) 0x519590 CMP	X10, X11

(3229) 0x519594 B.GE	5195cc

(3229) 0x519598 ADD	X12, X25, X10,LSL #3

(3229) 0x51959c MOVZ	X15, #0

(3229) 0x5195a0 SUB	X13, X11, X10

(3229) 0x5195a4 ADD	X14, X24, X10,LSL #3

(3229) 0x5195a8 WHILELO	P1.D, XZR, X13

  (3230) 0x5195ac LD1D	{Z21.D}, P1/Z, [X14, X15,LSL #3]

  (3230) 0x5195b0 LD1D	{Z19.D}, P1/Z, [X12, X15,LSL #3]

  (3230) 0x5195b4 LD1D	{Z20.D}, P1/Z, [X19, Z21.D,LSL #3]

  (3230) 0x5195b8 ADD	X15, X15, X9

  (3230) 0x5195bc FMUL	Z19.D, P1/M, Z19.D, Z20.D

  (3230) 0x5195c0 FADDA	D4, P1, D4, Z19.D

  (3230) 0x5195c4 WHILELO	P1.D, X15, X13

  (3230) 0x5195c8 B.NE	5195ac

(3229) 0x5195cc STR	D4, [X23, X20,LSL #3]

(3229) 0x5195d0 ADD	X20, X20, #1

(3229) 0x5195d4 CMP	X21, X20

(3229) 0x5195d8 B.NE	519580

0x5195dc B	519014

0x5195e0 CMP	X20, X21

0x5195e4 B.GE	519014

0x5195e8 ADD	X16, X22, #8

0x5195ec CNTD	X17, ALL

(3237) 0x5195f0 LDR	X18, [X22, X20,LSL #3]

(3237) 0x5195f4 LDR	X30, [X16, X20,LSL #3]

(3237) 0x5195f8 LDR	D7, [X26, X20,LSL #3]

(3237) 0x5195fc CMP	X18, X30

(3237) 0x519600 B.GE	519640

(3237) 0x519604 ADD	X27, X25, X18,LSL #3

(3237) 0x519608 MOVZ	X2, #0

(3237) 0x51960c SUB	X1, X30, X18

(3237) 0x519610 ADD	X4, X24, X18,LSL #3

(3237) 0x519614 WHILELO	P2.D, XZR, X1

(3237) 0x519618 HINT	#0

(3237) 0x51961c HINT	#0

  (3238) 0x519620 LD1D	{Z18.D}, P2/Z, [X4, X2,LSL #3]

  (3238) 0x519624 LD1D	{Z16.D}, P2/Z, [X27, X2,LSL #3]

  (3238) 0x519628 LD1D	{Z17.D}, P2/Z, [X19, Z18.D,LSL #3]

  (3238) 0x51962c ADD	X2, X2, X17

  (3238) 0x519630 FMUL	Z16.D, P2/M, Z16.D, Z17.D

  (3238) 0x519634 FADDA	D7, P2, D7, Z16.D

  (3238) 0x519638 WHILELO	P2.D, X2, X1

  (3238) 0x51963c B.NE	519620

(3237) 0x519640 FMUL	D5, D14, D7

(3237) 0x519644 STR	D5, [X23, X20,LSL #3]

(3237) 0x519648 ADD	X20, X20, #1

(3237) 0x51964c CMP	X21, X20

(3237) 0x519650 B.NE	5195f0

0x519654 B	519014

0x519658 CMP	X20, X21

0x51965c B.GE	519014

0x519660 ADD	X13, X22, #8

0x519664 CNTD	X14, ALL

(3231) 0x519668 LDR	D29, [X26, X20,LSL #3]

(3231) 0x51966c LDR	X15, [X22, X20,LSL #3]

(3231) 0x519670 LDR	X16, [X13, X20,LSL #3]

(3231) 0x519674 FMUL	D1, D15, D29

(3231) 0x519678 CMP	X15, X16

(3231) 0x51967c B.GE	5196c0

(3231) 0x519680 ADD	X17, X25, X15,LSL #3

(3231) 0x519684 MOVZ	X1, #0

(3231) 0x519688 SUB	X18, X16, X15

(3231) 0x51968c ADD	X30, X24, X15,LSL #3

(3231) 0x519690 WHILELO	P7.D, XZR, X18

(3231) 0x519694 HINT	#0

(3231) 0x519698 HINT	#0

(3231) 0x51969c HINT	#0

  (3232) 0x5196a0 LD1D	{Z0.D}, P7/Z, [X30, X1,LSL #3]

  (3232) 0x5196a4 LD1D	{Z28.D}, P7/Z, [X17, X1,LSL #3]

  (3232) 0x5196a8 LD1D	{Z26.D}, P7/Z, [X19, Z0.D,LSL #3]

  (3232) 0x5196ac ADD	X1, X1, X14

  (3232) 0x5196b0 FMUL	Z28.D, P7/M, Z28.D, Z26.D

  (3232) 0x5196b4 FADDA	D1, P7, D1, Z28.D

  (3232) 0x5196b8 WHILELO	P7.D, X1, X18

  (3232) 0x5196bc B.NE	5196a0

(3231) 0x5196c0 FMUL	D2, D14, D1

(3231) 0x5196c4 STR	D2, [X23, X20,LSL #3]

(3231) 0x5196c8 ADD	X20, X20, #1

(3231) 0x5196cc CMP	X21, X20

(3231) 0x5196d0 B.NE	519668

0x5196d4 B	519014

0x5196d8 HINT	#0

0x5196dc HINT	#0

Coverage (%)	Name	Module
►98.42+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 26.00 to 4.00 cycles (6.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 31% of vector register length is used (average across all VPU instructions).

Details

2% of VPU instructions are used in vector version (process two or more data elements in vector registers):

11% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CSRMatrixGetLoadBalancedPartitionBegin: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:246
hypre_CSRMatrixGetLoadBalancedPartitionEnd: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:247
hypre_error_handler: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248
hypre_fprintf: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	196
nb uops	189
loop length	784
used w registers	0
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	0
used v registers	0
used z registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.63 cycles
front end	23.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	26.00	26.00	23.25	23.25	23.25	23.25	11.00	2.00	2.00	2.00	12.50	12.17	12.33	3.00	3.00
cycles	26.00	26.00	23.25	23.25	23.25	23.25	11.00	2.00	2.00	2.00	12.50	12.17	12.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.63
Dispatch	26.00
Overall L1	26.00

Vectorization ratios

INT

all	3%
load	11%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	11%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	32%
load	34%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	31%
load	34%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 26.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 518f00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP X21, X25, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X24, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X26, [X1, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D14, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D15, [X1, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X23, [X1, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [X1, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 517ba4 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 517c48 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 519288 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X27, X20, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 519250 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X27, X21, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 519218 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D15, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 519034 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D15, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51917c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D26, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D14, D26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 5192c0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 5194f4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x5f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X27, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D5, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D14, D5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 5190d8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X30, [X16, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 5190c0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D6, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D14, D6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 5193e4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x4e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X13, [X10, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519164 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D30, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D15, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 519350 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 519480 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x580>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 5195e0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X9, <533218>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X10, <53221c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X11, <560220>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X9, #1312	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X10, #2216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X11, #1280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 525180 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X12, <533234>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X12, #1344	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #250	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 5289c0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 518f78 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, <533250>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X6, <532254>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X7, <560258>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X5, #1432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X6, #2216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X7, #1280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 525180 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, <53326c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X8, #1344	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #249	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 5289c0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 518f6c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, <532288>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, <53328c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <560290>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X3, #2216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #872	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X0, #1280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 525180 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X4, <5332a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X4, #1344	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 5289c0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 518f60 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 519568 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 519658 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X2, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X5, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519464 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x564>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 26.00 to 4.00 cycles (6.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 31% of vector register length is used (average across all VPU instructions).

Details

2% of VPU instructions are used in vector version (process two or more data elements in vector registers):

11% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CSRMatrixGetLoadBalancedPartitionBegin: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:246
hypre_CSRMatrixGetLoadBalancedPartitionEnd: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:247
hypre_error_handler: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248
hypre_fprintf: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	196
nb uops	189
loop length	784
used w registers	0
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	0
used v registers	0
used z registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.63 cycles
front end	23.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	26.00	26.00	23.25	23.25	23.25	23.25	11.00	2.00	2.00	2.00	12.50	12.17	12.33	3.00	3.00
cycles	26.00	26.00	23.25	23.25	23.25	23.25	11.00	2.00	2.00	2.00	12.50	12.17	12.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.63
Dispatch	26.00
Overall L1	26.00

Vectorization ratios

INT

all	3%
load	11%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	11%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	32%
load	34%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	31%
load	34%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 26.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 518f00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP X21, X25, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X24, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X26, [X1, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D14, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D15, [X1, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X23, [X1, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [X1, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 517ba4 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 517c48 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 519288 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X27, X20, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 519250 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X27, X21, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 519218 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D15, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 519034 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D15, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51917c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D26, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D14, D26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 5192c0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 5194f4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x5f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X27, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D5, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D14, D5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 5190d8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X30, [X16, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 5190c0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D6, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D14, D6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 5193e4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x4e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X13, [X10, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519164 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D30, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D15, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 519350 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 519480 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x580>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 5195e0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X9, <533218>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X10, <53221c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X11, <560220>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X9, #1312	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X10, #2216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X11, #1280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 525180 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X12, <533234>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X12, #1344	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #250	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 5289c0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 518f78 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, <533250>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X6, <532254>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X7, <560258>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X5, #1432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X6, #2216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X7, #1280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 525180 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, <53326c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X8, #1344	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #249	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 5289c0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 518f6c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, <532288>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, <53328c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <560290>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X3, #2216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #872	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X0, #1280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 525180 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X4, <5332a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X4, #1344	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 5289c0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 518f60 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 519568 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 519658 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X2, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X5, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519464 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x564>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B 519014 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6–	17.91	7.48
▼Loop 3243 - csr_matvec.c:307-314 - exec–	0.12	0.04
○Loop 3244 - csr_matvec.c:310-312 - exec	8.89	2.76
▼Loop 3235 - csr_matvec.c:334-341 - exec–	0.07	0.02
○Loop 3236 - csr_matvec.c:337-339 - exec	0.86	0.27
▼Loop 3222 - csr_matvec.c:280-287 - exec–	0.00	0.00
▼Loop 3221 - csr_matvec.c:280-287 - exec–	0.00	0.00
○Loop 3220 - csr_matvec.c:283-285 - exec	0.00	0.00
▼Loop 3233 - csr_matvec.c:385-392 - exec–	0.00	0.00
○Loop 3234 - csr_matvec.c:388-390 - exec	0.00	0.00
▼Loop 3225 - csr_matvec.c:268-275 - exec–	0.00	0.00
▼Loop 3224 - csr_matvec.c:268-275 - exec–	0.00	0.00
○Loop 3223 - csr_matvec.c:271-273 - exec	0.00	0.00
▼Loop 3241 - csr_matvec.c:295-302 - exec–	0.00	0.00
○Loop 3242 - csr_matvec.c:298-300 - exec	0.00	0.00
▼Loop 3231 - csr_matvec.c:397-404 - exec–	0.00	0.00
○Loop 3232 - csr_matvec.c:400-402 - exec	0.00	0.00
▼Loop 3239 - csr_matvec.c:346-353 - exec–	0.00	0.00
○Loop 3240 - csr_matvec.c:349-351 - exec	0.00	0.00
▼Loop 3237 - csr_matvec.c:358-365 - exec–	0.00	0.00
○Loop 3238 - csr_matvec.c:361-363 - exec	0.00	0.00
▼Loop 3228 - csr_matvec.c:256-263 - exec–	0.00	0.00
▼Loop 3227 - csr_matvec.c:256-263 - exec–	0.07	0.02
○Loop 3226 - csr_matvec.c:259-261 - exec	7.90	2.46
▼Loop 3229 - csr_matvec.c:373-380 - exec–	0.00	0.00
○Loop 3230 - csr_matvec.c:376-378 - exec	0.00	0.00
▼Loop 3245 - csr_matvec.c:319-326 - exec–	0.00	0.00
○Loop 3246 - csr_matvec.c:322-324 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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ASM code