OV - exec - Function hypre_CSRMatrixMatvecT._omp

	Function: hypre_CSRMatrixMatvecT._omp_fn.3	Module: exec	Source: csr_matvec.c:554-579 [...]	Coverage (incl. loops): 0.87% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 554 - 579

--------------------------------------------------------------------------------

554: #pragma omp parallel private(i,jj,j,my_thread_num,offset)

555: #endif

556:          {

557:             my_thread_num = hypre_GetThreadNum();

558:             offset =  y_size*my_thread_num;

[...]

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

[...]

577:                for (j = 0; j < num_threads; j++)

578:                {

579:                   y_data[i] += y_data_expand[j*y_size + i];

0x519ec0 STP	X29, X30, [SP, #912]!

0x519ec4 ADD	X29, SP, #0

0x519ec8 STP	X19, X20, [SP, #16]

0x519ecc STP	X21, X22, [SP, #32]

0x519ed0 STP	X23, X24, [SP, #48]

0x519ed4 STP	X25, X26, [SP, #64]

0x519ed8 STP	X27, X28, [SP, #80]

0x519edc LDP	X28, X7, [X0]

0x519ee0 LDP	X27, X20, [X0, #16]

0x519ee4 LDP	X25, X23, [X0, #32]

0x519ee8 LDP	X22, X19, [X0, #48]

0x519eec STR	X7, [SP, #104]

0x519ef0 LDR	X26, [X0, #64]

0x519ef4 BL	527b40

0x519ef8 ORR	X24, XZR, X0

0x519efc BL	4100b0

0x519f00 SBFM	X21, X0, #0, #31

0x519f04 BL	410200

0x519f08 SDIV	X12, X20, X21

0x519f0c SBFM	X0, X0, #0, #31

0x519f10 LDR	X14, [SP, #104]

0x519f14 MSUB	X2, X12, X21, X20

0x519f18 CMP	X0, X2

0x519f1c B.LT	51a258

0x519f20 MADD	X2, X12, X0, X2

0x519f24 ADD	X15, X12, X2

0x519f28 CMP	X2, X15

0x519f2c B.GE	51a084

0x519f30 MUL	X16, X22, X24

0x519f34 ADD	X13, X14, #8

0x519f38 HINT	#0

0x519f3c HINT	#0

(3252) 0x519f40 LDR	X1, [X14, X2,LSL #3]

(3252) 0x519f44 LDR	X11, [X13, X2,LSL #3]

(3252) 0x519f48 CMP	X1, X11

(3252) 0x519f4c B.GE	51a078

(3252) 0x519f50 SUB	X3, X11, X1

(3252) 0x519f54 ANDS	X4, X3, #0x3

(3252) 0x519f58 B.EQ	519fe0

(3252) 0x519f5c CMP	X4, #1

(3252) 0x519f60 B.EQ	519fb4

(3252) 0x519f64 CMP	X4, #2

(3252) 0x519f68 B.EQ	519f90

(3252) 0x519f6c LDR	X5, [X27, X1,LSL #3]

(3252) 0x519f70 LDR	D31, [X28, X1,LSL #3]

(3252) 0x519f74 ADD	X1, X1, #1

(3252) 0x519f78 LDR	D30, [X25, X2,LSL #3]

(3252) 0x519f7c ADD	X6, X16, X5

(3252) 0x519f80 UBFM	X8, X6, #61, #60

(3252) 0x519f84 LDR	D29, [X19, X8]

(3252) 0x519f88 FMADD	D0, D31, D30, D29

(3252) 0x519f8c STR	D0, [X19, X8]

(3252) 0x519f90 LDR	X9, [X27, X1,LSL #3]

(3252) 0x519f94 LDR	D28, [X28, X1,LSL #3]

(3252) 0x519f98 ADD	X1, X1, #1

(3252) 0x519f9c LDR	D27, [X25, X2,LSL #3]

(3252) 0x519fa0 ADD	X10, X16, X9

(3252) 0x519fa4 UBFM	X17, X10, #61, #60

(3252) 0x519fa8 LDR	D26, [X19, X17]

(3252) 0x519fac FMADD	D1, D28, D27, D26

(3252) 0x519fb0 STR	D1, [X19, X17]

(3252) 0x519fb4 LDR	X18, [X27, X1,LSL #3]

(3252) 0x519fb8 LDR	D25, [X28, X1,LSL #3]

(3252) 0x519fbc ADD	X1, X1, #1

(3252) 0x519fc0 LDR	D24, [X25, X2,LSL #3]

(3252) 0x519fc4 ADD	X30, X16, X18

(3252) 0x519fc8 UBFM	X7, X30, #61, #60

(3252) 0x519fcc LDR	D23, [X19, X7]

(3252) 0x519fd0 FMADD	D2, D25, D24, D23

(3252) 0x519fd4 STR	D2, [X19, X7]

(3252) 0x519fd8 CMP	X1, X11

(3252) 0x519fdc B.EQ	51a078

  (3253) 0x519fe0 LDR	X20, [X27, X1,LSL #3]

  (3253) 0x519fe4 ADD	X24, X1, #1

  (3253) 0x519fe8 ADD	X12, X1, #3

  (3253) 0x519fec ADD	X8, X1, #2

  (3253) 0x519ff0 LDR	D5, [X28, X1,LSL #3]

  (3253) 0x519ff4 ADD	X1, X1, #4

  (3253) 0x519ff8 LDR	D4, [X25, X2,LSL #3]

  (3253) 0x519ffc ADD	X3, X16, X20

  (3253) 0x51a000 UBFM	X6, X3, #61, #60

  (3253) 0x51a004 LDR	X5, [X27, X24,LSL #3]

  (3253) 0x51a008 LDR	D3, [X19, X6]

  (3253) 0x51a00c LDR	X4, [X27, X8,LSL #3]

  (3253) 0x51a010 ADD	X9, X16, X5

  (3253) 0x51a014 UBFM	X10, X9, #61, #60

  (3253) 0x51a018 LDR	X17, [X27, X12,LSL #3]

  (3253) 0x51a01c FMADD	D6, D5, D4, D3

  (3253) 0x51a020 ADD	X18, X16, X4

  (3253) 0x51a024 UBFM	X30, X18, #61, #60

  (3253) 0x51a028 ADD	X7, X16, X17

  (3253) 0x51a02c UBFM	X20, X7, #61, #60

  (3253) 0x51a030 STR	D6, [X19, X6]

  (3253) 0x51a034 LDR	D16, [X28, X24,LSL #3]

  (3253) 0x51a038 LDR	D7, [X25, X2,LSL #3]

  (3253) 0x51a03c LDR	D17, [X19, X10]

  (3253) 0x51a040 FMADD	D18, D16, D7, D17

  (3253) 0x51a044 STR	D18, [X19, X10]

  (3253) 0x51a048 LDR	D19, [X28, X8,LSL #3]

  (3253) 0x51a04c LDR	D20, [X25, X2,LSL #3]

  (3253) 0x51a050 LDR	D21, [X19, X30]

  (3253) 0x51a054 FMADD	D22, D19, D20, D21

  (3253) 0x51a058 STR	D22, [X19, X30]

  (3253) 0x51a05c LDR	D31, [X28, X12,LSL #3]

  (3253) 0x51a060 LDR	D30, [X25, X2,LSL #3]

  (3253) 0x51a064 LDR	D29, [X19, X20]

  (3253) 0x51a068 FMADD	D0, D31, D30, D29

  (3253) 0x51a06c STR	D0, [X19, X20]

  (3253) 0x51a070 CMP	X1, X11

  (3253) 0x51a074 B.NE	519fe0

(3252) 0x51a078 ADD	X2, X2, #1

(3252) 0x51a07c CMP	X15, X2

(3252) 0x51a080 B.NE	519f40

0x51a084 STR	X0, [SP, #104]

0x51a088 BL	4102a0

0x51a08c SDIV	X27, X22, X21

0x51a090 LDR	X28, [SP, #104]

0x51a094 MSUB	X25, X27, X21, X22

0x51a098 CMP	X28, X25

0x51a09c B.LT	51a24c

0x51a0a0 MADD	X1, X27, X28, X25

0x51a0a4 ADD	X21, X27, X1

0x51a0a8 CMP	X1, X21

0x51a0ac B.GE	51a230

0x51a0b0 CMP	X26, #0

0x51a0b4 B.LE	51a230

0x51a0b8 ADD	X19, X19, X1,LSL #3

0x51a0bc UBFM	X22, X22, #61, #60

(3251) 0x51a0c0 ANDS	X0, X26, #0x7

(3251) 0x51a0c4 LDR	D2, [X23, X1,LSL #3]

(3251) 0x51a0c8 ORR	X15, XZR, X19

(3251) 0x51a0cc MOVZ	X14, #0

(3251) 0x51a0d0 B.EQ	51a198

(3251) 0x51a0d4 CMP	X0, #1

(3251) 0x51a0d8 B.EQ	51a17c

(3251) 0x51a0dc CMP	X0, #2

(3251) 0x51a0e0 B.EQ	51a168

(3251) 0x51a0e4 CMP	X0, #3

(3251) 0x51a0e8 B.EQ	51a154

(3251) 0x51a0ec CMP	X0, #4

(3251) 0x51a0f0 B.EQ	51a140

(3251) 0x51a0f4 CMP	X0, #5

(3251) 0x51a0f8 B.EQ	51a12c

(3251) 0x51a0fc CMP	X0, #6

(3251) 0x51a100 B.EQ	51a118

(3251) 0x51a104 LDR	D28, [X19]

(3251) 0x51a108 MOVZ	X14, #1

(3251) 0x51a10c ADD	X15, X19, X22

(3251) 0x51a110 FADD	D2, D2, D28

(3251) 0x51a114 STR	D2, [X23, X1,LSL #3]

(3251) 0x51a118 LDR	D27, [X15]

(3251) 0x51a11c ADD	X14, X14, #1

(3251) 0x51a120 ADD	X15, X15, X22

(3251) 0x51a124 FADD	D2, D2, D27

(3251) 0x51a128 STR	D2, [X23, X1,LSL #3]

(3251) 0x51a12c LDR	D26, [X15]

(3251) 0x51a130 ADD	X14, X14, #1

(3251) 0x51a134 ADD	X15, X15, X22

(3251) 0x51a138 FADD	D2, D2, D26

(3251) 0x51a13c STR	D2, [X23, X1,LSL #3]

(3251) 0x51a140 LDR	D1, [X15]

(3251) 0x51a144 ADD	X14, X14, #1

(3251) 0x51a148 ADD	X15, X15, X22

(3251) 0x51a14c FADD	D2, D2, D1

(3251) 0x51a150 STR	D2, [X23, X1,LSL #3]

(3251) 0x51a154 LDR	D25, [X15]

(3251) 0x51a158 ADD	X14, X14, #1

(3251) 0x51a15c ADD	X15, X15, X22

(3251) 0x51a160 FADD	D2, D2, D25

(3251) 0x51a164 STR	D2, [X23, X1,LSL #3]

(3251) 0x51a168 LDR	D24, [X15]

(3251) 0x51a16c ADD	X14, X14, #1

(3251) 0x51a170 ADD	X15, X15, X22

(3251) 0x51a174 FADD	D2, D2, D24

(3251) 0x51a178 STR	D2, [X23, X1,LSL #3]

(3251) 0x51a17c LDR	D23, [X15]

(3251) 0x51a180 ADD	X14, X14, #1

(3251) 0x51a184 ADD	X15, X15, X22

(3251) 0x51a188 FADD	D2, D2, D23

(3251) 0x51a18c STR	D2, [X23, X1,LSL #3]

(3251) 0x51a190 CMP	X26, X14

(3251) 0x51a194 B.EQ	51a220

  (3250) 0x51a198 LDR	D5, [X15]

  (3250) 0x51a19c ADD	X16, X15, X22

  (3250) 0x51a1a0 ADD	X13, X15, X22,LSL #1

  (3250) 0x51a1a4 ADD	X14, X14, #8

  (3250) 0x51a1a8 ADD	X11, X13, X22

  (3250) 0x51a1ac ADD	X24, X13, X22,LSL #1

  (3250) 0x51a1b0 ADD	X12, X24, X22

  (3250) 0x51a1b4 ADD	X8, X24, X22,LSL #1

  (3250) 0x51a1b8 FADD	D4, D2, D5

  (3250) 0x51a1bc STR	D4, [X23, X1,LSL #3]

  (3250) 0x51a1c0 LDR	D3, [X15, X22]

  (3250) 0x51a1c4 ADD	X15, X8, X22,LSL #1

  (3250) 0x51a1c8 FADD	D6, D4, D3

  (3250) 0x51a1cc STR	D6, [X23, X1,LSL #3]

  (3250) 0x51a1d0 LDR	D16, [X16, X22]

  (3250) 0x51a1d4 FADD	D7, D6, D16

  (3250) 0x51a1d8 STR	D7, [X23, X1,LSL #3]

  (3250) 0x51a1dc LDR	D17, [X13, X22]

  (3250) 0x51a1e0 FADD	D18, D7, D17

  (3250) 0x51a1e4 STR	D18, [X23, X1,LSL #3]

  (3250) 0x51a1e8 LDR	D19, [X11, X22]

  (3250) 0x51a1ec FADD	D20, D18, D19

  (3250) 0x51a1f0 STR	D20, [X23, X1,LSL #3]

  (3250) 0x51a1f4 LDR	D21, [X24, X22]

  (3250) 0x51a1f8 FADD	D22, D20, D21

  (3250) 0x51a1fc STR	D22, [X23, X1,LSL #3]

  (3250) 0x51a200 LDR	D31, [X12, X22]

  (3250) 0x51a204 FADD	D30, D22, D31

  (3250) 0x51a208 STR	D30, [X23, X1,LSL #3]

  (3250) 0x51a20c LDR	D29, [X8, X22]

  (3250) 0x51a210 FADD	D2, D30, D29

  (3250) 0x51a214 STR	D2, [X23, X1,LSL #3]

  (3250) 0x51a218 CMP	X26, X14

  (3250) 0x51a21c B.NE	51a198

(3251) 0x51a220 ADD	X1, X1, #1

(3251) 0x51a224 ADD	X19, X19, #8

(3251) 0x51a228 CMP	X21, X1

(3251) 0x51a22c B.NE	51a0c0

0x51a230 LDP	X19, X20, [SP, #16]

0x51a234 LDP	X21, X22, [SP, #32]

0x51a238 LDP	X23, X24, [SP, #48]

0x51a23c LDP	X25, X26, [SP, #64]

0x51a240 LDP	X27, X28, [SP, #80]

0x51a244 LDP	X29, X30, [SP], #112

0x51a248 B	4102a0

0x51a24c ADD	X27, X27, #1

0x51a250 MOVZ	X25, #0

0x51a254 B	51a0a0

0x51a258 ADD	X12, X12, #1

0x51a25c MOVZ	X2, #0

0x51a260 B	519f20

Coverage (%)	Name	Source Location	Module
►98.45+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.50+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMatvecT	csr_matvec.c:554	exec
○	hypre_ParCSRMatrixMatvecT	par_csr_matvec.c:439	exec
○	hypre_BoomerAMGCycle	par_cycle.c:435	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 36% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 40.00 to 30.00 cycles (1.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 7.00 cycles (5.71x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557
unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	60
nb uops	58
loop length	240
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.25 cycles
front end	7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00
cycles	6.00	6.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	7.25
Dispatch	7.50
DIV/SQRT	10.00-40.00
Overall L1	10.00-40.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	36%
load	44%
store	43%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 519ec0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X20, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X23, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X19, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 527b40 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X21, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 410200 <@plt_start@+0x1e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X12, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X0, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X2, X12, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 51a258 <hypre_CSRMatrixMatvecT._omp_fn.3+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X2, X12, X0, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X15, X12, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51a084 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X16, X22, X24	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X13, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
STR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X27, X22, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X25, X27, X21, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X28, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 51a24c <hypre_CSRMatrixMatvecT._omp_fn.3+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X27, X28, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X21, X27, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51a230 <hypre_CSRMatrixMatvecT._omp_fn.3+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 51a230 <hypre_CSRMatrixMatvecT._omp_fn.3+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X19, X19, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X22, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 51a0a0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 519f20 <hypre_CSRMatrixMatvecT._omp_fn.3+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 7.00 cycles (5.71x speedup).

CALL instructions

Detected function call instructions.

Details

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557
unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	60
nb uops	58
loop length	240
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.25 cycles
front end	7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00
cycles	6.00	6.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	7.25
Dispatch	7.50
DIV/SQRT	10.00-40.00
Overall L1	10.00-40.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	36%
load	44%
store	43%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 519ec0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X20, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X23, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X19, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 527b40 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X21, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 410200 <@plt_start@+0x1e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X12, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X0, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X2, X12, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 51a258 <hypre_CSRMatrixMatvecT._omp_fn.3+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X2, X12, X0, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X15, X12, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51a084 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X16, X22, X24	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X13, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
STR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X27, X22, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X25, X27, X21, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X28, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 51a24c <hypre_CSRMatrixMatvecT._omp_fn.3+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X27, X28, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X21, X27, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51a230 <hypre_CSRMatrixMatvecT._omp_fn.3+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 51a230 <hypre_CSRMatrixMatvecT._omp_fn.3+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X19, X19, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X22, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 51a0a0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 519f20 <hypre_CSRMatrixMatvecT._omp_fn.3+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecT._omp_fn.3–	0.87	0.36
▼Loop 3252 - csr_matvec.c:564-567 - exec–	0.63	0.20
○Loop 3253 - csr_matvec.c:564-567 - exec	0.12	0.04
▼Loop 3251 - csr_matvec.c:577-579 - exec–	0.00	0.01
○Loop 3250 - csr_matvec.c:577-579 - exec	0.12	0.04

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Vectorization

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Matching between your function (in the source code) and the binary function

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code