OV - exec - Function hypre_SeqVectorAxpy._omp

	Function: hypre_SeqVectorAxpy._omp_fn.0	Module: exec	Source: vector.c:449-452	Coverage (incl. loops): 1.25% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 449 - 452

--------------------------------------------------------------------------------

449: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

450: #endif

451:    for (i = 0; i < size; i++)

452:       y_data[i] += alpha * x_data[i];

0x51d2a8 STP	X29, X30, [SP, #976]!

0x51d2ac ADD	X29, SP, #0

0x51d2b0 STP	X19, X20, [SP, #16]

0x51d2b4 ORR	X20, XZR, X0

0x51d2b8 STR	X21, [SP, #32]

0x51d2bc LDR	X21, [X0, #24]

0x51d2c0 BL	4100b0

0x51d2c4 SBFM	X19, X0, #0, #31

0x51d2c8 BL	410200

0x51d2cc SBFM	X1, X0, #0, #31

0x51d2d0 SDIV	X4, X21, X19

0x51d2d4 MSUB	X2, X4, X19, X21

0x51d2d8 CMP	X1, X2

0x51d2dc B.LT	51d4e0

0x51d2e0 MADD	X1, X4, X1, X2

0x51d2e4 ADD	X0, X4, X1

0x51d2e8 CMP	X1, X0

0x51d2ec B.GE	51d4d0

0x51d2f0 SUB	X3, X4, #1

0x51d2f4 LDR	D31, [X20]

0x51d2f8 LDP	X8, X6, [X20, #8]

0x51d2fc CMP	X3, #1

0x51d300 B.LS	51d4ec

0x51d304 UBFM	X9, X1, #61, #60

0x51d308 ADD	X15, X6, X1,LSL #3

0x51d30c ADD	X5, X9, #8

0x51d310 ADD	X7, X8, X5

0x51d314 CMP	X15, X7

0x51d318 B.EQ	51d4ec

0x51d31c UBFM	X10, X4, #1, #63

0x51d320 DUP	V30.2D, V31.D[0]

0x51d324 ADD	X16, X8, X9

0x51d328 UBFM	X17, X10, #60, #59

0x51d32c MOVZ	X18, #0

0x51d330 SUB	X11, X17, #16

0x51d334 UBFM	X12, X11, #4, #63

0x51d338 ADD	X13, X12, #1

0x51d33c ANDS	X14, X13, #0x7

0x51d340 B.EQ	51d408

0x51d344 CMP	X14, #1

0x51d348 B.EQ	51d3ec

0x51d34c CMP	X14, #2

0x51d350 B.EQ	51d3d8

0x51d354 CMP	X14, #3

0x51d358 B.EQ	51d3c4

0x51d35c CMP	X14, #4

0x51d360 B.EQ	51d3b0

0x51d364 CMP	X14, #5

0x51d368 B.EQ	51d39c

0x51d36c CMP	X14, #6

0x51d370 B.EQ	51d388

0x51d374 LDR	Q22, [X15]

0x51d378 MOVZ	X18, #16

0x51d37c LDR	Q23, [X16]

0x51d380 FMLA	V22.2D, V23.2D, V30.2D

0x51d384 STR	Q22, [X15]

0x51d388 LDR	Q21, [X16, X18]

0x51d38c LDR	Q20, [X15, X18]

0x51d390 FMLA	V20.2D, V21.2D, V30.2D

0x51d394 STR	Q20, [X15, X18]

0x51d398 ADD	X18, X18, #16

0x51d39c LDR	Q19, [X16, X18]

0x51d3a0 LDR	Q18, [X15, X18]

0x51d3a4 FMLA	V18.2D, V19.2D, V30.2D

0x51d3a8 STR	Q18, [X15, X18]

0x51d3ac ADD	X18, X18, #16

0x51d3b0 LDR	Q17, [X16, X18]

0x51d3b4 LDR	Q16, [X15, X18]

0x51d3b8 FMLA	V16.2D, V17.2D, V30.2D

0x51d3bc STR	Q16, [X15, X18]

0x51d3c0 ADD	X18, X18, #16

0x51d3c4 LDR	Q7, [X16, X18]

0x51d3c8 LDR	Q6, [X15, X18]

0x51d3cc FMLA	V6.2D, V7.2D, V30.2D

0x51d3d0 STR	Q6, [X15, X18]

0x51d3d4 ADD	X18, X18, #16

0x51d3d8 LDR	Q5, [X16, X18]

0x51d3dc LDR	Q4, [X15, X18]

0x51d3e0 FMLA	V4.2D, V5.2D, V30.2D

0x51d3e4 STR	Q4, [X15, X18]

0x51d3e8 ADD	X18, X18, #16

0x51d3ec LDR	Q3, [X16, X18]

0x51d3f0 LDR	Q2, [X15, X18]

0x51d3f4 FMLA	V2.2D, V3.2D, V30.2D

0x51d3f8 STR	Q2, [X15, X18]

0x51d3fc ADD	X18, X18, #16

0x51d400 CMP	X18, X17

0x51d404 B.EQ	51d4b0

(3289) 0x51d408 LDR	Q1, [X16, X18]

(3289) 0x51d40c ADD	X30, X18, #16

(3289) 0x51d410 ADD	X21, X18, #32

(3289) 0x51d414 ADD	X20, X18, #48

(3289) 0x51d418 ADD	X19, X18, #64

(3289) 0x51d41c LDR	Q0, [X15, X18]

(3289) 0x51d420 ADD	X2, X18, #80

(3289) 0x51d424 ADD	X0, X18, #96

(3289) 0x51d428 ADD	X3, X18, #112

(3289) 0x51d42c FMLA	V0.2D, V1.2D, V30.2D

(3289) 0x51d430 STR	Q0, [X15, X18]

(3289) 0x51d434 ADD	X18, X18, #128

(3289) 0x51d438 LDR	Q29, [X16, X30]

(3289) 0x51d43c LDR	Q28, [X15, X30]

(3289) 0x51d440 FMLA	V28.2D, V29.2D, V30.2D

(3289) 0x51d444 STR	Q28, [X15, X30]

(3289) 0x51d448 LDR	Q27, [X16, X21]

(3289) 0x51d44c LDR	Q26, [X15, X21]

(3289) 0x51d450 FMLA	V26.2D, V27.2D, V30.2D

(3289) 0x51d454 STR	Q26, [X15, X21]

(3289) 0x51d458 LDR	Q25, [X16, X20]

(3289) 0x51d45c LDR	Q24, [X15, X20]

(3289) 0x51d460 FMLA	V24.2D, V25.2D, V30.2D

(3289) 0x51d464 STR	Q24, [X15, X20]

(3289) 0x51d468 LDR	Q23, [X16, X19]

(3289) 0x51d46c LDR	Q22, [X15, X19]

(3289) 0x51d470 FMLA	V22.2D, V23.2D, V30.2D

(3289) 0x51d474 STR	Q22, [X15, X19]

(3289) 0x51d478 LDR	Q21, [X16, X2]

(3289) 0x51d47c LDR	Q20, [X15, X2]

(3289) 0x51d480 FMLA	V20.2D, V21.2D, V30.2D

(3289) 0x51d484 STR	Q20, [X15, X2]

(3289) 0x51d488 LDR	Q19, [X16, X0]

(3289) 0x51d48c LDR	Q18, [X15, X0]

(3289) 0x51d490 FMLA	V18.2D, V19.2D, V30.2D

(3289) 0x51d494 STR	Q18, [X15, X0]

(3289) 0x51d498 LDR	Q17, [X16, X3]

(3289) 0x51d49c LDR	Q16, [X15, X3]

(3289) 0x51d4a0 FMLA	V16.2D, V17.2D, V30.2D

(3289) 0x51d4a4 STR	Q16, [X15, X3]

(3289) 0x51d4a8 CMP	X18, X17

(3289) 0x51d4ac B.NE	51d408

0x51d4b0 AND	X9, X4, #0xfffffffe

0x51d4b4 TBZ	W4, #0, 51d4d0

0x51d4b8 ADD	X1, X1, X9

0x51d4bc UBFM	X4, X1, #61, #60

0x51d4c0 LDR	D30, [X8, X4]

0x51d4c4 LDR	D7, [X6, X4]

0x51d4c8 FMADD	D31, D31, D30, D7

0x51d4cc STR	D31, [X6, X4]

0x51d4d0 LDR	X21, [SP, #32]

0x51d4d4 LDP	X19, X20, [SP, #16]

0x51d4d8 LDP	X29, X30, [SP], #48

0x51d4dc RET

0x51d4e0 ADD	X4, X4, #1

0x51d4e4 MOVZ	X2, #0

0x51d4e8 B	51d2e0

0x51d4ec SUB	X15, X0, X1

0x51d4f0 ANDS	X5, X15, #0x7

0x51d4f4 B.EQ	51d5bc

0x51d4f8 CMP	X5, #1

0x51d4fc B.EQ	51d5a0

0x51d500 CMP	X5, #2

0x51d504 B.EQ	51d58c

0x51d508 CMP	X5, #3

0x51d50c B.EQ	51d578

0x51d510 CMP	X5, #4

0x51d514 B.EQ	51d564

0x51d518 CMP	X5, #5

0x51d51c B.EQ	51d550

0x51d520 CMP	X5, #6

0x51d524 B.EQ	51d53c

0x51d528 LDR	D6, [X8, X1,LSL #3]

0x51d52c LDR	D5, [X6, X1,LSL #3]

0x51d530 FMADD	D4, D31, D6, D5

0x51d534 STR	D4, [X6, X1,LSL #3]

0x51d538 ADD	X1, X1, #1

0x51d53c LDR	D3, [X8, X1,LSL #3]

0x51d540 LDR	D2, [X6, X1,LSL #3]

0x51d544 FMADD	D1, D31, D3, D2

0x51d548 STR	D1, [X6, X1,LSL #3]

0x51d54c ADD	X1, X1, #1

0x51d550 LDR	D29, [X8, X1,LSL #3]

0x51d554 LDR	D0, [X6, X1,LSL #3]

0x51d558 FMADD	D28, D31, D29, D0

0x51d55c STR	D28, [X6, X1,LSL #3]

0x51d560 ADD	X1, X1, #1

0x51d564 LDR	D27, [X8, X1,LSL #3]

0x51d568 LDR	D26, [X6, X1,LSL #3]

0x51d56c FMADD	D25, D31, D27, D26

0x51d570 STR	D25, [X6, X1,LSL #3]

0x51d574 ADD	X1, X1, #1

0x51d578 LDR	D24, [X8, X1,LSL #3]

0x51d57c LDR	D23, [X6, X1,LSL #3]

0x51d580 FMADD	D22, D31, D24, D23

0x51d584 STR	D22, [X6, X1,LSL #3]

0x51d588 ADD	X1, X1, #1

0x51d58c LDR	D21, [X8, X1,LSL #3]

0x51d590 LDR	D20, [X6, X1,LSL #3]

0x51d594 FMADD	D19, D31, D21, D20

0x51d598 STR	D19, [X6, X1,LSL #3]

0x51d59c ADD	X1, X1, #1

0x51d5a0 LDR	D18, [X8, X1,LSL #3]

0x51d5a4 LDR	D17, [X6, X1,LSL #3]

0x51d5a8 FMADD	D16, D31, D18, D17

0x51d5ac STR	D16, [X6, X1,LSL #3]

0x51d5b0 ADD	X1, X1, #1

0x51d5b4 CMP	X0, X1

0x51d5b8 B.EQ	51d4d0

(3288) 0x51d5bc LDR	D30, [X8, X1,LSL #3]

(3288) 0x51d5c0 ADD	X16, X1, #1

(3288) 0x51d5c4 ADD	X10, X1, #2

(3288) 0x51d5c8 ADD	X17, X1, #3

(3288) 0x51d5cc ADD	X7, X1, #4

(3288) 0x51d5d0 LDR	D7, [X6, X1,LSL #3]

(3288) 0x51d5d4 ADD	X11, X1, #5

(3288) 0x51d5d8 ADD	X12, X1, #6

(3288) 0x51d5dc ADD	X13, X1, #7

(3288) 0x51d5e0 FMADD	D6, D31, D30, D7

(3288) 0x51d5e4 STR	D6, [X6, X1,LSL #3]

(3288) 0x51d5e8 ADD	X1, X1, #8

(3288) 0x51d5ec LDR	D5, [X8, X16,LSL #3]

(3288) 0x51d5f0 LDR	D4, [X6, X16,LSL #3]

(3288) 0x51d5f4 FMADD	D3, D31, D5, D4

(3288) 0x51d5f8 STR	D3, [X6, X16,LSL #3]

(3288) 0x51d5fc LDR	D2, [X8, X10,LSL #3]

(3288) 0x51d600 LDR	D1, [X6, X10,LSL #3]

(3288) 0x51d604 FMADD	D29, D31, D2, D1

(3288) 0x51d608 STR	D29, [X6, X10,LSL #3]

(3288) 0x51d60c LDR	D0, [X8, X17,LSL #3]

(3288) 0x51d610 LDR	D28, [X6, X17,LSL #3]

(3288) 0x51d614 FMADD	D27, D31, D0, D28

(3288) 0x51d618 STR	D27, [X6, X17,LSL #3]

(3288) 0x51d61c LDR	D26, [X8, X7,LSL #3]

(3288) 0x51d620 LDR	D25, [X6, X7,LSL #3]

(3288) 0x51d624 FMADD	D24, D31, D26, D25

(3288) 0x51d628 STR	D24, [X6, X7,LSL #3]

(3288) 0x51d62c LDR	D23, [X8, X11,LSL #3]

(3288) 0x51d630 LDR	D22, [X6, X11,LSL #3]

(3288) 0x51d634 FMADD	D21, D31, D23, D22

(3288) 0x51d638 STR	D21, [X6, X11,LSL #3]

(3288) 0x51d63c LDR	D20, [X8, X12,LSL #3]

(3288) 0x51d640 LDR	D19, [X6, X12,LSL #3]

(3288) 0x51d644 FMADD	D18, D31, D20, D19

(3288) 0x51d648 STR	D18, [X6, X12,LSL #3]

(3288) 0x51d64c LDR	D17, [X8, X13,LSL #3]

(3288) 0x51d650 LDR	D16, [X6, X13,LSL #3]

(3288) 0x51d654 FMADD	D30, D31, D17, D16

(3288) 0x51d658 STR	D30, [X6, X13,LSL #3]

(3288) 0x51d65c CMP	X0, X1

(3288) 0x51d660 B.NE	51d5bc

0x51d664 B	51d4d0

Coverage (%)	Name	Module
►98.45+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	vector.c:449-452
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:449-452.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.00 to 15.50 cycles (1.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 33% of vector register length is used (average across all VPU instructions).

Details

28% of VPU instructions are used in vector version (process two or more data elements in vector registers):

41% of VPU loads are used in vector version.
38% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
43% of VPU fused multiply-add instructions are used in vector version.
3% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 22 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:449
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:449

Matching between your function (in the source code) and the binary function

The binary function is composed of 44 FP arithmetical operations:

22: addition or subtraction (all inside FMA instructions)
22: multiply (all inside FMA instructions)

The binary function does not load or store any data.

General properties

nb instructions	156
nb uops	156
loop length	624
used w registers	1
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	24
used q registers	14
used v registers	16
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.50 cycles
front end	19.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	15.75	15.75	15.75	15.75	7.75	7.75	7.75	7.75	18.00	18.00	18.00	1.50	1.50
cycles	13.00	13.00	15.75	15.75	15.75	15.75	7.75	7.75	7.75	7.75	18.00	18.00	18.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	19.50
Dispatch	18.00
DIV/SQRT	5.00-20.00
Overall L1	19.50-20.00

Vectorization ratios

INT

all	25%
load	41%
store	38%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	3%

all	46%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	46%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	28%
load	41%
store	38%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	43%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

Vector efficiency ratios

INT

all	33%
load	36%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
other	28%

all	36%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	36%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	33%
load	36%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	35%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 51d2a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 410200 <@plt_start@+0x1e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X4, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X2, X4, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 51d4e0 <hypre_SeqVectorAxpy._omp_fn.0+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X4, X1, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d4d0 <hypre_SeqVectorAxpy._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X3, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X8, X6, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 51d4ec <hypre_SeqVectorAxpy._omp_fn.0+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X15, X6, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X15, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d4ec <hypre_SeqVectorAxpy._omp_fn.0+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X4, #1, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP V30.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD X16, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X17, X10, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X12, X11, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X14, X13, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d408 <hypre_SeqVectorAxpy._omp_fn.0+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d3ec <hypre_SeqVectorAxpy._omp_fn.0+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d3d8 <hypre_SeqVectorAxpy._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d3c4 <hypre_SeqVectorAxpy._omp_fn.0+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d3b0 <hypre_SeqVectorAxpy._omp_fn.0+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d39c <hypre_SeqVectorAxpy._omp_fn.0+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d388 <hypre_SeqVectorAxpy._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q22, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
MOVZ X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q23, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V22.2D, V23.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q22, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR Q21, [X16, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q20, [X15, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V20.2D, V21.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q20, [X15, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q19, [X16, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q18, [X15, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V18.2D, V19.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q18, [X15, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q17, [X16, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q16, [X15, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V16.2D, V17.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q16, [X15, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q7, [X16, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q6, [X15, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V6.2D, V7.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q6, [X15, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q5, [X16, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q4, [X15, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V4.2D, V5.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q4, [X15, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q3, [X16, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q2, [X15, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V2.2D, V3.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q2, [X15, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d4b0 <hypre_SeqVectorAxpy._omp_fn.0+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X9, X4, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
TBZ W4, #0, 51d4d0 <hypre_SeqVectorAxpy._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X4, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X8, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D7, [X6, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D31, D31, D30, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D31, [X6, X4]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 51d2e0 <hypre_SeqVectorAxpy._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X15, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X5, X15, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d5bc <hypre_SeqVectorAxpy._omp_fn.0+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d5a0 <hypre_SeqVectorAxpy._omp_fn.0+0x2f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d58c <hypre_SeqVectorAxpy._omp_fn.0+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d578 <hypre_SeqVectorAxpy._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d564 <hypre_SeqVectorAxpy._omp_fn.0+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d550 <hypre_SeqVectorAxpy._omp_fn.0+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d53c <hypre_SeqVectorAxpy._omp_fn.0+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D5, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D4, D31, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D4, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D2, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D1, D31, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D1, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D29, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D0, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D28, D31, D29, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D28, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D26, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D25, D31, D27, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D25, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D24, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D23, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D22, D31, D24, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D22, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D20, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D19, D31, D21, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D19, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D17, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D16, D31, D18, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D16, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 51d4d0 <hypre_SeqVectorAxpy._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51d4d0 <hypre_SeqVectorAxpy._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	vector.c:449-452
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:449-452.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 33% of vector register length is used (average across all VPU instructions).

Details

28% of VPU instructions are used in vector version (process two or more data elements in vector registers):

41% of VPU loads are used in vector version.
38% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
43% of VPU fused multiply-add instructions are used in vector version.
3% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 22 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:449
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:449

Matching between your function (in the source code) and the binary function

The binary function is composed of 44 FP arithmetical operations:

22: addition or subtraction (all inside FMA instructions)
22: multiply (all inside FMA instructions)

The binary function does not load or store any data.

General properties

nb instructions	156
nb uops	156
loop length	624
used w registers	1
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	24
used q registers	14
used v registers	16
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.50 cycles
front end	19.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	15.75	15.75	15.75	15.75	7.75	7.75	7.75	7.75	18.00	18.00	18.00	1.50	1.50
cycles	13.00	13.00	15.75	15.75	15.75	15.75	7.75	7.75	7.75	7.75	18.00	18.00	18.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	19.50
Dispatch	18.00
DIV/SQRT	5.00-20.00
Overall L1	19.50-20.00

Vectorization ratios

INT

all	25%
load	41%
store	38%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	3%

all	46%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	46%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	28%
load	41%
store	38%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	43%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

Vector efficiency ratios

INT

all	33%
load	36%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
other	28%

all	36%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	36%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	33%
load	36%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	35%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 51d2a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 410200 <@plt_start@+0x1e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X4, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X2, X4, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 51d4e0 <hypre_SeqVectorAxpy._omp_fn.0+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X4, X1, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d4d0 <hypre_SeqVectorAxpy._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X3, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X8, X6, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 51d4ec <hypre_SeqVectorAxpy._omp_fn.0+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X15, X6, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X15, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d4ec <hypre_SeqVectorAxpy._omp_fn.0+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X4, #1, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP V30.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD X16, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X17, X10, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X12, X11, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X14, X13, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d408 <hypre_SeqVectorAxpy._omp_fn.0+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d3ec <hypre_SeqVectorAxpy._omp_fn.0+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d3d8 <hypre_SeqVectorAxpy._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d3c4 <hypre_SeqVectorAxpy._omp_fn.0+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d3b0 <hypre_SeqVectorAxpy._omp_fn.0+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d39c <hypre_SeqVectorAxpy._omp_fn.0+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d388 <hypre_SeqVectorAxpy._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q22, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
MOVZ X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q23, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V22.2D, V23.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q22, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR Q21, [X16, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q20, [X15, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V20.2D, V21.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q20, [X15, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q19, [X16, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q18, [X15, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V18.2D, V19.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q18, [X15, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q17, [X16, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q16, [X15, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V16.2D, V17.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q16, [X15, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q7, [X16, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q6, [X15, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V6.2D, V7.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q6, [X15, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q5, [X16, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q4, [X15, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V4.2D, V5.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q4, [X15, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q3, [X16, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q2, [X15, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMLA V2.2D, V3.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
STR Q2, [X15, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d4b0 <hypre_SeqVectorAxpy._omp_fn.0+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X9, X4, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
TBZ W4, #0, 51d4d0 <hypre_SeqVectorAxpy._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X4, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X8, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D7, [X6, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D31, D31, D30, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D31, [X6, X4]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 51d2e0 <hypre_SeqVectorAxpy._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X15, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X5, X15, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d5bc <hypre_SeqVectorAxpy._omp_fn.0+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d5a0 <hypre_SeqVectorAxpy._omp_fn.0+0x2f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d58c <hypre_SeqVectorAxpy._omp_fn.0+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d578 <hypre_SeqVectorAxpy._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d564 <hypre_SeqVectorAxpy._omp_fn.0+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d550 <hypre_SeqVectorAxpy._omp_fn.0+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51d53c <hypre_SeqVectorAxpy._omp_fn.0+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D5, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D4, D31, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D4, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D2, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D1, D31, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D1, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D29, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D0, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D28, D31, D29, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D28, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D26, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D25, D31, D27, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D25, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D24, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D23, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D22, D31, D24, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D22, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D20, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D19, D31, D21, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D19, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D17, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D16, D31, D18, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D16, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 51d4d0 <hypre_SeqVectorAxpy._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51d4d0 <hypre_SeqVectorAxpy._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorAxpy._omp_fn.0–	1.25	0.52
○Loop 3289 - vector.c:452-452 - exec	1.25	0.39
○Loop 3288 - vector.c:452-452 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

FMA

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

FMA

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code