OV - exec - Loop 113

	Loop Id: 113	Module: exec	Source: par_coarsen.c:2332-2334	Coverage: 0.05%

0x42791c LDR	X12, [X0]    [1]

0x427920 UBFM	X13, X12, #61, #60

0x427924 LDR	D6, [X9, X13]    [3]

0x427928 FCMPE	D6, D31

0x42792c B.GT	427a98

0x427930 LDR	X14, [X0, #8]    [5]

0x427934 ADD	X0, X0, #8

0x427938 UBFM	X15, X14, #61, #60

0x42793c LDR	D5, [X9, X15]    [3]

0x427940 FCMPE	D5, D31

0x427944 B.GT	427a7c

0x427948 LDR	X16, [X0, #8]    [7]

0x42794c UBFM	X17, X16, #61, #60

0x427950 LDR	D4, [X9, X17]    [3]

0x427954 FCMPE	D4, D31

0x427958 B.GT	427a60

0x42795c LDR	X18, [X0, #16]    [9]

0x427960 UBFM	X30, X18, #61, #60

0x427964 LDR	D3, [X9, X30]    [3]

0x427968 FCMPE	D3, D31

0x42796c B.GT	427a44

0x427970 LDR	X20, [X0, #24]    [11]

0x427974 UBFM	X21, X20, #61, #60

0x427978 LDR	D2, [X9, X21]    [3]

0x42797c FCMPE	D2, D31

0x427980 B.GT	427a28

0x427984 LDR	X19, [X0, #32]    [13]

0x427988 UBFM	X1, X19, #61, #60

0x42798c LDR	D1, [X9, X1]    [3]

0x427990 FCMPE	D1, D31

0x427994 B.GT	427a0c

0x427998 LDR	X3, [X0, #40]    [15]

0x42799c UBFM	X2, X3, #61, #60

0x4279a0 LDR	D0, [X9, X2]    [3]

0x4279a4 FCMPE	D0, D31

0x4279a8 B.GT	4279f0

0x4279ac LDR	X7, [X0, #48]    [17]

0x4279b0 UBFM	X8, X7, #61, #60

0x4279b4 LDR	D30, [X9, X8]    [3]

0x4279b8 FCMPE	D30, D31

0x4279bc B.GT	4279dc

0x4279c0 ADD	X0, X0, #56

0x4279c4 CMP	X10, X0

0x4279c8 B.NE	42791c

0x4279dc ADD	X0, X0, #56

0x4279e0 STR	X5, [X4, X8]    [2]

0x4279e4 CMP	X10, X0

0x4279e8 B.NE	42791c

0x4279f0 STR	X5, [X4, X2]    [2]

0x4279f4 LDR	X7, [X0, #48]    [16]

0x4279f8 UBFM	X8, X7, #61, #60

0x4279fc LDR	D30, [X9, X8]    [3]

0x427a00 FCMPE	D30, D31

0x427a04 B.GT	4279dc

0x427a08 B	4279c0

0x427a0c STR	X5, [X4, X1]    [2]

0x427a10 LDR	X3, [X0, #40]    [14]

0x427a14 UBFM	X2, X3, #61, #60

0x427a18 LDR	D0, [X9, X2]    [3]

0x427a1c FCMPE	D0, D31

0x427a20 B.GT	4279f0

0x427a24 B	4279ac

0x427a28 STR	X5, [X4, X21]    [2]

0x427a2c LDR	X19, [X0, #32]    [12]

0x427a30 UBFM	X1, X19, #61, #60

0x427a34 LDR	D1, [X9, X1]    [3]

0x427a38 FCMPE	D1, D31

0x427a3c B.GT	427a0c

0x427a40 B	427998

0x427a44 STR	X5, [X4, X30]    [2]

0x427a48 LDR	X20, [X0, #24]    [10]

0x427a4c UBFM	X21, X20, #61, #60

0x427a50 LDR	D2, [X9, X21]    [3]

0x427a54 FCMPE	D2, D31

0x427a58 B.GT	427a28

0x427a5c B	427984

0x427a60 STR	X5, [X4, X17]    [2]

0x427a64 LDR	X18, [X0, #16]    [8]

0x427a68 UBFM	X30, X18, #61, #60

0x427a6c LDR	D3, [X9, X30]    [3]

0x427a70 FCMPE	D3, D31

0x427a74 B.GT	427a44

0x427a78 B	427970

0x427a7c STR	X5, [X4, X15]    [2]

0x427a80 LDR	X16, [X0, #8]    [6]

0x427a84 UBFM	X17, X16, #61, #60

0x427a88 LDR	D4, [X9, X17]    [3]

0x427a8c FCMPE	D4, D31

0x427a90 B.GT	427a60

0x427a94 B	42795c

0x427a98 STR	X5, [X4, X13]    [2]

0x427a9c ADD	X0, X0, #8

0x427aa0 LDR	X14, [X0]    [4]

0x427aa4 UBFM	X15, X14, #61, #60

0x427aa8 LDR	D5, [X9, X15]    [3]

0x427aac FCMPE	D5, D31

0x427ab0 B.GT	427a7c

0x427ab4 B	427948

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2332 - 2334

--------------------------------------------------------------------------------

2332:            if (measure_array[i] > 1)

2333:            {

2334:               CF_marker[i] = 1;

Coverage (%)	Name	Source Location	Module
►98.47+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.02+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2338	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P6,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.4
Source	par_coarsen.c:2332-2334
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	15.00
CQA cycles if fully vectorized	3.75
Front-end cycles	12.25
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	5.25
P3 cycles	5.25
P4 cycles	5.25
P5 cycles	5.25
P6 cycles	15.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	12.67
P11 cycles	12.67
P12 cycles	12.67
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	98.00
Nb uops	98.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P6,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.4
Source	par_coarsen.c:2332-2334
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	15.00
CQA cycles if fully vectorized	3.75
Front-end cycles	12.25
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	5.25
P3 cycles	5.25
P4 cycles	5.25
P5 cycles	5.25
P6 cycles	15.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	12.67
P11 cycles	12.67
P12 cycles	12.67
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	98.00
Nb uops	98.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.4
Source file and lines	par_coarsen.c:2332-2334
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332-2334.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 5.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 15.00 to 3.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	98
nb uops	98
loop length	392
used w registers	0
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	9
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.25 cycles
front end	12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.00	12.00	5.25	5.25	5.25	5.25	15.00	0.00	0.00	0.00	12.67	12.67	12.67	4.00	4.00
cycles	12.00	12.00	5.25	5.25	5.25	5.25	15.00	0.00	0.00	0.00	12.67	12.67	12.67	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Dispatch	15.00
Overall L1	15.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42791c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X12, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X13, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X9, X13]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D6, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a98 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X9, X15]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D5, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a7c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X17, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X9, X17]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D4, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a60 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X0, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X30, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X9, X30]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D3, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a44 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [X0, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X21, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X9, X21]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D2, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a28 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [X0, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X1, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D1, [X9, X1]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D1, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a0c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X0, #40]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X2, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X9, X2]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D0, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 4279f0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X0, #48]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X8, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X9, X8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D30, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 4279dc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 42791c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X4, X8]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 42791c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X2]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [X0, #48]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X8, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X9, X8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D30, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 4279dc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4279c0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X1]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X0, #40]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X2, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X9, X2]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D0, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 4279f0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4279ac <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X21]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X0, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X1, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D1, [X9, X1]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D1, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a0c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427998 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X30]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X0, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X21, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X9, X21]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D2, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a28 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427984 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X17]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [X0, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X30, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X9, X30]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D3, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a44 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427970 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X15]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X17, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X9, X17]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D4, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a60 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 42795c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X13]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X9, X15]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D5, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a7c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427948 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.4
Source file and lines	par_coarsen.c:2332-2334
Module	exec

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 5.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	98
nb uops	98
loop length	392
used w registers	0
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	9
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.25 cycles
front end	12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.00	12.00	5.25	5.25	5.25	5.25	15.00	0.00	0.00	0.00	12.67	12.67	12.67	4.00	4.00
cycles	12.00	12.00	5.25	5.25	5.25	5.25	15.00	0.00	0.00	0.00	12.67	12.67	12.67	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Dispatch	15.00
Overall L1	15.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42791c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X12, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X13, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X9, X13]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D6, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a98 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X9, X15]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D5, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a7c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X17, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X9, X17]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D4, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a60 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X0, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X30, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X9, X30]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D3, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a44 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [X0, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X21, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X9, X21]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D2, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a28 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [X0, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X1, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D1, [X9, X1]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D1, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a0c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X0, #40]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X2, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X9, X2]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D0, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 4279f0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X0, #48]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X8, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X9, X8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D30, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 4279dc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 42791c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X4, X8]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 42791c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X2]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [X0, #48]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X8, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X9, X8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D30, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 4279dc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4279c0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X1]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X0, #40]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X2, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X9, X2]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D0, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 4279f0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4279ac <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X21]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X0, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X1, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D1, [X9, X1]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D1, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a0c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427998 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X30]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X0, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X21, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X9, X21]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D2, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a28 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427984 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X17]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [X0, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X30, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X9, X30]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D3, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a44 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427970 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X15]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X17, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X9, X17]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D4, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a60 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 42795c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X13]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X9, X15]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D5, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.GT 427a7c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427948 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code