OV - exec - Loop 114

	Loop Id: 114	Module: exec	Source: par_coarsen.c:2446-2477 [...]	Coverage: 0.03%

0x427b90 LDR	X12, [X1]

0x427b94 UBFM	X18, X12, #61, #60

0x427b98 ADD	X30, X3, X12,LSL #3

0x427b9c LDR	D30, [X13, X18]

0x427ba0 FCMPE	D30, D31

0x427ba4 B.MI	427bd4

0x427ba8 LDR	X14, [X3, X18]

0x427bac CMP	X14, #0

0x427bb0 B.LE	427bd8

0x427bb4 STR	X15, [X3, X18]

0x427bb8 ADD	X1, X1, #8

0x427bbc CMP	X7, X1

0x427bc0 B.NE	427b90

0x427bd4 STR	X8, [X3, X18]

0x427bd8 ADD	X20, X18, #8

0x427bdc LDR	X0, [X17, X18]

0x427be0 ADD	X21, X17, X20

0x427be4 LDR	X4, [X17, X20]

0x427be8 CMP	X0, X4

0x427bec B.GE	427c14

  (117) 0x427bf0 LDR	X19, [X11, X0,LSL #3]

  (117) 0x427bf4 LDR	X2, [X3, X19,LSL #3]

  (117) 0x427bf8 CMP	X2, #0

  (117) 0x427bfc B.LE	427c6c

  (117) 0x427c00 STR	X8, [X30]

  (117) 0x427c04 ADD	X0, X0, #1

  (117) 0x427c08 LDR	X4, [X21]

  (117) 0x427c0c CMP	X4, X0

  (117) 0x427c10 B.GT	427bf0

0x427c14 LDR	X14, [X16, X18]

0x427c18 ADD	X6, X16, X20

0x427c1c LDR	X5, [X16, X20]

0x427c20 CMP	X14, X5

0x427c24 B.GE	427bb8

  (115) 0x427c28 LDR	X12, [X10, X14,LSL #3]

  (115) 0x427c2c LDR	X18, [X9, X12,LSL #3]

  (115) 0x427c30 CMP	X18, #0

  (115) 0x427c34 B.LE	427c5c

  (116) 0x427c38 STR	X8, [X30]

  (116) 0x427c3c ADD	X14, X14, #1

  (116) 0x427c40 LDR	X5, [X6]

  (116) 0x427c44 CMP	X14, X5

  (116) 0x427c48 B.GE	427bb8

  (116) 0x427c4c LDR	X12, [X10, X14,LSL #3]

  (116) 0x427c50 LDR	X18, [X9, X12,LSL #3]

  (116) 0x427c54 CMP	X18, #0

  (116) 0x427c58 B.GT	427c38

  (115) 0x427c5c ADD	X14, X14, #1

  (115) 0x427c60 CMP	X14, X5

  (115) 0x427c64 B.LT	427c28

0x427c68 B	427bb8

  (117) 0x427c6c ADD	X0, X0, #1

  (117) 0x427c70 CMP	X0, X4

  (117) 0x427c74 B.LT	427bf0

0x427c78 B	427c14

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2446 - 2477

--------------------------------------------------------------------------------

2446:        if(measure_array[i]<1.) CF_marker[i]= F_PT;

[...]

2453:        if (CF_marker[i] > 0) CF_marker[i] = C_PT;

[...]

2465: 	 for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2466:          {

2467: 	   /* j is the column number, or the local number of the point influencing i */

2468: 	   j = S_diag_j[jS];

2469: 	   if (CF_marker[j] > 0) /* j is a C-point */

2470: 	     CF_marker[i] = F_PT;

2471: 	 }

2472: 	 /* now the external part */

2473: 	 for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2474: 	 {

2475: 	   j = S_offd_j[jS];

2476: 	   if (CF_marker_offd[j] > 0) /* j is a C-point */

2477: 	     CF_marker[i] = F_PT;

Coverage (%)	Name	Source Location	Module
►98.44+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.56+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2492	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.63
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.7
Source	par_coarsen.c:2446-2446,par_coarsen.c:2453-2453,par_coarsen.c:2465-2465,par_coarsen.c:2473-2473
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.88
Front-end cycles	3.38
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	1.00
P14 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	2.63
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.7
Source	par_coarsen.c:2446-2446,par_coarsen.c:2453-2453,par_coarsen.c:2465-2465,par_coarsen.c:2473-2473
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.88
Front-end cycles	3.38
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	1.00
P14 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.7
Source file and lines	par_coarsen.c:2446-2477
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2446,2453,2465-2477.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2446,2453,2465,2473.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=25
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 25 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.33 cycles (2.62x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 0.87 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	27
nb uops	27
loop length	108
used w registers	0
used x registers	18
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	2.50	2.50	2.50	2.50	1.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00
cycles	3.50	3.50	2.50	2.50	2.50	2.50	1.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	3.50
Overall L1	3.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 427b90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X12, [X1]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X18, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X3, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D30, [X13, X18]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D30, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.MI 427bd4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X3, X18]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 427bd8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X15, [X3, X18]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 427b90 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X8, [X3, X18]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X20, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X17, X18]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X21, X17, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X4, [X17, X20]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 427c14 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X16, X18]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X16, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X5, [X16, X20]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
B.GE 427bb8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427bb8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427c14 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.7
Source file and lines	par_coarsen.c:2446-2477
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=25
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.33 cycles (2.62x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 0.87 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	27
nb uops	27
loop length	108
used w registers	0
used x registers	18
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	2.50	2.50	2.50	2.50	1.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00
cycles	3.50	3.50	2.50	2.50	2.50	2.50	1.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	3.50
Overall L1	3.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 427b90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X12, [X1]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X18, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X3, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D30, [X13, X18]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D30, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.MI 427bd4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X3, X18]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 427bd8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X15, [X3, X18]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 427b90 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X8, [X3, X18]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X20, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X17, X18]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X21, X17, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X4, [X17, X20]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 427c14 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X16, X18]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X16, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X5, [X16, X20]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
B.GE 427bb8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427bb8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427c14 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code