OV - exec - Loop 2216

	Loop Id: 2216	Module: exec	Source: ams.c:3672-3675	Coverage: 34.54%

0x4c4d0c LD1D	{Z4.D}, P7/Z, [X19, X0,LSL #3]    [3]

0x4c4d10 LD1D	{Z2.D}, P7/Z, [X6, X0,LSL #3]    [1]

0x4c4d14 LD1D	{Z3.D}, P7/Z, [X9, Z4.D,LSL #3]    [2]

0x4c4d18 ADD	X0, X0, X4

0x4c4d1c FMUL	Z2.D, P7/M, Z2.D, Z3.D

0x4c4d20 FNEG	Z2.D, P6/M, Z2.D

0x4c4d24 FADDA	D0, P7, D0, Z2.D

0x4c4d28 WHILELO	P7.D, X0, X7

0x4c4d2c B.NE	4c4d0c

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3672 - 3675

--------------------------------------------------------------------------------

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

Coverage (%)	Name	Source Location	Module
►98.50+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.43+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_ParCSRRelaxThreads	ams.c:3662	exec
○	hypre_BoomerAMGCycle	par_cycle.c:394	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	5.33
Bottlenecks
Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source	ams.c:3672-3675
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	1.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.00
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	5.33
Bottlenecks
Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source	ams.c:3672-3675
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	1.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.00
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source file and lines	ams.c:3672-3675
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3672-3675.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: multiply

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	9
nb uops	9
loop length	36
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	1
used q registers	0
used v registers	0
used z registers	3
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.13 cycles
front end	1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	1.50	1.50	0.00	0.00	1.50	1.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	1.50	1.50	1.00	1.00	1.50	1.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	1.13
Dispatch	1.50
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4c4d0c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z4.D}, P7/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P7/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X9, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X0, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z2.D, P7/M, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FNEG Z2.D, P6/M, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADDA D0, P7, D0, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
WHILELO P7.D, X0, X7	1	0	0	0	0	1	0	0	0	0	0	3	2	N/A
B.NE 4c4d0c <hypre_ParCSRRelaxThreads._omp_fn.1+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source file and lines	ams.c:3672-3675
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3672-3675.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: multiply

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	9
nb uops	9
loop length	36
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	1
used q registers	0
used v registers	0
used z registers	3
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.13 cycles
front end	1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	1.50	1.50	0.00	0.00	1.50	1.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	1.50	1.50	1.00	1.00	1.50	1.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	1.13
Dispatch	1.50
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4c4d0c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z4.D}, P7/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P7/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X9, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X0, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z2.D, P7/M, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FNEG Z2.D, P6/M, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADDA D0, P7, D0, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
WHILELO P7.D, X0, X7	1	0	0	0	0	1	0	0	0	0	0	3	2	N/A
B.NE 4c4d0c <hypre_ParCSRRelaxThreads._omp_fn.1+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code