OV - exec - Loop 2561

	Loop Id: 2561	Module: exec	Source: par_csr_matop.c:127-242 [...]	Coverage: 0.01%

0x4e2424 ORR	X3, XZR, X20

0x4e2428 LDR	X12, [SP, #112]

0x4e242c CBNZ	X12, 4e24f8

0x4e2434 LDR	X17, [X28, X2,LSL #3]

0x4e2438 ORR	X7, XZR, X25

0x4e243c LDR	X12, [X28, X15]

0x4e2440 CMP	X17, X12

0x4e2444 B.GE	4e24bc

  (2565) 0x4e2448 LDR	X25, [X6, X17,LSL #3]

  (2565) 0x4e244c UBFM	X18, X25, #61, #60

  (2565) 0x4e2450 ADD	X30, X18, #8

  (2565) 0x4e2454 LDR	X12, [X23, X18]

  (2565) 0x4e2458 ADD	X25, X23, X30

  (2565) 0x4e245c LDR	X16, [X23, X30]

  (2565) 0x4e2460 CMP	X12, X16

  (2565) 0x4e2464 B.GE	4e24a4

  (2565) 0x4e2468 ORR	X13, XZR, X5

  (2565) 0x4e246c STR	X0, [SP, #104]

    (2568) 0x4e2470 LDR	X0, [X21, X12,LSL #3]

    (2568) 0x4e2474 UBFM	X5, X0, #61, #60

    (2568) 0x4e2478 LDR	X0, [X19, X5]

    (2568) 0x4e247c CMP	X20, X0

    (2568) 0x4e2480 B.LE	4e25d0

    (2568) 0x4e2484 STR	X3, [X19, X5]

    (2568) 0x4e2488 ADD	X12, X12, #1

    (2568) 0x4e248c ADD	X3, X3, #1

    (2568) 0x4e2490 LDR	X16, [X25]

    (2568) 0x4e2494 CMP	X16, X12

    (2568) 0x4e2498 B.GT	4e2470

  (2565) 0x4e249c LDR	X0, [SP, #104]

  (2565) 0x4e24a0 ORR	X5, XZR, X13

  (2565) 0x4e24a4 CBNZ	X5, 4e2618

  (2565) 0x4e24a8 LDR	X18, [X28, X15]

  (2565) 0x4e24ac ADD	X17, X17, #1

  (2565) 0x4e24b0 CMP	X18, X17

  (2565) 0x4e24b4 B.GT	4e2448

0x4e24b8 ORR	X25, XZR, X7

0x4e24bc STR	X20, [X0, X2,LSL #3]

0x4e24c0 ADD	X15, X15, #8

0x4e24c4 LDR	X20, [SP, #120]

0x4e24c8 STR	X14, [X1, X2,LSL #3]

0x4e24cc ADD	X2, X2, #1

0x4e24d0 CMP	X20, X2

0x4e24d4 B.EQ	4e268c

0x4e24d8 LDR	X13, [SP, #128]

0x4e24dc ORR	X14, XZR, X11

0x4e24e0 ORR	X20, XZR, X3

0x4e24e4 CBZ	X13, 4e2424

0x4e24f8 LDR	X30, [X10, X2,LSL #3]

0x4e24fc LDR	X7, [X10, X15]

0x4e2500 CMP	X30, X7

0x4e2504 B.GE	4e2430

0x4e2508 LDR	X7, [SP, #184]

0x4e250c ORR	X11, XZR, X14

0x4e2510 STP	X5, X24, [SP, #144]

0x4e2514 HINT	#0

0x4e2518 HINT	#0

0x4e251c HINT	#0

  (2560) 0x4e2520 LDR	X24, [X4, X30,LSL #3]

  (2560) 0x4e2524 UBFM	X5, X24, #61, #60

  (2560) 0x4e2528 ADD	X24, X5, #8

  (2560) 0x4e252c LDR	X12, [X7, X5]

  (2560) 0x4e2530 ADD	X18, X7, X24

  (2560) 0x4e2534 LDR	X16, [X7, X24]

  (2560) 0x4e2538 CMP	X12, X16

  (2560) 0x4e253c B.GE	4e2578

  (2560) 0x4e2540 STR	X0, [SP, #104]

    (2563) 0x4e2544 LDR	X17, [X25, X12,LSL #3]

    (2563) 0x4e2548 ADD	X0, X22, X17

    (2563) 0x4e254c UBFM	X13, X0, #61, #60

    (2563) 0x4e2550 LDR	X17, [X19, X13]

    (2563) 0x4e2554 CMP	X14, X17

    (2563) 0x4e2558 B.LE	4e25e8

    (2563) 0x4e255c STR	X11, [X19, X13]

    (2563) 0x4e2560 ADD	X12, X12, #1

    (2563) 0x4e2564 ADD	X11, X11, #1

    (2563) 0x4e2568 LDR	X16, [X18]

    (2563) 0x4e256c CMP	X16, X12

    (2563) 0x4e2570 B.GT	4e2544

  (2560) 0x4e2574 LDR	X0, [SP, #104]

  (2560) 0x4e2578 LDR	X13, [X8, X5]

  (2560) 0x4e257c ADD	X5, X8, X24

  (2560) 0x4e2580 LDR	X18, [X8, X24]

  (2560) 0x4e2584 CMP	X13, X18

  (2560) 0x4e2588 B.GE	4e25b8

    (2562) 0x4e258c LDR	X24, [X26, X13,LSL #3]

    (2562) 0x4e2590 UBFM	X17, X24, #61, #60

    (2562) 0x4e2594 LDR	X12, [X19, X17]

    (2562) 0x4e2598 CMP	X20, X12

    (2562) 0x4e259c B.LE	4e25f8

    (2562) 0x4e25a0 STR	X3, [X19, X17]

    (2562) 0x4e25a4 ADD	X13, X13, #1

    (2562) 0x4e25a8 ADD	X3, X3, #1

    (2562) 0x4e25ac LDR	X18, [X5]

    (2562) 0x4e25b0 CMP	X18, X13

    (2562) 0x4e25b4 B.GT	4e258c

  (2560) 0x4e25b8 LDR	X16, [X10, X15]

  (2560) 0x4e25bc ADD	X30, X30, #1

  (2560) 0x4e25c0 CMP	X16, X30

  (2560) 0x4e25c4 B.GT	4e2520

0x4e25c8 LDP	X5, X24, [SP, #144]

0x4e25cc B	4e2434

    (2568) 0x4e25d0 ADD	X12, X12, #1

    (2568) 0x4e25d4 CMP	X12, X16

    (2568) 0x4e25d8 B.LT	4e2470

  (2565) 0x4e25dc LDR	X0, [SP, #104]

  (2565) 0x4e25e0 ORR	X5, XZR, X13

  (2565) 0x4e25e4 B	4e24a4

    (2563) 0x4e25e8 ADD	X12, X12, #1

    (2563) 0x4e25ec CMP	X12, X16

    (2563) 0x4e25f0 B.LT	4e2544

  (2560) 0x4e25f4 B	4e2574

    (2562) 0x4e25f8 ADD	X13, X13, #1

    (2562) 0x4e25fc CMP	X13, X18

    (2562) 0x4e2600 B.LT	4e258c

  (2560) 0x4e2604 LDR	X16, [X10, X15]

  (2560) 0x4e2608 ADD	X30, X30, #1

  (2560) 0x4e260c CMP	X16, X30

  (2560) 0x4e2610 B.GT	4e2520

0x4e2614 B	4e25c8

  (2565) 0x4e2618 LDR	X13, [X9, X18]

  (2565) 0x4e261c ADD	X18, X9, X30

  (2565) 0x4e2620 LDR	X25, [X9, X30]

  (2565) 0x4e2624 CMP	X13, X25

  (2565) 0x4e2628 B.GE	4e24a8

    (2566) 0x4e262c LDR	X30, [X27, X13,LSL #3]

    (2566) 0x4e2630 LDR	X12, [X24, X30,LSL #3]

    (2566) 0x4e2634 ADD	X16, X22, X12

    (2566) 0x4e2638 UBFM	X30, X16, #61, #60

    (2566) 0x4e263c LDR	X12, [X19, X30]

    (2566) 0x4e2640 CMP	X14, X12

    (2566) 0x4e2644 B.LE	4e267c

    (2567) 0x4e2648 STR	X11, [X19, X30]

    (2567) 0x4e264c ADD	X13, X13, #1

    (2567) 0x4e2650 ADD	X11, X11, #1

    (2567) 0x4e2654 LDR	X25, [X18]

    (2567) 0x4e2658 CMP	X25, X13

    (2567) 0x4e265c B.LE	4e24a8

    (2567) 0x4e2660 LDR	X30, [X27, X13,LSL #3]

    (2567) 0x4e2664 LDR	X12, [X24, X30,LSL #3]

    (2567) 0x4e2668 ADD	X16, X22, X12

    (2567) 0x4e266c UBFM	X30, X16, #61, #60

    (2567) 0x4e2670 LDR	X12, [X19, X30]

    (2567) 0x4e2674 CMP	X14, X12

    (2567) 0x4e2678 B.GT	4e2648

    (2566) 0x4e267c ADD	X13, X13, #1

    (2566) 0x4e2680 CMP	X25, X13

    (2566) 0x4e2684 B.GT	4e262c

  (2565) 0x4e2688 B	4e24a8

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242

--------------------------------------------------------------------------------

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module
►93.48+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►6.52+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_ParMatmul_RowSizes	par_csr_matop.c:286	exec
○	hypre_ParMatmul	par_csr_matop.c:811	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.57
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P10,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-135,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	1.17
Front-end cycles	3.75
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.17
P11 cycles	3.83
P12 cycles	4.00
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	30.00
Nb loads	NA
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.13
Vector-efficiency ratio load	29.17
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.57
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P10,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-135,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	1.17
Front-end cycles	3.75
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.17
P11 cycles	3.83
P12 cycles	4.00
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	30.00
Nb loads	NA
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.13
Vector-efficiency ratio load	29.17
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144-146,154-156,164-177,187,195,205-208,216-220,228-231,241-242.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144-146,187,241-242.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.17 to 1.17 cycles (3.57x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	33
nb uops	30
loop length	132
used w registers	0
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.75 cycles
front end	3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	4.17	3.83	4.00	1.50	1.50
cycles	3.50	3.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	4.17	3.83	4.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.75
Dispatch	4.17
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	29%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4e2434

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ORR X3, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X12, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X12, 4e24f8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X28, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X7, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X28, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4e24bc <hypre_ParMatmul_RowSizes._omp_fn.0+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X20, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X20, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [X1, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X20, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4e268c <hypre_ParMatmul_RowSizes._omp_fn.0+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X14, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CBZ X13, 4e2424 <hypre_ParMatmul_RowSizes._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X10, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X30, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4e2430 <hypre_ParMatmul_RowSizes._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X11, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X5, X24, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X5, X24, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 4e2434 <hypre_ParMatmul_RowSizes._omp_fn.0+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e25c8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:127-242
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	33
nb uops	30
loop length	132
used w registers	0
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.75 cycles
front end	3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	4.17	3.83	4.00	1.50	1.50
cycles	3.50	3.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	4.17	3.83	4.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.75
Dispatch	4.17
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	29%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4e2434

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ORR X3, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X12, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X12, 4e24f8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X28, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X7, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X28, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4e24bc <hypre_ParMatmul_RowSizes._omp_fn.0+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X20, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X20, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [X1, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X20, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4e268c <hypre_ParMatmul_RowSizes._omp_fn.0+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X14, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CBZ X13, 4e2424 <hypre_ParMatmul_RowSizes._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X10, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X30, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4e2430 <hypre_ParMatmul_RowSizes._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X11, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X5, X24, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X5, X24, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 4e2434 <hypre_ParMatmul_RowSizes._omp_fn.0+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e25c8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code