OV - exec - Loop 2570

	Loop Id: 2570	Module: exec	Source: par_csr_matop.c:865-989 [...]	Coverage: 0.01%

0x4e3194 LDR	X18, [SP, #168]

0x4e3198 ORR	X2, XZR, X20

0x4e319c ORR	X9, XZR, X25

0x4e31a0 CBNZ	X18, 4e3288

0x4e31a4 LDP	X12, X4, [X10]

0x4e31a8 CMP	X12, X4

0x4e31ac B.GE	4e3238

0x4e31b0 LDP	X17, X18, [SP, #176]

0x4e31b4 LDP	X13, X11, [SP, #192]

0x4e31b8 STR	X8, [SP, #120]

0x4e31bc HINT	#0

  (2575) 0x4e31c0 LDR	X23, [X16, X12,LSL #3]

  (2575) 0x4e31c4 LDR	D28, [X13, X12,LSL #3]

  (2575) 0x4e31c8 UBFM	X5, X23, #61, #60

  (2575) 0x4e31cc ADD	X8, X5, #8

  (2575) 0x4e31d0 LDR	X1, [X27, X5]

  (2575) 0x4e31d4 ADD	X15, X27, X8

  (2575) 0x4e31d8 LDR	X14, [X27, X8]

  (2575) 0x4e31dc CMP	X1, X14

  (2575) 0x4e31e0 B.GE	4e3220

    (2577) 0x4e31e4 LDR	X4, [X21, X1,LSL #3]

    (2577) 0x4e31e8 UBFM	X28, X2, #61, #60

    (2577) 0x4e31ec LDR	D6, [X22, X1,LSL #3]

    (2577) 0x4e31f0 UBFM	X23, X4, #61, #60

    (2577) 0x4e31f4 LDR	X3, [X0, X23]

    (2577) 0x4e31f8 FMUL	D7, D28, D6

    (2577) 0x4e31fc UBFM	X30, X3, #61, #60

    (2577) 0x4e3200 CMP	X20, X3

    (2577) 0x4e3204 B.GT	4e33c4

    (2577) 0x4e3208 LDR	D16, [X19, X30]

    (2577) 0x4e320c ADD	X1, X1, #1

    (2577) 0x4e3210 FADD	D17, D16, D7

    (2577) 0x4e3214 STR	D17, [X19, X30]

    (2577) 0x4e3218 CMP	X1, X14

    (2577) 0x4e321c B.LT	4e31e4

  (2575) 0x4e3220 CBNZ	X17, 4e33e8

  (2575) 0x4e3224 LDR	X4, [X10, #8]

  (2575) 0x4e3228 ADD	X12, X12, #1

  (2575) 0x4e322c CMP	X4, X12

  (2575) 0x4e3230 B.GT	4e31c0

0x4e3234 LDR	X8, [SP, #120]

0x4e3238 ADD	X8, X8, #1

0x4e323c ADD	X10, X10, #8

0x4e3240 LDR	X20, [SP, #144]

0x4e3244 LDR	X17, [SP, #160]

0x4e3248 ADD	X25, X20, #8

0x4e324c STR	X25, [SP, #144]

0x4e3250 CMP	X17, X8

0x4e3254 B.EQ	4e34c8

0x4e3258 LDR	X23, [SP, #152]

0x4e325c ORR	X25, XZR, X9

0x4e3260 ORR	X20, XZR, X2

0x4e3264 CBZ	X23, 4e3194

0x4e3288 LDR	X5, [SP, #144]

0x4e328c LDP	X13, X3, [X5]

0x4e3290 CMP	X13, X3

0x4e3294 B.GE	4e31a4

0x4e3298 LDR	X4, [SP, #112]

0x4e329c LDP	X14, X15, [SP, #272]

0x4e32a0 LDP	X18, X28, [SP, #296]

0x4e32a4 STP	X22, X16, [SP, #240]

0x4e32a8 ORR	X22, XZR, X10

0x4e32ac LDR	X23, [SP, #136]

0x4e32b0 STP	X21, X27, [SP, #224]

0x4e32b4 ORR	X21, XZR, X5

0x4e32b8 ORR	X27, XZR, X8

0x4e32bc LDR	X17, [SP, #256]

0x4e32c0 STP	X6, X7, [SP, #208]

0x4e32c4 LDR	X10, [SP, #264]

0x4e32c8 LDR	X16, [SP, #288]

0x4e32cc LDR	X3, [SP, #312]

  (2571) 0x4e32d0 LDR	X6, [X15, X13,LSL #3]

  (2571) 0x4e32d4 LDR	D31, [X16, X13,LSL #3]

  (2571) 0x4e32d8 UBFM	X7, X6, #61, #60

  (2571) 0x4e32dc ADD	X8, X7, #8

  (2571) 0x4e32e0 LDR	X1, [X10, X7]

  (2571) 0x4e32e4 ADD	X12, X10, X8

  (2571) 0x4e32e8 LDR	X11, [X10, X8]

  (2571) 0x4e32ec CMP	X1, X11

  (2571) 0x4e32f0 B.GE	4e3344

  (2571) 0x4e32f4 STP	X10, X28, [SP, #120]

  (2571) 0x4e32f8 HINT	#0

  (2571) 0x4e32fc HINT	#0

    (2573) 0x4e3300 UBFM	X28, X9, #61, #60

    (2573) 0x4e3304 LDR	X10, [X17, X1,LSL #3]

    (2573) 0x4e3308 LDR	D1, [X18, X1,LSL #3]

    (2573) 0x4e330c ADD	X30, X26, X10

    (2573) 0x4e3310 UBFM	X5, X30, #61, #60

    (2573) 0x4e3314 LDR	X6, [X0, X5]

    (2573) 0x4e3318 FMUL	D2, D31, D1

    (2573) 0x4e331c UBFM	X30, X6, #61, #60

    (2573) 0x4e3320 CMP	X25, X6

    (2573) 0x4e3324 B.GT	4e34a4

    (2573) 0x4e3328 LDR	D0, [X23, X30]

    (2573) 0x4e332c ADD	X1, X1, #1

    (2573) 0x4e3330 FADD	D3, D0, D2

    (2573) 0x4e3334 STR	D3, [X23, X30]

    (2573) 0x4e3338 CMP	X1, X11

    (2573) 0x4e333c B.LT	4e3300

  (2571) 0x4e3340 LDP	X10, X28, [SP, #120]

  (2571) 0x4e3344 ADD	X12, X14, X8

  (2571) 0x4e3348 LDR	X1, [X14, X7]

  (2571) 0x4e334c LDR	X30, [X14, X8]

  (2571) 0x4e3350 CMP	X1, X30

  (2571) 0x4e3354 B.GE	4e339c

  (2571) 0x4e3358 HINT	#0

  (2571) 0x4e335c HINT	#0

    (2572) 0x4e3360 LDR	X6, [X28, X1,LSL #3]

    (2572) 0x4e3364 UBFM	X8, X2, #61, #60

    (2572) 0x4e3368 LDR	D30, [X3, X1,LSL #3]

    (2572) 0x4e336c UBFM	X7, X6, #61, #60

    (2572) 0x4e3370 LDR	X5, [X0, X7]

    (2572) 0x4e3374 FMUL	D4, D31, D30

    (2572) 0x4e3378 UBFM	X11, X5, #61, #60

    (2572) 0x4e337c CMP	X20, X5

    (2572) 0x4e3380 B.GT	4e3470

    (2572) 0x4e3384 LDR	D29, [X19, X11]

    (2572) 0x4e3388 ADD	X1, X1, #1

    (2572) 0x4e338c FADD	D5, D29, D4

    (2572) 0x4e3390 STR	D5, [X19, X11]

    (2572) 0x4e3394 CMP	X1, X30

    (2572) 0x4e3398 B.LT	4e3360

  (2571) 0x4e339c LDR	X12, [X21, #8]

  (2571) 0x4e33a0 ADD	X13, X13, #1

  (2571) 0x4e33a4 CMP	X12, X13

  (2571) 0x4e33a8 B.GT	4e32d0

0x4e33ac ORR	X8, XZR, X27

0x4e33b0 ORR	X10, XZR, X22

0x4e33b4 LDP	X6, X7, [SP, #208]

0x4e33b8 LDP	X21, X27, [SP, #224]

0x4e33bc LDP	X22, X16, [SP, #240]

0x4e33c0 B	4e31a4

    (2577) 0x4e33c4 STR	X2, [X0, X23]

    (2577) 0x4e33c8 ADD	X1, X1, #1

    (2577) 0x4e33cc ADD	X2, X2, #1

    (2577) 0x4e33d0 STR	D7, [X19, X28]

    (2577) 0x4e33d4 STR	X4, [X24, X28]

    (2577) 0x4e33d8 LDR	X14, [X15]

    (2577) 0x4e33dc CMP	X14, X1

    (2577) 0x4e33e0 B.GT	4e31e4

  (2575) 0x4e33e4 CBZ	X17, 4e3224

  (2575) 0x4e33e8 LDR	X1, [X18, X5]

  (2575) 0x4e33ec ADD	X4, X18, X8

  (2575) 0x4e33f0 LDR	X30, [X18, X8]

  (2575) 0x4e33f4 CMP	X1, X30

  (2575) 0x4e33f8 B.GE	4e3224

  (2575) 0x4e33fc LDR	X28, [SP, #136]

    (2576) 0x4e3400 UBFM	X23, X9, #61, #60

    (2576) 0x4e3404 LDR	X5, [X6, X1,LSL #3]

    (2576) 0x4e3408 LDR	D27, [X7, X1,LSL #3]

    (2576) 0x4e340c LDR	X8, [X11, X5,LSL #3]

    (2576) 0x4e3410 FMUL	D18, D28, D27

    (2576) 0x4e3414 ADD	X15, X26, X8

    (2576) 0x4e3418 UBFM	X3, X15, #61, #60

    (2576) 0x4e341c LDR	X14, [X0, X3]

    (2576) 0x4e3420 UBFM	X5, X14, #61, #60

    (2576) 0x4e3424 CMP	X25, X14

    (2576) 0x4e3428 B.GT	4e3448

    (2576) 0x4e342c LDR	D26, [X28, X5]

    (2576) 0x4e3430 ADD	X1, X1, #1

    (2576) 0x4e3434 FADD	D19, D26, D18

    (2576) 0x4e3438 STR	D19, [X28, X5]

    (2576) 0x4e343c CMP	X1, X30

    (2576) 0x4e3440 B.LT	4e3400

  (2575) 0x4e3444 B	4e3224

    (2576) 0x4e3448 LDR	X30, [SP, #112]

    (2576) 0x4e344c ADD	X1, X1, #1

    (2576) 0x4e3450 STR	X9, [X0, X3]

    (2576) 0x4e3454 ADD	X9, X9, #1

    (2576) 0x4e3458 STR	D18, [X28, X23]

    (2576) 0x4e345c STR	X8, [X30, X23]

    (2576) 0x4e3460 LDR	X30, [X4]

    (2576) 0x4e3464 CMP	X30, X1

    (2576) 0x4e3468 B.GT	4e3400

  (2575) 0x4e346c B	4e3224

    (2572) 0x4e3470 STR	X2, [X0, X7]

    (2572) 0x4e3474 ADD	X1, X1, #1

    (2572) 0x4e3478 ADD	X2, X2, #1

    (2572) 0x4e347c STR	D4, [X19, X8]

    (2572) 0x4e3480 STR	X6, [X24, X8]

    (2572) 0x4e3484 LDR	X30, [X12]

    (2572) 0x4e3488 CMP	X30, X1

    (2572) 0x4e348c B.GT	4e3360

  (2571) 0x4e3490 LDR	X12, [X21, #8]

  (2571) 0x4e3494 ADD	X13, X13, #1

  (2571) 0x4e3498 CMP	X12, X13

  (2571) 0x4e349c B.GT	4e32d0

0x4e34a0 B	4e33ac

    (2573) 0x4e34a4 STR	X9, [X0, X5]

    (2573) 0x4e34a8 ADD	X1, X1, #1

    (2573) 0x4e34ac ADD	X9, X9, #1

    (2573) 0x4e34b0 STR	D2, [X23, X28]

    (2573) 0x4e34b4 STR	X10, [X4, X28]

    (2573) 0x4e34b8 LDR	X11, [X12]

    (2573) 0x4e34bc CMP	X11, X1

    (2573) 0x4e34c0 B.GT	4e3300

  (2571) 0x4e34c4 B	4e3340

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989

--------------------------------------------------------------------------------

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module
►98.11+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.89+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_ParMatmul	par_csr_matop.c:998	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.94
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	hypre_ParMatmul._omp_fn.3
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-874,par_csr_matop.c:886-888,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.83
CQA cycles if no scalar integer	8.83
CQA cycles if FP arith vectorized	8.83
CQA cycles if fully vectorized	3.00
Front-end cycles	6.00
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	3.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	8.83
P11 cycles	8.50
P12 cycles	8.67
P13 cycles	2.50
P14 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	48.00
Nb loads	NA
Nb stores	5.00
Nb stack references	24.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	32.58
Vector-efficiency ratio load	35.94
Vector-efficiency ratio store	40.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.94
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	hypre_ParMatmul._omp_fn.3
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-874,par_csr_matop.c:886-888,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.83
CQA cycles if no scalar integer	8.83
CQA cycles if FP arith vectorized	8.83
CQA cycles if fully vectorized	3.00
Front-end cycles	6.00
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	3.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	8.83
P11 cycles	8.50
P12 cycles	8.67
P13 cycles	2.50
P14 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	48.00
Nb loads	NA
Nb stores	5.00
Nb stack references	24.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	32.58
Vector-efficiency ratio load	35.94
Vector-efficiency ratio store	40.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul._omp_fn.3
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874,886-888,937.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 32% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.83 to 3.00 cycles (2.94x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	49
nb uops	48
loop length	196
used w registers	0
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	8.83	8.50	8.67	2.50	2.50
cycles	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	8.83	8.50	8.67	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	8.83
Overall L1	8.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	32%
load	35%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4e31a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X9, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CBNZ X18, 4e3288 <hypre_ParMatmul._omp_fn.3+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X12, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4e3238 <hypre_ParMatmul._omp_fn.3+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X17, X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X13, X11, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X20, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X25, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X17, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4e34c8 <hypre_ParMatmul._omp_fn.3+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X25, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CBZ X23, 4e3194 <hypre_ParMatmul._omp_fn.3+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X13, X3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X13, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4e31a4 <hypre_ParMatmul._omp_fn.3+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X14, X15, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X28, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X22, X16, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X22, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X21, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X27, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X17, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X6, X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X6, X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X16, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 4e31a4 <hypre_ParMatmul._omp_fn.3+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e33ac <hypre_ParMatmul._omp_fn.3+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParMatmul._omp_fn.3
Source file and lines	par_csr_matop.c:865-989
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	49
nb uops	48
loop length	196
used w registers	0
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	8.83	8.50	8.67	2.50	2.50
cycles	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	8.83	8.50	8.67	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	8.83
Overall L1	8.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	32%
load	35%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4e31a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X9, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CBNZ X18, 4e3288 <hypre_ParMatmul._omp_fn.3+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X12, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4e3238 <hypre_ParMatmul._omp_fn.3+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X17, X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X13, X11, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X20, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X25, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X17, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4e34c8 <hypre_ParMatmul._omp_fn.3+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X25, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CBZ X23, 4e3194 <hypre_ParMatmul._omp_fn.3+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X13, X3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X13, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4e31a4 <hypre_ParMatmul._omp_fn.3+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X14, X15, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X28, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X22, X16, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X22, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X21, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X27, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X17, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X6, X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X6, X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X16, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 4e31a4 <hypre_ParMatmul._omp_fn.3+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e33ac <hypre_ParMatmul._omp_fn.3+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code