OV - exec - Loop 643

	Loop Id: 643	Module: exec	Source: par_multi_interp.c:1072-1125	Coverage: 0.04%

0x455ec0 LDR	X21, [SP, #104]

0x455ec4 LDR	X6, [X21, X9,LSL #3]

0x455ec8 UBFM	X15, X6, #61, #60

0x455ecc ORN	X0, XZR, X6

0x455ed0 ADD	X14, X15, #8

0x455ed4 LDR	X3, [X12, X15]

0x455ed8 ADD	X5, X12, X14

0x455edc LDR	X13, [X12, X14]

0x455ee0 CMP	X3, X13

0x455ee4 B.GE	456248

0x455ee8 ORR	X28, XZR, X24

0x455eec STR	X6, [SP, #128]

0x455ef0 ORR	X6, XZR, X5

0x455ef4 B	455f04

  (646) 0x455ef8 ADD	X3, X3, #1

  (646) 0x455efc CMP	X3, X13

  (646) 0x455f00 B.GE	456240

  (646) 0x455f04 LDR	X24, [X27, X3,LSL #3]

  (646) 0x455f08 UBFM	X1, X24, #61, #60

  (646) 0x455f0c LDR	X16, [X25, X1]

  (646) 0x455f10 CMP	X16, X7

  (646) 0x455f14 B.NE	455ef8

  (646) 0x455f18 LDR	X21, [SP, #152]

  (646) 0x455f1c ADD	X16, X1, #8

  (646) 0x455f20 LDR	X13, [X23, X16]

  (646) 0x455f24 LDR	X5, [X21, X1]

  (646) 0x455f28 ADD	X13, X5, X13

  (646) 0x455f2c CMP	X5, X13

  (646) 0x455f30 B.GE	4560b8

  (646) 0x455f34 LDR	X24, [SP, #160]

  (646) 0x455f38 UBFM	X21, X5, #61, #60

  (646) 0x455f3c STR	X21, [SP, #144]

  (646) 0x455f40 LDUR	X24, [X24, #504]

  (646) 0x455f44 ADD	X13, X24, X13,LSL #3

  (646) 0x455f48 ADD	X5, X24, X5,LSL #3

  (646) 0x455f4c SUB	X21, X13, X5

  (646) 0x455f50 STR	X13, [SP, #96]

  (646) 0x455f54 SUB	X21, X21, #8

  (646) 0x455f58 UBFM	X21, X21, #3, #63

  (646) 0x455f5c ADD	X21, X21, #1

  (646) 0x455f60 ANDS	X21, X21, #0x3

  (646) 0x455f64 B.EQ	456000

  (646) 0x455f68 CMP	X21, #1

  (646) 0x455f6c B.EQ	455fcc

  (646) 0x455f70 CMP	X21, #2

  (646) 0x455f74 B.EQ	455fa4

  (646) 0x455f78 LDR	X13, [SP, #144]

  (646) 0x455f7c LDR	X24, [X24, X13]

  (646) 0x455f80 UBFM	X21, X24, #61, #60

  (646) 0x455f84 LDR	X13, [X20, X21]

  (646) 0x455f88 CMP	X13, X0

  (646) 0x455f8c B.EQ	455fa0

  (646) 0x455f90 LDR	X13, [X10, X22]

  (646) 0x455f94 STR	X24, [X13, X4,LSL #3]

  (646) 0x455f98 ADD	X4, X4, #1

  (646) 0x455f9c STR	X0, [X20, X21]

  (646) 0x455fa0 ADD	X5, X5, #8

  (646) 0x455fa4 LDR	X24, [X5]

  (646) 0x455fa8 UBFM	X21, X24, #61, #60

  (646) 0x455fac LDR	X13, [X20, X21]

  (646) 0x455fb0 CMP	X13, X0

  (646) 0x455fb4 B.EQ	455fc8

  (646) 0x455fb8 LDR	X13, [X10, X22]

  (646) 0x455fbc STR	X24, [X13, X4,LSL #3]

  (646) 0x455fc0 ADD	X4, X4, #1

  (646) 0x455fc4 STR	X0, [X20, X21]

  (646) 0x455fc8 ADD	X5, X5, #8

  (646) 0x455fcc LDR	X24, [X5]

  (646) 0x455fd0 UBFM	X21, X24, #61, #60

  (646) 0x455fd4 LDR	X13, [X20, X21]

  (646) 0x455fd8 CMP	X13, X0

  (646) 0x455fdc B.EQ	455ff0

  (646) 0x455fe0 LDR	X13, [X10, X22]

  (646) 0x455fe4 STR	X24, [X13, X4,LSL #3]

  (646) 0x455fe8 ADD	X4, X4, #1

  (646) 0x455fec STR	X0, [X20, X21]

  (646) 0x455ff0 LDR	X13, [SP, #96]

  (646) 0x455ff4 ADD	X5, X5, #8

  (646) 0x455ff8 CMP	X13, X5

  (646) 0x455ffc B.EQ	4560b8

  (646) 0x456000 ORR	X24, XZR, X2

  (646) 0x456004 STR	X1, [SP, #96]

  (646) 0x456008 STR	X19, [SP, #144]

    (648) 0x45600c LDR	X21, [X5]

    (648) 0x456010 ADD	X2, X5, #8

    (648) 0x456014 UBFM	X19, X21, #61, #60

    (648) 0x456018 LDR	X1, [X20, X19]

    (648) 0x45601c CMP	X1, X0

    (648) 0x456020 B.EQ	456034

    (648) 0x456024 LDR	X1, [X10, X22]

    (648) 0x456028 STR	X21, [X1, X4,LSL #3]

    (648) 0x45602c ADD	X4, X4, #1

    (648) 0x456030 STR	X0, [X20, X19]

    (648) 0x456034 LDR	X19, [X5, #8]

    (648) 0x456038 UBFM	X5, X19, #61, #60

    (648) 0x45603c LDR	X21, [X20, X5]

    (648) 0x456040 CMP	X21, X0

    (648) 0x456044 B.EQ	456058

    (648) 0x456048 LDR	X1, [X10, X22]

    (648) 0x45604c STR	X19, [X1, X4,LSL #3]

    (648) 0x456050 ADD	X4, X4, #1

    (648) 0x456054 STR	X0, [X20, X5]

    (648) 0x456058 LDR	X21, [X2, #8]

    (648) 0x45605c ADD	X5, X2, #24

    (648) 0x456060 UBFM	X19, X21, #61, #60

    (648) 0x456064 LDR	X1, [X20, X19]

    (648) 0x456068 CMP	X1, X0

    (648) 0x45606c B.EQ	456080

    (648) 0x456070 LDR	X1, [X10, X22]

    (648) 0x456074 STR	X21, [X1, X4,LSL #3]

    (648) 0x456078 ADD	X4, X4, #1

    (648) 0x45607c STR	X0, [X20, X19]

    (648) 0x456080 LDR	X19, [X2, #16]

    (648) 0x456084 UBFM	X2, X19, #61, #60

    (648) 0x456088 LDR	X21, [X20, X2]

    (648) 0x45608c CMP	X21, X0

    (648) 0x456090 B.EQ	4560a4

    (648) 0x456094 LDR	X1, [X10, X22]

    (648) 0x456098 STR	X19, [X1, X4,LSL #3]

    (648) 0x45609c ADD	X4, X4, #1

    (648) 0x4560a0 STR	X0, [X20, X2]

    (648) 0x4560a4 CMP	X13, X5

    (648) 0x4560a8 B.NE	45600c

  (646) 0x4560ac LDR	X1, [SP, #96]

  (646) 0x4560b0 ORR	X2, XZR, X24

  (646) 0x4560b4 LDR	X19, [SP, #144]

  (646) 0x4560b8 LDR	X13, [SP, #136]

  (646) 0x4560bc LDR	X16, [X18, X16]

  (646) 0x4560c0 LDR	X24, [X13, X1]

  (646) 0x4560c4 ADD	X5, X24, X16

  (646) 0x4560c8 CMP	X24, X5

  (646) 0x4560cc B.GE	45622c

  (646) 0x4560d0 LDR	X1, [SP, #168]

  (646) 0x4560d4 UBFM	X21, X24, #61, #60

  (646) 0x4560d8 LDUR	X16, [X1, #504]

  (646) 0x4560dc ADD	X1, X16, X24,LSL #3

  (646) 0x4560e0 ADD	X5, X16, X5,LSL #3

  (646) 0x4560e4 SUB	X13, X5, X1

  (646) 0x4560e8 SUB	X24, X13, #8

  (646) 0x4560ec UBFM	X13, X24, #3, #63

  (646) 0x4560f0 ADD	X24, X13, #1

  (646) 0x4560f4 ANDS	X13, X24, #0x3

  (646) 0x4560f8 B.EQ	45618c

  (646) 0x4560fc CMP	X13, #1

  (646) 0x456100 B.EQ	45615c

  (646) 0x456104 CMP	X13, #2

  (646) 0x456108 B.EQ	456134

  (646) 0x45610c LDR	X16, [X16, X21]

  (646) 0x456110 UBFM	X24, X16, #61, #60

  (646) 0x456114 LDR	X21, [X19, X24]

  (646) 0x456118 CMP	X21, X0

  (646) 0x45611c B.EQ	456130

  (646) 0x456120 LDR	X13, [X8, X22]

  (646) 0x456124 STR	X16, [X13, X2,LSL #3]

  (646) 0x456128 ADD	X2, X2, #1

  (646) 0x45612c STR	X0, [X19, X24]

  (646) 0x456130 ADD	X1, X1, #8

  (646) 0x456134 LDR	X16, [X1]

  (646) 0x456138 UBFM	X24, X16, #61, #60

  (646) 0x45613c LDR	X21, [X19, X24]

  (646) 0x456140 CMP	X21, X0

  (646) 0x456144 B.EQ	456158

  (646) 0x456148 LDR	X13, [X8, X22]

  (646) 0x45614c STR	X16, [X13, X2,LSL #3]

  (646) 0x456150 ADD	X2, X2, #1

  (646) 0x456154 STR	X0, [X19, X24]

  (646) 0x456158 ADD	X1, X1, #8

  (646) 0x45615c LDR	X16, [X1]

  (646) 0x456160 UBFM	X24, X16, #61, #60

  (646) 0x456164 LDR	X21, [X19, X24]

  (646) 0x456168 CMP	X21, X0

  (646) 0x45616c B.EQ	456180

  (646) 0x456170 LDR	X13, [X8, X22]

  (646) 0x456174 STR	X16, [X13, X2,LSL #3]

  (646) 0x456178 ADD	X2, X2, #1

  (646) 0x45617c STR	X0, [X19, X24]

  (646) 0x456180 ADD	X1, X1, #8

  (646) 0x456184 CMP	X1, X5

  (646) 0x456188 B.EQ	45622c

    (647) 0x45618c LDR	X21, [X1]

    (647) 0x456190 ADD	X13, X1, #8

    (647) 0x456194 UBFM	X16, X21, #61, #60

    (647) 0x456198 LDR	X24, [X19, X16]

    (647) 0x45619c CMP	X24, X0

    (647) 0x4561a0 B.EQ	4561b4

    (647) 0x4561a4 LDR	X24, [X8, X22]

    (647) 0x4561a8 STR	X21, [X24, X2,LSL #3]

    (647) 0x4561ac ADD	X2, X2, #1

    (647) 0x4561b0 STR	X0, [X19, X16]

    (647) 0x4561b4 LDR	X16, [X1, #8]

    (647) 0x4561b8 UBFM	X1, X16, #61, #60

    (647) 0x4561bc LDR	X21, [X19, X1]

    (647) 0x4561c0 CMP	X21, X0

    (647) 0x4561c4 B.EQ	4561d8

    (647) 0x4561c8 LDR	X24, [X8, X22]

    (647) 0x4561cc STR	X16, [X24, X2,LSL #3]

    (647) 0x4561d0 ADD	X2, X2, #1

    (647) 0x4561d4 STR	X0, [X19, X1]

    (647) 0x4561d8 LDR	X21, [X13, #8]

    (647) 0x4561dc ADD	X1, X13, #24

    (647) 0x4561e0 UBFM	X16, X21, #61, #60

    (647) 0x4561e4 LDR	X24, [X19, X16]

    (647) 0x4561e8 CMP	X24, X0

    (647) 0x4561ec B.EQ	456200

    (647) 0x4561f0 LDR	X24, [X8, X22]

    (647) 0x4561f4 STR	X21, [X24, X2,LSL #3]

    (647) 0x4561f8 ADD	X2, X2, #1

    (647) 0x4561fc STR	X0, [X19, X16]

    (647) 0x456200 LDR	X16, [X13, #16]

    (647) 0x456204 UBFM	X13, X16, #61, #60

    (647) 0x456208 LDR	X21, [X19, X13]

    (647) 0x45620c CMP	X21, X0

    (647) 0x456210 B.EQ	456224

    (647) 0x456214 LDR	X24, [X8, X22]

    (647) 0x456218 STR	X16, [X24, X2,LSL #3]

    (647) 0x45621c ADD	X2, X2, #1

    (647) 0x456220 STR	X0, [X19, X13]

    (647) 0x456224 CMP	X1, X5

    (647) 0x456228 B.NE	45618c

  (646) 0x45622c LDR	X13, [X6]

  (646) 0x456230 ADD	X3, X3, #1

  (646) 0x456234 CMP	X3, X13

  (646) 0x456238 B.LT	455f04

0x45623c HINT	#0

0x456240 LDR	X6, [SP, #128]

0x456244 ORR	X24, XZR, X28

0x456248 ORN	X6, XZR, X6

0x45624c LDR	X1, [X11, X15]

0x456250 ADD	X15, X11, X14

0x456254 LDR	X3, [X11, X14]

0x456258 CMP	X3, X1

0x45625c B.LE	456380

0x456260 LDP	X21, X28, [SP, #112]

0x456264 B	456274

  (644) 0x456268 ADD	X1, X1, #1

  (644) 0x45626c CMP	X1, X3

  (644) 0x456270 B.GE	456380

  (644) 0x456274 LDR	X0, [X26, X1,LSL #3]

  (644) 0x456278 UBFM	X14, X0, #61, #60

  (644) 0x45627c LDR	X5, [X24, X14]

  (644) 0x456280 CMP	X5, X7

  (644) 0x456284 B.NE	456268

  (644) 0x456288 ADD	X16, X21, X14

  (644) 0x45628c LDR	X0, [X17, X14]

  (644) 0x456290 LDR	X13, [X16, #8]

  (644) 0x456294 ADD	X5, X0, X13

  (644) 0x456298 CMP	X0, X5

  (644) 0x45629c B.GE	456268

  (644) 0x4562a0 LDR	X16, [X28, X22]

  (644) 0x4562a4 UBFM	X14, X0, #61, #60

  (644) 0x4562a8 ADD	X5, X16, X5,LSL #3

  (644) 0x4562ac ADD	X0, X16, X0,LSL #3

  (644) 0x4562b0 SUB	X3, X5, X0

  (644) 0x4562b4 SUB	X13, X3, #8

  (644) 0x4562b8 UBFM	X3, X13, #3, #63

  (644) 0x4562bc ADD	X13, X3, #1

  (644) 0x4562c0 ANDS	X3, X13, #0x3

  (644) 0x4562c4 B.EQ	456448

  (644) 0x4562c8 CMP	X3, #1

  (644) 0x4562cc B.EQ	456330

  (644) 0x4562d0 CMP	X3, #2

  (644) 0x4562d4 B.EQ	456304

  (644) 0x4562d8 LDR	X16, [X16, X14]

  (644) 0x4562dc TBNZ	X16, #63, 45658c

  (644) 0x4562e0 UBFM	X13, X16, #61, #60

  (644) 0x4562e4 LDR	X14, [X19, X13]

  (644) 0x4562e8 CMP	X14, X6

  (644) 0x4562ec B.EQ	456300

  (644) 0x4562f0 LDR	X3, [X8, X22]

  (644) 0x4562f4 STR	X16, [X3, X2,LSL #3]

  (644) 0x4562f8 ADD	X2, X2, #1

  (644) 0x4562fc STR	X6, [X19, X13]

  (644) 0x456300 ADD	X0, X0, #8

  (644) 0x456304 LDR	X3, [X0]

  (644) 0x456308 TBNZ	X3, #63, 456560

  (644) 0x45630c UBFM	X13, X3, #61, #60

  (644) 0x456310 LDR	X14, [X19, X13]

  (644) 0x456314 CMP	X14, X6

  (644) 0x456318 B.EQ	45632c

  (644) 0x45631c LDR	X16, [X8, X22]

  (644) 0x456320 STR	X3, [X16, X2,LSL #3]

  (644) 0x456324 ADD	X2, X2, #1

  (644) 0x456328 STR	X6, [X19, X13]

  (644) 0x45632c ADD	X0, X0, #8

  (644) 0x456330 LDR	X16, [X0]

  (644) 0x456334 TBNZ	X16, #63, 456534

  (644) 0x456338 UBFM	X13, X16, #61, #60

  (644) 0x45633c LDR	X14, [X19, X13]

  (644) 0x456340 CMP	X14, X6

  (644) 0x456344 B.EQ	456358

  (644) 0x456348 LDR	X3, [X8, X22]

  (644) 0x45634c STR	X16, [X3, X2,LSL #3]

  (644) 0x456350 ADD	X2, X2, #1

  (644) 0x456354 STR	X6, [X19, X13]

  (644) 0x456358 ADD	X0, X0, #8

  (644) 0x45635c CMP	X0, X5

  (644) 0x456360 B.NE	456448

  (644) 0x456364 LDR	X3, [X15]

  (644) 0x456368 ADD	X1, X1, #1

  (644) 0x45636c CMP	X1, X3

  (644) 0x456370 B.LT	456274

0x456374 HINT	#0

0x456378 HINT	#0

0x45637c HINT	#0

0x456380 ADD	X9, X9, #1

0x456384 CMP	X30, X9

0x456388 B.GT	455ec0

    (645) 0x4563cc UBFM	X13, X16, #61, #60

    (645) 0x4563d0 LDR	X14, [X19, X13]

    (645) 0x4563d4 CMP	X14, X6

    (645) 0x4563d8 B.EQ	4563ec

    (645) 0x4563dc LDR	X3, [X8, X22]

    (645) 0x4563e0 STR	X16, [X3, X2,LSL #3]

    (645) 0x4563e4 ADD	X2, X2, #1

    (645) 0x4563e8 STR	X6, [X19, X13]

    (645) 0x4563ec LDR	X3, [X0, #8]

    (645) 0x4563f0 TBNZ	X3, #63, 4564ac

    (645) 0x4563f4 UBFM	X13, X3, #61, #60

    (645) 0x4563f8 LDR	X14, [X19, X13]

    (645) 0x4563fc CMP	X14, X6

    (645) 0x456400 B.EQ	456414

    (645) 0x456404 LDR	X16, [X8, X22]

    (645) 0x456408 STR	X3, [X16, X2,LSL #3]

    (645) 0x45640c ADD	X2, X2, #1

    (645) 0x456410 STR	X6, [X19, X13]

    (645) 0x456414 LDR	X16, [X0, #16]

    (645) 0x456418 TBNZ	X16, #63, 4564dc

    (645) 0x45641c UBFM	X13, X16, #61, #60

    (645) 0x456420 LDR	X14, [X19, X13]

    (645) 0x456424 CMP	X14, X6

    (645) 0x456428 B.EQ	45643c

    (645) 0x45642c LDR	X3, [X8, X22]

    (645) 0x456430 STR	X16, [X3, X2,LSL #3]

    (645) 0x456434 ADD	X2, X2, #1

    (645) 0x456438 STR	X6, [X19, X13]

    (645) 0x45643c ADD	X0, X0, #24

    (645) 0x456440 CMP	X0, X5

    (645) 0x456444 B.EQ	456364

    (645) 0x456448 LDR	X3, [X0]

    (645) 0x45644c TBNZ	X3, #63, 456508

    (645) 0x456450 UBFM	X13, X3, #61, #60

    (645) 0x456454 LDR	X14, [X19, X13]

    (645) 0x456458 CMP	X14, X6

    (645) 0x45645c B.EQ	456470

    (645) 0x456460 LDR	X16, [X8, X22]

    (645) 0x456464 STR	X3, [X16, X2,LSL #3]

    (645) 0x456468 ADD	X2, X2, #1

    (645) 0x45646c STR	X6, [X19, X13]

    (645) 0x456470 LDR	X16, [X0, #8]

    (645) 0x456474 ADD	X0, X0, #8

    (645) 0x456478 TBZ	X16, #63, 4563cc

    (645) 0x45647c ORN	X13, XZR, X16

    (645) 0x456480 UBFM	X13, X13, #61, #60

    (645) 0x456484 LDR	X14, [X20, X13]

    (645) 0x456488 CMP	X14, X6

    (645) 0x45648c B.EQ	4563ec

    (645) 0x456490 LDR	X14, [X10, X22]

    (645) 0x456494 ORN	X16, XZR, X16

    (645) 0x456498 STR	X16, [X14, X4,LSL #3]

    (645) 0x45649c ADD	X4, X4, #1

    (645) 0x4564a0 STR	X6, [X20, X13]

    (645) 0x4564a4 LDR	X3, [X0, #8]

    (645) 0x4564a8 TBZ	X3, #63, 4563f4

    (645) 0x4564ac ORN	X13, XZR, X3

    (645) 0x4564b0 UBFM	X16, X13, #61, #60

    (645) 0x4564b4 LDR	X14, [X20, X16]

    (645) 0x4564b8 CMP	X14, X6

    (645) 0x4564bc B.EQ	456414

    (645) 0x4564c0 LDR	X13, [X10, X22]

    (645) 0x4564c4 ORN	X3, XZR, X3

    (645) 0x4564c8 STR	X3, [X13, X4,LSL #3]

    (645) 0x4564cc ADD	X4, X4, #1

    (645) 0x4564d0 STR	X6, [X20, X16]

    (645) 0x4564d4 LDR	X16, [X0, #16]

    (645) 0x4564d8 TBZ	X16, #63, 45641c

    (645) 0x4564dc ORN	X13, XZR, X16

    (645) 0x4564e0 UBFM	X13, X13, #61, #60

    (645) 0x4564e4 LDR	X14, [X20, X13]

    (645) 0x4564e8 CMP	X14, X6

    (645) 0x4564ec B.EQ	45643c

    (645) 0x4564f0 LDR	X14, [X10, X22]

    (645) 0x4564f4 ORN	X16, XZR, X16

    (645) 0x4564f8 STR	X16, [X14, X4,LSL #3]

    (645) 0x4564fc ADD	X4, X4, #1

    (645) 0x456500 STR	X6, [X20, X13]

    (645) 0x456504 B	45643c

    (645) 0x456508 ORN	X13, XZR, X3

    (645) 0x45650c UBFM	X16, X13, #61, #60

    (645) 0x456510 LDR	X14, [X20, X16]

    (645) 0x456514 CMP	X14, X6

    (645) 0x456518 B.EQ	456470

    (645) 0x45651c LDR	X13, [X10, X22]

    (645) 0x456520 ORN	X3, XZR, X3

    (645) 0x456524 STR	X3, [X13, X4,LSL #3]

    (645) 0x456528 ADD	X4, X4, #1

    (645) 0x45652c STR	X6, [X20, X16]

    (645) 0x456530 B	456470

  (644) 0x456534 ORN	X13, XZR, X16

  (644) 0x456538 UBFM	X13, X13, #61, #60

  (644) 0x45653c LDR	X14, [X20, X13]

  (644) 0x456540 CMP	X14, X6

  (644) 0x456544 B.EQ	456358

  (644) 0x456548 LDR	X14, [X10, X22]

  (644) 0x45654c ORN	X16, XZR, X16

  (644) 0x456550 STR	X16, [X14, X4,LSL #3]

  (644) 0x456554 ADD	X4, X4, #1

  (644) 0x456558 STR	X6, [X20, X13]

  (644) 0x45655c B	456358

  (644) 0x456560 ORN	X13, XZR, X3

  (644) 0x456564 UBFM	X16, X13, #61, #60

  (644) 0x456568 LDR	X14, [X20, X16]

  (644) 0x45656c CMP	X14, X6

  (644) 0x456570 B.EQ	45632c

  (644) 0x456574 LDR	X13, [X10, X22]

  (644) 0x456578 ORN	X3, XZR, X3

  (644) 0x45657c STR	X3, [X13, X4,LSL #3]

  (644) 0x456580 ADD	X4, X4, #1

  (644) 0x456584 STR	X6, [X20, X16]

  (644) 0x456588 B	45632c

  (644) 0x45658c ORN	X13, XZR, X16

  (644) 0x456590 UBFM	X13, X13, #61, #60

  (644) 0x456594 LDR	X14, [X20, X13]

  (644) 0x456598 CMP	X14, X6

  (644) 0x45659c B.EQ	456300

  (644) 0x4565a0 LDR	X14, [X10, X22]

  (644) 0x4565a4 ORN	X16, XZR, X16

  (644) 0x4565a8 STR	X16, [X14, X4,LSL #3]

  (644) 0x4565ac ADD	X4, X4, #1

  (644) 0x4565b0 STR	X6, [X20, X13]

  (644) 0x4565b4 B	456300

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1072 - 1125

--------------------------------------------------------------------------------

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
►98.73+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.27+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.38
CQA cycles if no scalar integer	3.38
CQA cycles if FP arith vectorized	3.38
CQA cycles if fully vectorized	0.84
Front-end cycles	3.38
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	3.25
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.17
P11 cycles	2.83
P12 cycles	3.00
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	27.00
Nb loads	NA
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.38
CQA cycles if no scalar integer	3.38
CQA cycles if FP arith vectorized	3.38
CQA cycles if fully vectorized	0.84
Front-end cycles	3.38
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	3.25
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.17
P11 cycles	2.83
P12 cycles	3.00
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	27.00
Nb loads	NA
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1125.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1104,1122.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.38 to 0.84 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	31
nb uops	27
loop length	124
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50
cycles	2.50	2.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	3.25
Overall L1	3.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.38 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 455ec0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X15, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN X0, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [X12, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X5, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X13, [X12, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456248 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x103c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X6, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 455f04 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X24, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORN X6, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [X11, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [X11, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 456380 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 456274 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1068>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 455ec0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.38 to 0.84 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	31
nb uops	27
loop length	124
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50
cycles	2.50	2.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	3.25
Overall L1	3.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.38 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 455ec0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X15, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN X0, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [X12, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X5, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X13, [X12, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456248 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x103c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X6, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 455f04 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X24, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORN X6, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [X11, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [X11, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 456380 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 456274 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1068>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 455ec0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code