OV - exec - Loop 646

	Loop Id: 646	Module: exec	Source: par_multi_interp.c:1075-1099	Coverage: 0.55%

0x455ef8 ADD	X3, X3, #1

0x455efc CMP	X3, X13

0x455f00 B.GE	456240

0x455f04 LDR	X24, [X27, X3,LSL #3]

0x455f08 UBFM	X1, X24, #61, #60

0x455f0c LDR	X16, [X25, X1]

0x455f10 CMP	X16, X7

0x455f14 B.NE	455ef8

0x455f18 LDR	X21, [SP, #152]

0x455f1c ADD	X16, X1, #8

0x455f20 LDR	X13, [X23, X16]

0x455f24 LDR	X5, [X21, X1]

0x455f28 ADD	X13, X5, X13

0x455f2c CMP	X5, X13

0x455f30 B.GE	4560b8

0x455f34 LDR	X24, [SP, #160]

0x455f38 UBFM	X21, X5, #61, #60

0x455f3c STR	X21, [SP, #144]

0x455f40 LDUR	X24, [X24, #504]

0x455f44 ADD	X13, X24, X13,LSL #3

0x455f48 ADD	X5, X24, X5,LSL #3

0x455f4c SUB	X21, X13, X5

0x455f50 STR	X13, [SP, #96]

0x455f54 SUB	X21, X21, #8

0x455f58 UBFM	X21, X21, #3, #63

0x455f5c ADD	X21, X21, #1

0x455f60 ANDS	X21, X21, #0x3

0x455f64 B.EQ	456000

0x455f68 CMP	X21, #1

0x455f6c B.EQ	455fcc

0x455f70 CMP	X21, #2

0x455f74 B.EQ	455fa4

0x455f78 LDR	X13, [SP, #144]

0x455f7c LDR	X24, [X24, X13]

0x455f80 UBFM	X21, X24, #61, #60

0x455f84 LDR	X13, [X20, X21]

0x455f88 CMP	X13, X0

0x455f8c B.EQ	455fa0

0x455f90 LDR	X13, [X10, X22]

0x455f94 STR	X24, [X13, X4,LSL #3]

0x455f98 ADD	X4, X4, #1

0x455f9c STR	X0, [X20, X21]

0x455fa0 ADD	X5, X5, #8

0x455fa4 LDR	X24, [X5]

0x455fa8 UBFM	X21, X24, #61, #60

0x455fac LDR	X13, [X20, X21]

0x455fb0 CMP	X13, X0

0x455fb4 B.EQ	455fc8

0x455fb8 LDR	X13, [X10, X22]

0x455fbc STR	X24, [X13, X4,LSL #3]

0x455fc0 ADD	X4, X4, #1

0x455fc4 STR	X0, [X20, X21]

0x455fc8 ADD	X5, X5, #8

0x455fcc LDR	X24, [X5]

0x455fd0 UBFM	X21, X24, #61, #60

0x455fd4 LDR	X13, [X20, X21]

0x455fd8 CMP	X13, X0

0x455fdc B.EQ	455ff0

0x455fe0 LDR	X13, [X10, X22]

0x455fe4 STR	X24, [X13, X4,LSL #3]

0x455fe8 ADD	X4, X4, #1

0x455fec STR	X0, [X20, X21]

0x455ff0 LDR	X13, [SP, #96]

0x455ff4 ADD	X5, X5, #8

0x455ff8 CMP	X13, X5

0x455ffc B.EQ	4560b8

0x456000 ORR	X24, XZR, X2

0x456004 STR	X1, [SP, #96]

0x456008 STR	X19, [SP, #144]

  (648) 0x45600c LDR	X21, [X5]

  (648) 0x456010 ADD	X2, X5, #8

  (648) 0x456014 UBFM	X19, X21, #61, #60

  (648) 0x456018 LDR	X1, [X20, X19]

  (648) 0x45601c CMP	X1, X0

  (648) 0x456020 B.EQ	456034

  (648) 0x456024 LDR	X1, [X10, X22]

  (648) 0x456028 STR	X21, [X1, X4,LSL #3]

  (648) 0x45602c ADD	X4, X4, #1

  (648) 0x456030 STR	X0, [X20, X19]

  (648) 0x456034 LDR	X19, [X5, #8]

  (648) 0x456038 UBFM	X5, X19, #61, #60

  (648) 0x45603c LDR	X21, [X20, X5]

  (648) 0x456040 CMP	X21, X0

  (648) 0x456044 B.EQ	456058

  (648) 0x456048 LDR	X1, [X10, X22]

  (648) 0x45604c STR	X19, [X1, X4,LSL #3]

  (648) 0x456050 ADD	X4, X4, #1

  (648) 0x456054 STR	X0, [X20, X5]

  (648) 0x456058 LDR	X21, [X2, #8]

  (648) 0x45605c ADD	X5, X2, #24

  (648) 0x456060 UBFM	X19, X21, #61, #60

  (648) 0x456064 LDR	X1, [X20, X19]

  (648) 0x456068 CMP	X1, X0

  (648) 0x45606c B.EQ	456080

  (648) 0x456070 LDR	X1, [X10, X22]

  (648) 0x456074 STR	X21, [X1, X4,LSL #3]

  (648) 0x456078 ADD	X4, X4, #1

  (648) 0x45607c STR	X0, [X20, X19]

  (648) 0x456080 LDR	X19, [X2, #16]

  (648) 0x456084 UBFM	X2, X19, #61, #60

  (648) 0x456088 LDR	X21, [X20, X2]

  (648) 0x45608c CMP	X21, X0

  (648) 0x456090 B.EQ	4560a4

  (648) 0x456094 LDR	X1, [X10, X22]

  (648) 0x456098 STR	X19, [X1, X4,LSL #3]

  (648) 0x45609c ADD	X4, X4, #1

  (648) 0x4560a0 STR	X0, [X20, X2]

  (648) 0x4560a4 CMP	X13, X5

  (648) 0x4560a8 B.NE	45600c

0x4560ac LDR	X1, [SP, #96]

0x4560b0 ORR	X2, XZR, X24

0x4560b4 LDR	X19, [SP, #144]

0x4560b8 LDR	X13, [SP, #136]

0x4560bc LDR	X16, [X18, X16]

0x4560c0 LDR	X24, [X13, X1]

0x4560c4 ADD	X5, X24, X16

0x4560c8 CMP	X24, X5

0x4560cc B.GE	45622c

0x4560d0 LDR	X1, [SP, #168]

0x4560d4 UBFM	X21, X24, #61, #60

0x4560d8 LDUR	X16, [X1, #504]

0x4560dc ADD	X1, X16, X24,LSL #3

0x4560e0 ADD	X5, X16, X5,LSL #3

0x4560e4 SUB	X13, X5, X1

0x4560e8 SUB	X24, X13, #8

0x4560ec UBFM	X13, X24, #3, #63

0x4560f0 ADD	X24, X13, #1

0x4560f4 ANDS	X13, X24, #0x3

0x4560f8 B.EQ	45618c

0x4560fc CMP	X13, #1

0x456100 B.EQ	45615c

0x456104 CMP	X13, #2

0x456108 B.EQ	456134

0x45610c LDR	X16, [X16, X21]

0x456110 UBFM	X24, X16, #61, #60

0x456114 LDR	X21, [X19, X24]

0x456118 CMP	X21, X0

0x45611c B.EQ	456130

0x456120 LDR	X13, [X8, X22]

0x456124 STR	X16, [X13, X2,LSL #3]

0x456128 ADD	X2, X2, #1

0x45612c STR	X0, [X19, X24]

0x456130 ADD	X1, X1, #8

0x456134 LDR	X16, [X1]

0x456138 UBFM	X24, X16, #61, #60

0x45613c LDR	X21, [X19, X24]

0x456140 CMP	X21, X0

0x456144 B.EQ	456158

0x456148 LDR	X13, [X8, X22]

0x45614c STR	X16, [X13, X2,LSL #3]

0x456150 ADD	X2, X2, #1

0x456154 STR	X0, [X19, X24]

0x456158 ADD	X1, X1, #8

0x45615c LDR	X16, [X1]

0x456160 UBFM	X24, X16, #61, #60

0x456164 LDR	X21, [X19, X24]

0x456168 CMP	X21, X0

0x45616c B.EQ	456180

0x456170 LDR	X13, [X8, X22]

0x456174 STR	X16, [X13, X2,LSL #3]

0x456178 ADD	X2, X2, #1

0x45617c STR	X0, [X19, X24]

0x456180 ADD	X1, X1, #8

0x456184 CMP	X1, X5

0x456188 B.EQ	45622c

  (647) 0x45618c LDR	X21, [X1]

  (647) 0x456190 ADD	X13, X1, #8

  (647) 0x456194 UBFM	X16, X21, #61, #60

  (647) 0x456198 LDR	X24, [X19, X16]

  (647) 0x45619c CMP	X24, X0

  (647) 0x4561a0 B.EQ	4561b4

  (647) 0x4561a4 LDR	X24, [X8, X22]

  (647) 0x4561a8 STR	X21, [X24, X2,LSL #3]

  (647) 0x4561ac ADD	X2, X2, #1

  (647) 0x4561b0 STR	X0, [X19, X16]

  (647) 0x4561b4 LDR	X16, [X1, #8]

  (647) 0x4561b8 UBFM	X1, X16, #61, #60

  (647) 0x4561bc LDR	X21, [X19, X1]

  (647) 0x4561c0 CMP	X21, X0

  (647) 0x4561c4 B.EQ	4561d8

  (647) 0x4561c8 LDR	X24, [X8, X22]

  (647) 0x4561cc STR	X16, [X24, X2,LSL #3]

  (647) 0x4561d0 ADD	X2, X2, #1

  (647) 0x4561d4 STR	X0, [X19, X1]

  (647) 0x4561d8 LDR	X21, [X13, #8]

  (647) 0x4561dc ADD	X1, X13, #24

  (647) 0x4561e0 UBFM	X16, X21, #61, #60

  (647) 0x4561e4 LDR	X24, [X19, X16]

  (647) 0x4561e8 CMP	X24, X0

  (647) 0x4561ec B.EQ	456200

  (647) 0x4561f0 LDR	X24, [X8, X22]

  (647) 0x4561f4 STR	X21, [X24, X2,LSL #3]

  (647) 0x4561f8 ADD	X2, X2, #1

  (647) 0x4561fc STR	X0, [X19, X16]

  (647) 0x456200 LDR	X16, [X13, #16]

  (647) 0x456204 UBFM	X13, X16, #61, #60

  (647) 0x456208 LDR	X21, [X19, X13]

  (647) 0x45620c CMP	X21, X0

  (647) 0x456210 B.EQ	456224

  (647) 0x456214 LDR	X24, [X8, X22]

  (647) 0x456218 STR	X16, [X24, X2,LSL #3]

  (647) 0x45621c ADD	X2, X2, #1

  (647) 0x456220 STR	X0, [X19, X13]

  (647) 0x456224 CMP	X1, X5

  (647) 0x456228 B.NE	45618c

0x45622c LDR	X13, [X6]

0x456230 ADD	X3, X3, #1

0x456234 CMP	X3, X13

0x456238 B.LT	455f04

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1075 - 1099

--------------------------------------------------------------------------------

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
►98.44+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.56+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1075-1075,par_multi_interp.c:1078-1088,par_multi_interp.c:1091-1099
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	4.25
Front-end cycles	16.13
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	14.75
P3 cycles	14.75
P4 cycles	14.75
P5 cycles	14.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	17.00
P11 cycles	17.00
P12 cycles	17.00
P13 cycles	8.00
P14 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	129.00
Nb loads	NA
Nb stores	16.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1075-1075,par_multi_interp.c:1078-1088,par_multi_interp.c:1091-1099
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	4.25
Front-end cycles	16.13
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	14.75
P3 cycles	14.75
P4 cycles	14.75
P5 cycles	14.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	17.00
P11 cycles	17.00
P12 cycles	17.00
P13 cycles	8.00
P14 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	129.00
Nb loads	NA
Nb stores	16.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1075-1099
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075-1099.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075,1078-1088,1091-1099.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 65026 paths individually, rerun with max-paths=65026
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 65026 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 17.00 to 4.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	129
nb uops	129
loop length	516
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.13 cycles
front end	16.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.50	9.50	14.75	14.75	14.75	14.75	0.00	0.00	0.00	0.00	17.00	17.00	17.00	8.00	8.00
cycles	9.50	9.50	14.75	14.75	14.75	14.75	0.00	0.00	0.00	0.00	17.00	17.00	17.00	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.13
Dispatch	17.00
Overall L1	17.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 455f04

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456240 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1034>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X27, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X25, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 455ef8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X23, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4560b8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X24, [X24, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X24, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X5, X24, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X21, X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X21, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X21, X21, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X21, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X21, X21, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 456000 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455fcc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455fa4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X24, X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455fa0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455fc8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455ff0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xde4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4560b8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X19, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X19, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X18, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X13, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X24, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X24, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45622c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDUR X16, [X1, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X16, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X5, X16, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X13, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X24, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X13, X24, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X24, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X13, X24, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 45618c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45615c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456134 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X16, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456130 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456158 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456180 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45622c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 455f04 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1075-1099
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 65026 paths individually, rerun with max-paths=65026
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	129
nb uops	129
loop length	516
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.13 cycles
front end	16.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.50	9.50	14.75	14.75	14.75	14.75	0.00	0.00	0.00	0.00	17.00	17.00	17.00	8.00	8.00
cycles	9.50	9.50	14.75	14.75	14.75	14.75	0.00	0.00	0.00	0.00	17.00	17.00	17.00	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.13
Dispatch	17.00
Overall L1	17.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 455f04

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456240 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1034>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X27, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X25, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 455ef8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X23, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4560b8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X24, [X24, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X24, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X5, X24, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X21, X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X21, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X21, X21, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X21, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X21, X21, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 456000 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455fcc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455fa4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X24, X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455fa0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455fc8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455ff0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xde4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4560b8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X19, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X19, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X18, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X13, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X24, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X24, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45622c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDUR X16, [X1, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X16, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X5, X16, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X13, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X24, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X13, X24, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X24, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X13, X24, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 45618c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45615c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456134 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X16, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456130 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456158 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456180 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45622c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 455f04 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code