OV - exec - Loop 651

	Loop Id: 651	Module: exec	Source: par_multi_interp.c:939-999 [...]	Coverage: 0.04%

0x4553e0 LDR	X14, [SP, #104]

0x4553e4 LDR	X0, [X14, X15,LSL #3]

0x4553e8 UBFM	X10, X0, #61, #60

0x4553ec ADD	X1, X10, #8

0x4553f0 STR	X6, [X18, X10]

0x4553f4 ADD	X4, X12, X1

0x4553f8 STR	X5, [X16, X10]

0x4553fc LDR	X3, [X12, X10]

0x455400 LDR	X8, [X12, X1]

0x455404 CMP	X3, X8

0x455408 B.GE	455774

0x45540c ORR	X28, XZR, X24

0x455410 STR	X9, [SP, #128]

0x455414 ORR	X9, XZR, X4

0x455418 B	455428

  (654) 0x45541c ADD	X3, X3, #1

  (654) 0x455420 CMP	X3, X8

  (654) 0x455424 B.GE	45576c

  (654) 0x455428 LDR	X24, [X27, X3,LSL #3]

  (654) 0x45542c UBFM	X2, X24, #61, #60

  (654) 0x455430 LDR	X17, [X25, X2]

  (654) 0x455434 STR	X2, [SP, #96]

  (654) 0x455438 CMP	X17, X7

  (654) 0x45543c B.NE	45541c

  (654) 0x455440 ADD	X17, X2, #8

  (654) 0x455444 LDR	X8, [X18, X2]

  (654) 0x455448 LDR	X14, [X23, X17]

  (654) 0x45544c ADD	X4, X8, X14

  (654) 0x455450 CMP	X8, X4

  (654) 0x455454 B.GE	4555d0

  (654) 0x455458 LDR	X24, [SP, #144]

  (654) 0x45545c UBFM	X2, X8, #61, #60

  (654) 0x455460 LDUR	X24, [X24, #504]

  (654) 0x455464 ADD	X14, X24, X4,LSL #3

  (654) 0x455468 ADD	X4, X24, X8,LSL #3

  (654) 0x45546c SUB	X8, X14, X4

  (654) 0x455470 SUB	X8, X8, #8

  (654) 0x455474 UBFM	X8, X8, #3, #63

  (654) 0x455478 ADD	X8, X8, #1

  (654) 0x45547c ANDS	X8, X8, #0x3

  (654) 0x455480 B.EQ	455520

  (654) 0x455484 CMP	X8, #1

  (654) 0x455488 B.EQ	4554ec

  (654) 0x45548c CMP	X8, #2

  (654) 0x455490 B.EQ	4554c0

  (654) 0x455494 LDR	X24, [X24, X2]

  (654) 0x455498 UBFM	X2, X24, #61, #60

  (654) 0x45549c LDR	X8, [X20, X2]

  (654) 0x4554a0 CMP	X0, X8

  (654) 0x4554a4 B.EQ	4554bc

  (654) 0x4554a8 LDR	X24, [X23, X1]

  (654) 0x4554ac ADD	X6, X6, #1

  (654) 0x4554b0 ADD	X8, X24, #1

  (654) 0x4554b4 STR	X8, [X23, X1]

  (654) 0x4554b8 STR	X0, [X20, X2]

  (654) 0x4554bc ADD	X4, X4, #8

  (654) 0x4554c0 LDR	X2, [X4]

  (654) 0x4554c4 UBFM	X8, X2, #61, #60

  (654) 0x4554c8 LDR	X24, [X20, X8]

  (654) 0x4554cc CMP	X0, X24

  (654) 0x4554d0 B.EQ	4554e8

  (654) 0x4554d4 LDR	X2, [X23, X1]

  (654) 0x4554d8 ADD	X6, X6, #1

  (654) 0x4554dc ADD	X24, X2, #1

  (654) 0x4554e0 STR	X24, [X23, X1]

  (654) 0x4554e4 STR	X0, [X20, X8]

  (654) 0x4554e8 ADD	X4, X4, #8

  (654) 0x4554ec LDR	X8, [X4]

  (654) 0x4554f0 UBFM	X2, X8, #61, #60

  (654) 0x4554f4 LDR	X24, [X20, X2]

  (654) 0x4554f8 CMP	X0, X24

  (654) 0x4554fc B.EQ	455514

  (654) 0x455500 LDR	X8, [X23, X1]

  (654) 0x455504 ADD	X6, X6, #1

  (654) 0x455508 ADD	X24, X8, #1

  (654) 0x45550c STR	X24, [X23, X1]

  (654) 0x455510 STR	X0, [X20, X2]

  (654) 0x455514 ADD	X4, X4, #8

  (654) 0x455518 CMP	X14, X4

  (654) 0x45551c B.EQ	4555d0

    (656) 0x455520 LDR	X2, [X4]

    (656) 0x455524 ADD	X8, X4, #8

    (656) 0x455528 UBFM	X2, X2, #61, #60

    (656) 0x45552c LDR	X24, [X20, X2]

    (656) 0x455530 CMP	X0, X24

    (656) 0x455534 B.EQ	45554c

    (656) 0x455538 LDR	X24, [X23, X1]

    (656) 0x45553c ADD	X6, X6, #1

    (656) 0x455540 ADD	X24, X24, #1

    (656) 0x455544 STR	X24, [X23, X1]

    (656) 0x455548 STR	X0, [X20, X2]

    (656) 0x45554c LDR	X4, [X4, #8]

    (656) 0x455550 UBFM	X2, X4, #61, #60

    (656) 0x455554 LDR	X24, [X20, X2]

    (656) 0x455558 CMP	X0, X24

    (656) 0x45555c B.EQ	455574

    (656) 0x455560 LDR	X4, [X23, X1]

    (656) 0x455564 ADD	X6, X6, #1

    (656) 0x455568 ADD	X24, X4, #1

    (656) 0x45556c STR	X24, [X23, X1]

    (656) 0x455570 STR	X0, [X20, X2]

    (656) 0x455574 LDR	X2, [X8, #8]

    (656) 0x455578 ADD	X4, X8, #24

    (656) 0x45557c UBFM	X2, X2, #61, #60

    (656) 0x455580 LDR	X24, [X20, X2]

    (656) 0x455584 CMP	X0, X24

    (656) 0x455588 B.EQ	4555a0

    (656) 0x45558c LDR	X24, [X23, X1]

    (656) 0x455590 ADD	X6, X6, #1

    (656) 0x455594 ADD	X24, X24, #1

    (656) 0x455598 STR	X24, [X23, X1]

    (656) 0x45559c STR	X0, [X20, X2]

    (656) 0x4555a0 LDR	X8, [X8, #16]

    (656) 0x4555a4 UBFM	X2, X8, #61, #60

    (656) 0x4555a8 LDR	X24, [X20, X2]

    (656) 0x4555ac CMP	X0, X24

    (656) 0x4555b0 B.EQ	4555c8

    (656) 0x4555b4 LDR	X8, [X23, X1]

    (656) 0x4555b8 ADD	X6, X6, #1

    (656) 0x4555bc ADD	X24, X8, #1

    (656) 0x4555c0 STR	X24, [X23, X1]

    (656) 0x4555c4 STR	X0, [X20, X2]

    (656) 0x4555c8 CMP	X14, X4

    (656) 0x4555cc B.NE	455520

  (654) 0x4555d0 LDR	X14, [SP, #96]

  (654) 0x4555d4 LDR	X17, [X21, X17]

  (654) 0x4555d8 LDR	X4, [X16, X14]

  (654) 0x4555dc ADD	X2, X4, X17

  (654) 0x4555e0 CMP	X4, X2

  (654) 0x4555e4 B.GE	45575c

  (654) 0x4555e8 LDUR	X17, [X30, #504]

  (654) 0x4555ec UBFM	X24, X4, #61, #60

  (654) 0x4555f0 ADD	X8, X17, X2,LSL #3

  (654) 0x4555f4 ADD	X2, X17, X4,LSL #3

  (654) 0x4555f8 SUB	X14, X8, X2

  (654) 0x4555fc SUB	X4, X14, #8

  (654) 0x455600 UBFM	X14, X4, #3, #63

  (654) 0x455604 ADD	X4, X14, #1

  (654) 0x455608 ANDS	X14, X4, #0x3

  (654) 0x45560c B.EQ	4556ac

  (654) 0x455610 CMP	X14, #1

  (654) 0x455614 B.EQ	455678

  (654) 0x455618 CMP	X14, #2

  (654) 0x45561c B.EQ	45564c

  (654) 0x455620 LDR	X24, [X17, X24]

  (654) 0x455624 UBFM	X17, X24, #61, #60

  (654) 0x455628 LDR	X4, [X19, X17]

  (654) 0x45562c CMP	X0, X4

  (654) 0x455630 B.EQ	455648

  (654) 0x455634 LDR	X14, [X21, X1]

  (654) 0x455638 ADD	X5, X5, #1

  (654) 0x45563c ADD	X24, X14, #1

  (654) 0x455640 STR	X24, [X21, X1]

  (654) 0x455644 STR	X0, [X19, X17]

  (654) 0x455648 ADD	X2, X2, #8

  (654) 0x45564c LDR	X17, [X2]

  (654) 0x455650 UBFM	X4, X17, #61, #60

  (654) 0x455654 LDR	X14, [X19, X4]

  (654) 0x455658 CMP	X0, X14

  (654) 0x45565c B.EQ	455674

  (654) 0x455660 LDR	X24, [X21, X1]

  (654) 0x455664 ADD	X5, X5, #1

  (654) 0x455668 ADD	X17, X24, #1

  (654) 0x45566c STR	X17, [X21, X1]

  (654) 0x455670 STR	X0, [X19, X4]

  (654) 0x455674 ADD	X2, X2, #8

  (654) 0x455678 LDR	X4, [X2]

  (654) 0x45567c UBFM	X24, X4, #61, #60

  (654) 0x455680 LDR	X14, [X19, X24]

  (654) 0x455684 CMP	X0, X14

  (654) 0x455688 B.EQ	4556a0

  (654) 0x45568c LDR	X17, [X21, X1]

  (654) 0x455690 ADD	X5, X5, #1

  (654) 0x455694 ADD	X4, X17, #1

  (654) 0x455698 STR	X4, [X21, X1]

  (654) 0x45569c STR	X0, [X19, X24]

  (654) 0x4556a0 ADD	X2, X2, #8

  (654) 0x4556a4 CMP	X2, X8

  (654) 0x4556a8 B.EQ	45575c

    (655) 0x4556ac LDR	X14, [X2]

    (655) 0x4556b0 ADD	X24, X2, #8

    (655) 0x4556b4 UBFM	X4, X14, #61, #60

    (655) 0x4556b8 LDR	X17, [X19, X4]

    (655) 0x4556bc CMP	X0, X17

    (655) 0x4556c0 B.EQ	4556d8

    (655) 0x4556c4 LDR	X14, [X21, X1]

    (655) 0x4556c8 ADD	X5, X5, #1

    (655) 0x4556cc ADD	X17, X14, #1

    (655) 0x4556d0 STR	X17, [X21, X1]

    (655) 0x4556d4 STR	X0, [X19, X4]

    (655) 0x4556d8 LDR	X2, [X2, #8]

    (655) 0x4556dc UBFM	X14, X2, #61, #60

    (655) 0x4556e0 LDR	X4, [X19, X14]

    (655) 0x4556e4 CMP	X0, X4

    (655) 0x4556e8 B.EQ	455700

    (655) 0x4556ec LDR	X17, [X21, X1]

    (655) 0x4556f0 ADD	X5, X5, #1

    (655) 0x4556f4 ADD	X2, X17, #1

    (655) 0x4556f8 STR	X2, [X21, X1]

    (655) 0x4556fc STR	X0, [X19, X14]

    (655) 0x455700 LDR	X14, [X24, #8]

    (655) 0x455704 ADD	X2, X24, #24

    (655) 0x455708 UBFM	X4, X14, #61, #60

    (655) 0x45570c LDR	X17, [X19, X4]

    (655) 0x455710 CMP	X0, X17

    (655) 0x455714 B.EQ	45572c

    (655) 0x455718 LDR	X14, [X21, X1]

    (655) 0x45571c ADD	X5, X5, #1

    (655) 0x455720 ADD	X17, X14, #1

    (655) 0x455724 STR	X17, [X21, X1]

    (655) 0x455728 STR	X0, [X19, X4]

    (655) 0x45572c LDR	X24, [X24, #16]

    (655) 0x455730 UBFM	X4, X24, #61, #60

    (655) 0x455734 LDR	X14, [X19, X4]

    (655) 0x455738 CMP	X0, X14

    (655) 0x45573c B.EQ	455754

    (655) 0x455740 LDR	X17, [X21, X1]

    (655) 0x455744 ADD	X5, X5, #1

    (655) 0x455748 ADD	X24, X17, #1

    (655) 0x45574c STR	X24, [X21, X1]

    (655) 0x455750 STR	X0, [X19, X4]

    (655) 0x455754 CMP	X2, X8

    (655) 0x455758 B.NE	4556ac

  (654) 0x45575c LDR	X8, [X9]

  (654) 0x455760 ADD	X3, X3, #1

  (654) 0x455764 CMP	X3, X8

  (654) 0x455768 B.LT	455428

0x45576c LDR	X9, [SP, #128]

0x455770 ORR	X24, XZR, X28

0x455774 LDR	X3, [X11, X10]

0x455778 ADD	X10, X11, X1

0x45577c LDR	X4, [X11, X1]

0x455780 CMP	X3, X4

0x455784 B.GE	4558c0

0x455788 LDP	X14, X28, [SP, #112]

0x45578c ORR	X2, XZR, X10

0x455790 B	4557a0

  (652) 0x455794 ADD	X3, X3, #1

  (652) 0x455798 CMP	X3, X4

  (652) 0x45579c B.GE	4558c0

  (652) 0x4557a0 LDR	X17, [X26, X3,LSL #3]

  (652) 0x4557a4 UBFM	X8, X17, #61, #60

  (652) 0x4557a8 LDR	X10, [X24, X8]

  (652) 0x4557ac CMP	X10, X7

  (652) 0x4557b0 B.NE	455794

  (652) 0x4557b4 ADD	X17, X14, X8

  (652) 0x4557b8 LDR	X8, [X13, X8]

  (652) 0x4557bc LDR	X10, [X17, #8]

  (652) 0x4557c0 ADD	X10, X8, X10

  (652) 0x4557c4 CMP	X8, X10

  (652) 0x4557c8 B.GE	455794

  (652) 0x4557cc LDR	X17, [X28, X22]

  (652) 0x4557d0 UBFM	X4, X8, #61, #60

  (652) 0x4557d4 STR	X4, [SP, #96]

  (652) 0x4557d8 ADD	X10, X17, X10,LSL #3

  (652) 0x4557dc ADD	X4, X17, X8,LSL #3

  (652) 0x4557e0 SUB	X8, X10, X4

  (652) 0x4557e4 SUB	X8, X8, #8

  (652) 0x4557e8 UBFM	X8, X8, #3, #63

  (652) 0x4557ec ADD	X8, X8, #1

  (652) 0x4557f0 ANDS	X8, X8, #0x3

  (652) 0x4557f4 B.EQ	455afc

  (652) 0x4557f8 CMP	X8, #1

  (652) 0x4557fc B.EQ	45586c

  (652) 0x455800 CMP	X8, #2

  (652) 0x455804 B.EQ	45583c

  (652) 0x455808 LDR	X8, [SP, #96]

  (652) 0x45580c LDR	X17, [X17, X8]

  (652) 0x455810 TBNZ	X17, #63, 455c1c

  (652) 0x455814 UBFM	X8, X17, #61, #60

  (652) 0x455818 LDR	X17, [X19, X8]

  (652) 0x45581c CMP	X0, X17

  (652) 0x455820 B.EQ	455838

  (652) 0x455824 LDR	X17, [X21, X1]

  (652) 0x455828 ADD	X5, X5, #1

  (652) 0x45582c ADD	X17, X17, #1

  (652) 0x455830 STR	X17, [X21, X1]

  (652) 0x455834 STR	X0, [X19, X8]

  (652) 0x455838 ADD	X4, X4, #8

  (652) 0x45583c LDR	X8, [X4]

  (652) 0x455840 TBNZ	X8, #63, 455bf0

  (652) 0x455844 UBFM	X8, X8, #61, #60

  (652) 0x455848 LDR	X17, [X19, X8]

  (652) 0x45584c CMP	X0, X17

  (652) 0x455850 B.EQ	455868

  (652) 0x455854 LDR	X17, [X21, X1]

  (652) 0x455858 ADD	X5, X5, #1

  (652) 0x45585c ADD	X17, X17, #1

  (652) 0x455860 STR	X17, [X21, X1]

  (652) 0x455864 STR	X0, [X19, X8]

  (652) 0x455868 ADD	X4, X4, #8

  (652) 0x45586c LDR	X8, [X4]

  (652) 0x455870 TBNZ	X8, #63, 455bc4

  (652) 0x455874 UBFM	X8, X8, #61, #60

  (652) 0x455878 LDR	X17, [X19, X8]

  (652) 0x45587c CMP	X0, X17

  (652) 0x455880 B.EQ	455898

  (652) 0x455884 LDR	X17, [X21, X1]

  (652) 0x455888 ADD	X5, X5, #1

  (652) 0x45588c ADD	X17, X17, #1

  (652) 0x455890 STR	X17, [X21, X1]

  (652) 0x455894 STR	X0, [X19, X8]

  (652) 0x455898 ADD	X4, X4, #8

  (652) 0x45589c CMP	X4, X10

  (652) 0x4558a0 B.NE	455afc

  (652) 0x4558a4 LDR	X4, [X2]

  (652) 0x4558a8 ADD	X3, X3, #1

  (652) 0x4558ac CMP	X3, X4

  (652) 0x4558b0 B.LT	4557a0

0x4558b4 HINT	#0

0x4558b8 HINT	#0

0x4558bc HINT	#0

0x4558c0 ADD	X15, X15, #1

0x4558c4 CMP	X9, X15

0x4558c8 B.GT	4553e0

    (653) 0x455a44 UBFM	X8, X8, #61, #60

    (653) 0x455a48 LDR	X17, [X19, X8]

    (653) 0x455a4c CMP	X0, X17

    (653) 0x455a50 B.EQ	455a68

    (653) 0x455a54 LDR	X17, [X21, X1]

    (653) 0x455a58 ADD	X5, X5, #1

    (653) 0x455a5c ADD	X17, X17, #1

    (653) 0x455a60 STR	X17, [X21, X1]

    (653) 0x455a64 STR	X0, [X19, X8]

    (653) 0x455a68 LDR	X8, [X4, #8]

    (653) 0x455a6c ADD	X4, X4, #8

    (653) 0x455a70 TBNZ	X8, #63, 455b38

    (653) 0x455a74 UBFM	X8, X8, #61, #60

    (653) 0x455a78 LDR	X17, [X19, X8]

    (653) 0x455a7c CMP	X0, X17

    (653) 0x455a80 B.EQ	455a98

    (653) 0x455a84 LDR	X17, [X21, X1]

    (653) 0x455a88 ADD	X5, X5, #1

    (653) 0x455a8c ADD	X17, X17, #1

    (653) 0x455a90 STR	X17, [X21, X1]

    (653) 0x455a94 STR	X0, [X19, X8]

    (653) 0x455a98 LDR	X8, [X4, #8]

    (653) 0x455a9c TBNZ	X8, #63, 455b68

    (653) 0x455aa0 UBFM	X8, X8, #61, #60

    (653) 0x455aa4 LDR	X17, [X19, X8]

    (653) 0x455aa8 CMP	X0, X17

    (653) 0x455aac B.EQ	455ac4

    (653) 0x455ab0 LDR	X17, [X21, X1]

    (653) 0x455ab4 ADD	X5, X5, #1

    (653) 0x455ab8 ADD	X17, X17, #1

    (653) 0x455abc STR	X17, [X21, X1]

    (653) 0x455ac0 STR	X0, [X19, X8]

    (653) 0x455ac4 LDR	X8, [X4, #16]

    (653) 0x455ac8 TBNZ	X8, #63, 455b98

    (653) 0x455acc UBFM	X8, X8, #61, #60

    (653) 0x455ad0 LDR	X17, [X19, X8]

    (653) 0x455ad4 CMP	X0, X17

    (653) 0x455ad8 B.EQ	455af0

    (653) 0x455adc LDR	X17, [X21, X1]

    (653) 0x455ae0 ADD	X5, X5, #1

    (653) 0x455ae4 ADD	X17, X17, #1

    (653) 0x455ae8 STR	X17, [X21, X1]

    (653) 0x455aec STR	X0, [X19, X8]

    (653) 0x455af0 ADD	X4, X4, #24

    (653) 0x455af4 CMP	X4, X10

    (653) 0x455af8 B.EQ	4558a4

    (653) 0x455afc LDR	X8, [X4]

    (653) 0x455b00 TBZ	X8, #63, 455a44

    (653) 0x455b04 ORN	X8, XZR, X8

    (653) 0x455b08 UBFM	X8, X8, #61, #60

    (653) 0x455b0c LDR	X17, [X20, X8]

    (653) 0x455b10 CMP	X0, X17

    (653) 0x455b14 B.EQ	455a68

    (653) 0x455b18 LDR	X17, [X23, X1]

    (653) 0x455b1c ADD	X6, X6, #1

    (653) 0x455b20 ADD	X4, X4, #8

    (653) 0x455b24 ADD	X17, X17, #1

    (653) 0x455b28 STR	X17, [X23, X1]

    (653) 0x455b2c STR	X0, [X20, X8]

    (653) 0x455b30 LDR	X8, [X4]

    (653) 0x455b34 TBZ	X8, #63, 455a74

    (653) 0x455b38 ORN	X8, XZR, X8

    (653) 0x455b3c UBFM	X8, X8, #61, #60

    (653) 0x455b40 LDR	X17, [X20, X8]

    (653) 0x455b44 CMP	X0, X17

    (653) 0x455b48 B.EQ	455a98

    (653) 0x455b4c LDR	X17, [X23, X1]

    (653) 0x455b50 ADD	X6, X6, #1

    (653) 0x455b54 ADD	X17, X17, #1

    (653) 0x455b58 STR	X17, [X23, X1]

    (653) 0x455b5c STR	X0, [X20, X8]

    (653) 0x455b60 LDR	X8, [X4, #8]

    (653) 0x455b64 TBZ	X8, #63, 455aa0

    (653) 0x455b68 ORN	X8, XZR, X8

    (653) 0x455b6c UBFM	X8, X8, #61, #60

    (653) 0x455b70 LDR	X17, [X20, X8]

    (653) 0x455b74 CMP	X0, X17

    (653) 0x455b78 B.EQ	455ac4

    (653) 0x455b7c LDR	X17, [X23, X1]

    (653) 0x455b80 ADD	X6, X6, #1

    (653) 0x455b84 ADD	X17, X17, #1

    (653) 0x455b88 STR	X17, [X23, X1]

    (653) 0x455b8c STR	X0, [X20, X8]

    (653) 0x455b90 LDR	X8, [X4, #16]

    (653) 0x455b94 TBZ	X8, #63, 455acc

    (653) 0x455b98 ORN	X8, XZR, X8

    (653) 0x455b9c UBFM	X8, X8, #61, #60

    (653) 0x455ba0 LDR	X17, [X20, X8]

    (653) 0x455ba4 CMP	X0, X17

    (653) 0x455ba8 B.EQ	455af0

    (653) 0x455bac LDR	X17, [X23, X1]

    (653) 0x455bb0 ADD	X6, X6, #1

    (653) 0x455bb4 ADD	X17, X17, #1

    (653) 0x455bb8 STR	X17, [X23, X1]

    (653) 0x455bbc STR	X0, [X20, X8]

    (653) 0x455bc0 B	455af0

  (652) 0x455bc4 ORN	X8, XZR, X8

  (652) 0x455bc8 UBFM	X8, X8, #61, #60

  (652) 0x455bcc LDR	X17, [X20, X8]

  (652) 0x455bd0 CMP	X0, X17

  (652) 0x455bd4 B.EQ	455898

  (652) 0x455bd8 LDR	X17, [X23, X1]

  (652) 0x455bdc ADD	X6, X6, #1

  (652) 0x455be0 ADD	X17, X17, #1

  (652) 0x455be4 STR	X17, [X23, X1]

  (652) 0x455be8 STR	X0, [X20, X8]

  (652) 0x455bec B	455898

  (652) 0x455bf0 ORN	X8, XZR, X8

  (652) 0x455bf4 UBFM	X8, X8, #61, #60

  (652) 0x455bf8 LDR	X17, [X20, X8]

  (652) 0x455bfc CMP	X0, X17

  (652) 0x455c00 B.EQ	455868

  (652) 0x455c04 LDR	X17, [X23, X1]

  (652) 0x455c08 ADD	X6, X6, #1

  (652) 0x455c0c ADD	X17, X17, #1

  (652) 0x455c10 STR	X17, [X23, X1]

  (652) 0x455c14 STR	X0, [X20, X8]

  (652) 0x455c18 B	455868

  (652) 0x455c1c ORN	X8, XZR, X17

  (652) 0x455c20 UBFM	X8, X8, #61, #60

  (652) 0x455c24 LDR	X17, [X20, X8]

  (652) 0x455c28 CMP	X0, X17

  (652) 0x455c2c B.EQ	455838

  (652) 0x455c30 LDR	X17, [X23, X1]

  (652) 0x455c34 ADD	X6, X6, #1

  (652) 0x455c38 ADD	X17, X17, #1

  (652) 0x455c3c STR	X17, [X23, X1]

  (652) 0x455c40 STR	X0, [X20, X8]

  (652) 0x455c44 B	455838

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 939 - 999

--------------------------------------------------------------------------------

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

Coverage (%)	Name	Source Location	Module
►98.84+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.16+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P10,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	3.83
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	0.96
Front-end cycles	3.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.83
P11 cycles	3.50
P12 cycles	3.67
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	28.00
Nb loads	NA
Nb stores	3.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P10,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	3.83
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	0.96
Front-end cycles	3.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.83
P11 cycles	3.50
P12 cycles	3.67
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	28.00
Nb loads	NA
Nb stores	3.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-970,976-999.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 0.96 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	31
nb uops	28
loop length	124
used w registers	0
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	2.50	2.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	3.83
Overall L1	3.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4553e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X14, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X10, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [X18, X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X5, [X16, X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X12, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [X12, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 455774 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x568>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X9, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 455428 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X3, [X11, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X10, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X11, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4558c0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x6b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X2, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4557a0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x594>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 4553e0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 0.96 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	31
nb uops	28
loop length	124
used w registers	0
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	2.50	2.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	3.83
Overall L1	3.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4553e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X14, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X10, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [X18, X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X5, [X16, X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X12, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [X12, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 455774 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x568>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X9, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 455428 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X3, [X11, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X10, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X11, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4558c0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x6b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X2, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4557a0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x594>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 4553e0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code