OV - exec - Loop 654

	Loop Id: 654	Module: exec	Source: par_multi_interp.c:944-970	Coverage: 0.52%

0x45541c ADD	X3, X3, #1

0x455420 CMP	X3, X8

0x455424 B.GE	45576c

0x455428 LDR	X24, [X27, X3,LSL #3]

0x45542c UBFM	X2, X24, #61, #60

0x455430 LDR	X17, [X25, X2]

0x455434 STR	X2, [SP, #96]

0x455438 CMP	X17, X7

0x45543c B.NE	45541c

0x455440 ADD	X17, X2, #8

0x455444 LDR	X8, [X18, X2]

0x455448 LDR	X14, [X23, X17]

0x45544c ADD	X4, X8, X14

0x455450 CMP	X8, X4

0x455454 B.GE	4555d0

0x455458 LDR	X24, [SP, #144]

0x45545c UBFM	X2, X8, #61, #60

0x455460 LDUR	X24, [X24, #504]

0x455464 ADD	X14, X24, X4,LSL #3

0x455468 ADD	X4, X24, X8,LSL #3

0x45546c SUB	X8, X14, X4

0x455470 SUB	X8, X8, #8

0x455474 UBFM	X8, X8, #3, #63

0x455478 ADD	X8, X8, #1

0x45547c ANDS	X8, X8, #0x3

0x455480 B.EQ	455520

0x455484 CMP	X8, #1

0x455488 B.EQ	4554ec

0x45548c CMP	X8, #2

0x455490 B.EQ	4554c0

0x455494 LDR	X24, [X24, X2]

0x455498 UBFM	X2, X24, #61, #60

0x45549c LDR	X8, [X20, X2]

0x4554a0 CMP	X0, X8

0x4554a4 B.EQ	4554bc

0x4554a8 LDR	X24, [X23, X1]

0x4554ac ADD	X6, X6, #1

0x4554b0 ADD	X8, X24, #1

0x4554b4 STR	X8, [X23, X1]

0x4554b8 STR	X0, [X20, X2]

0x4554bc ADD	X4, X4, #8

0x4554c0 LDR	X2, [X4]

0x4554c4 UBFM	X8, X2, #61, #60

0x4554c8 LDR	X24, [X20, X8]

0x4554cc CMP	X0, X24

0x4554d0 B.EQ	4554e8

0x4554d4 LDR	X2, [X23, X1]

0x4554d8 ADD	X6, X6, #1

0x4554dc ADD	X24, X2, #1

0x4554e0 STR	X24, [X23, X1]

0x4554e4 STR	X0, [X20, X8]

0x4554e8 ADD	X4, X4, #8

0x4554ec LDR	X8, [X4]

0x4554f0 UBFM	X2, X8, #61, #60

0x4554f4 LDR	X24, [X20, X2]

0x4554f8 CMP	X0, X24

0x4554fc B.EQ	455514

0x455500 LDR	X8, [X23, X1]

0x455504 ADD	X6, X6, #1

0x455508 ADD	X24, X8, #1

0x45550c STR	X24, [X23, X1]

0x455510 STR	X0, [X20, X2]

0x455514 ADD	X4, X4, #8

0x455518 CMP	X14, X4

0x45551c B.EQ	4555d0

  (656) 0x455520 LDR	X2, [X4]

  (656) 0x455524 ADD	X8, X4, #8

  (656) 0x455528 UBFM	X2, X2, #61, #60

  (656) 0x45552c LDR	X24, [X20, X2]

  (656) 0x455530 CMP	X0, X24

  (656) 0x455534 B.EQ	45554c

  (656) 0x455538 LDR	X24, [X23, X1]

  (656) 0x45553c ADD	X6, X6, #1

  (656) 0x455540 ADD	X24, X24, #1

  (656) 0x455544 STR	X24, [X23, X1]

  (656) 0x455548 STR	X0, [X20, X2]

  (656) 0x45554c LDR	X4, [X4, #8]

  (656) 0x455550 UBFM	X2, X4, #61, #60

  (656) 0x455554 LDR	X24, [X20, X2]

  (656) 0x455558 CMP	X0, X24

  (656) 0x45555c B.EQ	455574

  (656) 0x455560 LDR	X4, [X23, X1]

  (656) 0x455564 ADD	X6, X6, #1

  (656) 0x455568 ADD	X24, X4, #1

  (656) 0x45556c STR	X24, [X23, X1]

  (656) 0x455570 STR	X0, [X20, X2]

  (656) 0x455574 LDR	X2, [X8, #8]

  (656) 0x455578 ADD	X4, X8, #24

  (656) 0x45557c UBFM	X2, X2, #61, #60

  (656) 0x455580 LDR	X24, [X20, X2]

  (656) 0x455584 CMP	X0, X24

  (656) 0x455588 B.EQ	4555a0

  (656) 0x45558c LDR	X24, [X23, X1]

  (656) 0x455590 ADD	X6, X6, #1

  (656) 0x455594 ADD	X24, X24, #1

  (656) 0x455598 STR	X24, [X23, X1]

  (656) 0x45559c STR	X0, [X20, X2]

  (656) 0x4555a0 LDR	X8, [X8, #16]

  (656) 0x4555a4 UBFM	X2, X8, #61, #60

  (656) 0x4555a8 LDR	X24, [X20, X2]

  (656) 0x4555ac CMP	X0, X24

  (656) 0x4555b0 B.EQ	4555c8

  (656) 0x4555b4 LDR	X8, [X23, X1]

  (656) 0x4555b8 ADD	X6, X6, #1

  (656) 0x4555bc ADD	X24, X8, #1

  (656) 0x4555c0 STR	X24, [X23, X1]

  (656) 0x4555c4 STR	X0, [X20, X2]

  (656) 0x4555c8 CMP	X14, X4

  (656) 0x4555cc B.NE	455520

0x4555d0 LDR	X14, [SP, #96]

0x4555d4 LDR	X17, [X21, X17]

0x4555d8 LDR	X4, [X16, X14]

0x4555dc ADD	X2, X4, X17

0x4555e0 CMP	X4, X2

0x4555e4 B.GE	45575c

0x4555e8 LDUR	X17, [X30, #504]

0x4555ec UBFM	X24, X4, #61, #60

0x4555f0 ADD	X8, X17, X2,LSL #3

0x4555f4 ADD	X2, X17, X4,LSL #3

0x4555f8 SUB	X14, X8, X2

0x4555fc SUB	X4, X14, #8

0x455600 UBFM	X14, X4, #3, #63

0x455604 ADD	X4, X14, #1

0x455608 ANDS	X14, X4, #0x3

0x45560c B.EQ	4556ac

0x455610 CMP	X14, #1

0x455614 B.EQ	455678

0x455618 CMP	X14, #2

0x45561c B.EQ	45564c

0x455620 LDR	X24, [X17, X24]

0x455624 UBFM	X17, X24, #61, #60

0x455628 LDR	X4, [X19, X17]

0x45562c CMP	X0, X4

0x455630 B.EQ	455648

0x455634 LDR	X14, [X21, X1]

0x455638 ADD	X5, X5, #1

0x45563c ADD	X24, X14, #1

0x455640 STR	X24, [X21, X1]

0x455644 STR	X0, [X19, X17]

0x455648 ADD	X2, X2, #8

0x45564c LDR	X17, [X2]

0x455650 UBFM	X4, X17, #61, #60

0x455654 LDR	X14, [X19, X4]

0x455658 CMP	X0, X14

0x45565c B.EQ	455674

0x455660 LDR	X24, [X21, X1]

0x455664 ADD	X5, X5, #1

0x455668 ADD	X17, X24, #1

0x45566c STR	X17, [X21, X1]

0x455670 STR	X0, [X19, X4]

0x455674 ADD	X2, X2, #8

0x455678 LDR	X4, [X2]

0x45567c UBFM	X24, X4, #61, #60

0x455680 LDR	X14, [X19, X24]

0x455684 CMP	X0, X14

0x455688 B.EQ	4556a0

0x45568c LDR	X17, [X21, X1]

0x455690 ADD	X5, X5, #1

0x455694 ADD	X4, X17, #1

0x455698 STR	X4, [X21, X1]

0x45569c STR	X0, [X19, X24]

0x4556a0 ADD	X2, X2, #8

0x4556a4 CMP	X2, X8

0x4556a8 B.EQ	45575c

  (655) 0x4556ac LDR	X14, [X2]

  (655) 0x4556b0 ADD	X24, X2, #8

  (655) 0x4556b4 UBFM	X4, X14, #61, #60

  (655) 0x4556b8 LDR	X17, [X19, X4]

  (655) 0x4556bc CMP	X0, X17

  (655) 0x4556c0 B.EQ	4556d8

  (655) 0x4556c4 LDR	X14, [X21, X1]

  (655) 0x4556c8 ADD	X5, X5, #1

  (655) 0x4556cc ADD	X17, X14, #1

  (655) 0x4556d0 STR	X17, [X21, X1]

  (655) 0x4556d4 STR	X0, [X19, X4]

  (655) 0x4556d8 LDR	X2, [X2, #8]

  (655) 0x4556dc UBFM	X14, X2, #61, #60

  (655) 0x4556e0 LDR	X4, [X19, X14]

  (655) 0x4556e4 CMP	X0, X4

  (655) 0x4556e8 B.EQ	455700

  (655) 0x4556ec LDR	X17, [X21, X1]

  (655) 0x4556f0 ADD	X5, X5, #1

  (655) 0x4556f4 ADD	X2, X17, #1

  (655) 0x4556f8 STR	X2, [X21, X1]

  (655) 0x4556fc STR	X0, [X19, X14]

  (655) 0x455700 LDR	X14, [X24, #8]

  (655) 0x455704 ADD	X2, X24, #24

  (655) 0x455708 UBFM	X4, X14, #61, #60

  (655) 0x45570c LDR	X17, [X19, X4]

  (655) 0x455710 CMP	X0, X17

  (655) 0x455714 B.EQ	45572c

  (655) 0x455718 LDR	X14, [X21, X1]

  (655) 0x45571c ADD	X5, X5, #1

  (655) 0x455720 ADD	X17, X14, #1

  (655) 0x455724 STR	X17, [X21, X1]

  (655) 0x455728 STR	X0, [X19, X4]

  (655) 0x45572c LDR	X24, [X24, #16]

  (655) 0x455730 UBFM	X4, X24, #61, #60

  (655) 0x455734 LDR	X14, [X19, X4]

  (655) 0x455738 CMP	X0, X14

  (655) 0x45573c B.EQ	455754

  (655) 0x455740 LDR	X17, [X21, X1]

  (655) 0x455744 ADD	X5, X5, #1

  (655) 0x455748 ADD	X24, X17, #1

  (655) 0x45574c STR	X24, [X21, X1]

  (655) 0x455750 STR	X0, [X19, X4]

  (655) 0x455754 CMP	X2, X8

  (655) 0x455758 B.NE	4556ac

0x45575c LDR	X8, [X9]

0x455760 ADD	X3, X3, #1

0x455764 CMP	X3, X8

0x455768 B.LT	455428

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 944 - 970

--------------------------------------------------------------------------------

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

Coverage (%)	Name	Source Location	Module
►98.41+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.59+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P2, P3, P4, P5,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:944-944,par_multi_interp.c:947-958,par_multi_interp.c:961-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.75
CQA cycles if no scalar integer	15.75
CQA cycles if FP arith vectorized	15.75
CQA cycles if fully vectorized	3.94
Front-end cycles	15.50
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	15.75
P3 cycles	15.75
P4 cycles	15.75
P5 cycles	15.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	14.17
P11 cycles	13.83
P12 cycles	14.00
P13 cycles	6.50
P14 cycles	6.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	124.00
Nb uops	124.00
Nb loads	NA
Nb stores	13.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P2, P3, P4, P5,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:944-944,par_multi_interp.c:947-958,par_multi_interp.c:961-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.75
CQA cycles if no scalar integer	15.75
CQA cycles if FP arith vectorized	15.75
CQA cycles if fully vectorized	3.94
Front-end cycles	15.50
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	15.75
P3 cycles	15.75
P4 cycles	15.75
P5 cycles	15.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	14.17
P11 cycles	13.83
P12 cycles	14.00
P13 cycles	6.50
P14 cycles	6.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	124.00
Nb uops	124.00
Nb loads	NA
Nb stores	13.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:944-970
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:944-970.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:944,947-958,961-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 65026 paths individually, rerun with max-paths=65026
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 65026 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 15.75 to 3.94 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	124
nb uops	124
loop length	496
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.50	9.50	15.75	15.75	15.75	15.75	0.00	0.00	0.00	0.00	14.17	13.83	14.00	6.50	6.50
cycles	9.50	9.50	15.75	15.75	15.75	15.75	0.00	0.00	0.00	0.00	14.17	13.83	14.00	6.50	6.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.50
Dispatch	15.75
Overall L1	15.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.75 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 455428

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X3, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45576c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X27, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X17, [X25, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X17, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45541c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X8, [X18, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X23, X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X8, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4555d0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x3c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDUR X24, [X24, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X24, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X24, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X8, X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X8, X8, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X8, X8, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 455520 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4554ec <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4554c0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X24, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X8, [X20, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4554bc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X23, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X8, [X23, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X20, X2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X2, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X8, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X24, [X20, X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4554e8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X23, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X24, [X23, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X20, X8]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X8, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X24, [X20, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455514 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X24, [X23, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X20, X2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4555d0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x3c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X21, X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16, X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45575c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X17, [X30, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X8, X17, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X2, X17, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X14, X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X4, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X14, X4, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X14, X4, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 4556ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455678 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x46c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45564c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X17, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X17, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X4, [X19, X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455648 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x43c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X24, [X21, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X19, X17]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X17, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X4, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X19, X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455674 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x468>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X17, [X21, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X19, X4]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X4, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4556a0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x494>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X4, [X21, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X2, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45575c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X3, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 455428 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:944-970
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 65026 paths individually, rerun with max-paths=65026
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	124
nb uops	124
loop length	496
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.50	9.50	15.75	15.75	15.75	15.75	0.00	0.00	0.00	0.00	14.17	13.83	14.00	6.50	6.50
cycles	9.50	9.50	15.75	15.75	15.75	15.75	0.00	0.00	0.00	0.00	14.17	13.83	14.00	6.50	6.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.50
Dispatch	15.75
Overall L1	15.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.75 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 455428

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X3, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45576c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X27, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X17, [X25, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X17, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45541c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X8, [X18, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X23, X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X8, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4555d0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x3c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDUR X24, [X24, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X24, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X24, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X8, X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X8, X8, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X8, X8, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 455520 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4554ec <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4554c0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X24, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X8, [X20, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4554bc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X23, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X8, [X23, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X20, X2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X2, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X8, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X24, [X20, X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4554e8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X23, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X24, [X23, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X20, X8]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X8, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X24, [X20, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455514 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X24, [X23, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X20, X2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4555d0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x3c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X21, X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16, X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45575c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X17, [X30, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X8, X17, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X2, X17, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X14, X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X4, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X14, X4, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X14, X4, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 4556ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455678 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x46c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45564c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X17, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X17, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X4, [X19, X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455648 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x43c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X24, [X21, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X19, X17]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X17, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X4, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X19, X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455674 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x468>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X17, [X21, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X19, X4]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X4, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4556a0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x494>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X4, [X21, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X2, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45575c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X3, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 455428 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code