OV - exec - Loop 684

	Loop Id: 684	Module: exec	Source: par_multi_interp.c:1811-1837	Coverage: 0.59%

0x458a58 LDR	X13, [X27, X5]

0x458a5c LDR	X17, [X27, X4]

0x458a60 CMP	X17, X13

0x458a64 B.EQ	458a9c

0x458a68 ADD	X0, X0, #1

0x458a6c CMP	X0, X14

0x458a70 B.EQ	458ab0

0x458a74 LDR	X17, [X12, X0,LSL #3]

0x458a78 UBFM	X5, X17, #61, #60

0x458a7c LDR	X28, [X26, X5]

0x458a80 CMP	X3, X28

0x458a84 B.EQ	458ff4

0x458a88 LDR	X6, [X7, X5]

0x458a8c CMN	X6, #3

0x458a90 B.EQ	458a68

0x458a94 CMP	X18, #1

0x458a98 B.NE	458a58

0x458a9c LDR	D28, [X21, X0,LSL #3]

0x458aa0 ADD	X0, X0, #1

0x458aa4 FADD	D18, D18, D28

0x458aa8 CMP	X0, X14

0x458aac B.NE	458a74

0x458ff4 ADD	X13, X5, #8

0x458ff8 LDR	X6, [X16, X5]

0x458ffc LDR	X17, [X16, X13]

0x459000 CMP	X6, X17

0x459004 B.GE	459194

0x459008 SUB	X28, X17, X6

0x45900c ANDS	X28, X28, #0x3

0x459010 B.EQ	4590bc

0x459014 CMP	X28, #1

0x459018 B.EQ	459084

0x45901c CMP	X28, #2

0x459020 B.EQ	459054

0x459024 LDR	X28, [X25, X6,LSL #3]

0x459028 LDR	D27, [X20, X6,LSL #3]

0x45902c ADD	X6, X6, #1

0x459030 LDR	D0, [X21, X0,LSL #3]

0x459034 LDR	X28, [X23, X28,LSL #3]

0x459038 FMUL	D1, D0, D27

0x45903c UBFM	X28, X28, #61, #60

0x459040 LDR	D7, [X20, X28]

0x459044 FADD	D29, D29, D1

0x459048 FADD	D18, D18, D1

0x45904c FADD	D2, D7, D1

0x459050 STR	D2, [X20, X28]

0x459054 LDR	X28, [X25, X6,LSL #3]

0x459058 LDR	D24, [X20, X6,LSL #3]

0x45905c ADD	X6, X6, #1

0x459060 LDR	D25, [X21, X0,LSL #3]

0x459064 LDR	X28, [X23, X28,LSL #3]

0x459068 FMUL	D3, D25, D24

0x45906c UBFM	X28, X28, #61, #60

0x459070 LDR	D5, [X20, X28]

0x459074 FADD	D29, D29, D3

0x459078 FADD	D18, D18, D3

0x45907c FADD	D4, D5, D3

0x459080 STR	D4, [X20, X28]

0x459084 LDR	X28, [X25, X6,LSL #3]

0x459088 LDR	D16, [X20, X6,LSL #3]

0x45908c ADD	X6, X6, #1

0x459090 LDR	D6, [X21, X0,LSL #3]

0x459094 LDR	X28, [X23, X28,LSL #3]

0x459098 FMUL	D31, D6, D16

0x45909c UBFM	X28, X28, #61, #60

0x4590a0 LDR	D17, [X20, X28]

0x4590a4 FADD	D29, D29, D31

0x4590a8 FADD	D18, D18, D31

0x4590ac FADD	D19, D17, D31

0x4590b0 STR	D19, [X20, X28]

0x4590b4 CMP	X6, X17

0x4590b8 B.EQ	459194

0x4590bc STP	X26, X22, [SP, #168]

0x4590c0 STP	X9, X24, [SP, #184]

  (686) 0x4590c4 ADD	X22, X6, #1

  (686) 0x4590c8 ADD	X26, X6, #3

  (686) 0x4590cc ADD	X28, X22, #1

  (686) 0x4590d0 LDR	X24, [X25, X6,LSL #3]

  (686) 0x4590d4 LDR	D21, [X21, X0,LSL #3]

  (686) 0x4590d8 LDR	D20, [X20, X6,LSL #3]

  (686) 0x4590dc ADD	X6, X6, #4

  (686) 0x4590e0 LDR	X9, [X23, X24,LSL #3]

  (686) 0x4590e4 LDR	X24, [X25, X22,LSL #3]

  (686) 0x4590e8 FMUL	D22, D21, D20

  (686) 0x4590ec UBFM	X9, X9, #61, #60

  (686) 0x4590f0 LDR	D23, [X20, X9]

  (686) 0x4590f4 LDR	X24, [X23, X24,LSL #3]

  (686) 0x4590f8 FADD	D26, D29, D22

  (686) 0x4590fc FADD	D30, D18, D22

  (686) 0x459100 FADD	D31, D23, D22

  (686) 0x459104 UBFM	X24, X24, #61, #60

  (686) 0x459108 STR	D31, [X20, X9]

  (686) 0x45910c LDR	D0, [X20, X22,LSL #3]

  (686) 0x459110 LDR	D28, [X21, X0,LSL #3]

  (686) 0x459114 LDR	D27, [X20, X24]

  (686) 0x459118 LDR	X22, [X25, X28,LSL #3]

  (686) 0x45911c FMUL	D1, D28, D0

  (686) 0x459120 LDR	X9, [X25, X26,LSL #3]

  (686) 0x459124 LDR	X22, [X23, X22,LSL #3]

  (686) 0x459128 LDR	X9, [X23, X9,LSL #3]

  (686) 0x45912c FADD	D7, D27, D1

  (686) 0x459130 FADD	D2, D26, D1

  (686) 0x459134 FADD	D25, D30, D1

  (686) 0x459138 UBFM	X22, X22, #61, #60

  (686) 0x45913c UBFM	X9, X9, #61, #60

  (686) 0x459140 STR	D7, [X20, X24]

  (686) 0x459144 LDR	D24, [X21, X0,LSL #3]

  (686) 0x459148 LDR	D3, [X20, X28,LSL #3]

  (686) 0x45914c LDR	D5, [X20, X22]

  (686) 0x459150 FMUL	D4, D24, D3

  (686) 0x459154 FADD	D6, D5, D4

  (686) 0x459158 FADD	D17, D2, D4

  (686) 0x45915c FADD	D18, D25, D4

  (686) 0x459160 STR	D6, [X20, X22]

  (686) 0x459164 LDR	D29, [X20, X26,LSL #3]

  (686) 0x459168 LDR	D16, [X21, X0,LSL #3]

  (686) 0x45916c LDR	D19, [X20, X9]

  (686) 0x459170 FMUL	D31, D16, D29

  (686) 0x459174 FADD	D21, D19, D31

  (686) 0x459178 FADD	D29, D17, D31

  (686) 0x45917c FADD	D18, D18, D31

  (686) 0x459180 STR	D21, [X20, X9]

  (686) 0x459184 CMP	X6, X17

  (686) 0x459188 B.NE	4590c4

0x45918c LDP	X26, X22, [SP, #168]

0x459190 LDP	X9, X24, [SP, #184]

0x459194 LDR	X17, [SP, #120]

0x459198 LDR	X5, [X17, X5]

0x45919c LDR	X28, [X17, X13]

0x4591a0 CMP	X5, X28

0x4591a4 B.GE	458a68

0x4591a8 SUB	X13, X28, X5

0x4591ac ANDS	X6, X13, #0x3

0x4591b0 B.EQ	45925c

0x4591b4 CMP	X6, #1

0x4591b8 B.EQ	459224

0x4591bc CMP	X6, #2

0x4591c0 B.EQ	4591f4

0x4591c4 LDR	X17, [X24, X5,LSL #3]

0x4591c8 LDR	D22, [X19, X5,LSL #3]

0x4591cc ADD	X5, X5, #1

0x4591d0 LDR	D20, [X21, X0,LSL #3]

0x4591d4 LDR	X13, [X22, X17,LSL #3]

0x4591d8 FMUL	D23, D20, D22

0x4591dc UBFM	X6, X13, #61, #60

0x4591e0 LDR	D26, [X19, X6]

0x4591e4 FADD	D29, D29, D23

0x4591e8 FADD	D18, D18, D23

0x4591ec FADD	D30, D26, D23

0x4591f0 STR	D30, [X19, X6]

0x4591f4 LDR	X17, [X24, X5,LSL #3]

0x4591f8 LDR	D28, [X19, X5,LSL #3]

0x4591fc ADD	X5, X5, #1

0x459200 LDR	D31, [X21, X0,LSL #3]

0x459204 LDR	X13, [X22, X17,LSL #3]

0x459208 FMUL	D0, D31, D28

0x45920c UBFM	X6, X13, #61, #60

0x459210 LDR	D27, [X19, X6]

0x459214 FADD	D29, D29, D0

0x459218 FADD	D18, D18, D0

0x45921c FADD	D1, D27, D0

0x459220 STR	D1, [X19, X6]

0x459224 LDR	X17, [X24, X5,LSL #3]

0x459228 LDR	D2, [X19, X5,LSL #3]

0x45922c ADD	X5, X5, #1

0x459230 LDR	D7, [X21, X0,LSL #3]

0x459234 LDR	X13, [X22, X17,LSL #3]

0x459238 FMUL	D31, D7, D2

0x45923c UBFM	X6, X13, #61, #60

0x459240 LDR	D25, [X19, X6]

0x459244 FADD	D29, D29, D31

0x459248 FADD	D18, D18, D31

0x45924c FADD	D24, D25, D31

0x459250 STR	D24, [X19, X6]

0x459254 CMP	X5, X28

0x459258 B.EQ	458a68

0x45925c STP	X26, X23, [SP, #168]

  (685) 0x459260 ADD	X13, X5, #1

  (685) 0x459264 ADD	X23, X5, #3

  (685) 0x459268 LDR	X26, [X24, X5,LSL #3]

  (685) 0x45926c LDR	D3, [X21, X0,LSL #3]

  (685) 0x459270 LDR	D5, [X19, X5,LSL #3]

  (685) 0x459274 ADD	X5, X5, #4

  (685) 0x459278 LDR	X17, [X22, X26,LSL #3]

  (685) 0x45927c ADD	X26, X13, #1

  (685) 0x459280 FMUL	D4, D3, D5

  (685) 0x459284 UBFM	X6, X17, #61, #60

  (685) 0x459288 LDR	X17, [X24, X13,LSL #3]

  (685) 0x45928c LDR	D6, [X19, X6]

  (685) 0x459290 LDR	X17, [X22, X17,LSL #3]

  (685) 0x459294 FADD	D17, D29, D4

  (685) 0x459298 FADD	D18, D18, D4

  (685) 0x45929c FADD	D16, D6, D4

  (685) 0x4592a0 UBFM	X17, X17, #61, #60

  (685) 0x4592a4 STR	D16, [X19, X6]

  (685) 0x4592a8 LDR	D29, [X21, X0,LSL #3]

  (685) 0x4592ac LDR	D19, [X19, X13,LSL #3]

  (685) 0x4592b0 LDR	D21, [X19, X17]

  (685) 0x4592b4 LDR	X13, [X24, X26,LSL #3]

  (685) 0x4592b8 FMUL	D20, D29, D19

  (685) 0x4592bc LDR	X6, [X24, X23,LSL #3]

  (685) 0x4592c0 LDR	X13, [X22, X13,LSL #3]

  (685) 0x4592c4 LDR	X6, [X22, X6,LSL #3]

  (685) 0x4592c8 FADD	D22, D21, D20

  (685) 0x4592cc FADD	D26, D18, D20

  (685) 0x4592d0 FADD	D23, D17, D20

  (685) 0x4592d4 UBFM	X13, X13, #61, #60

  (685) 0x4592d8 UBFM	X6, X6, #61, #60

  (685) 0x4592dc STR	D22, [X19, X17]

  (685) 0x4592e0 LDR	D31, [X19, X26,LSL #3]

  (685) 0x4592e4 LDR	D30, [X21, X0,LSL #3]

  (685) 0x4592e8 LDR	D28, [X19, X13]

  (685) 0x4592ec FMUL	D0, D30, D31

  (685) 0x4592f0 FADD	D27, D28, D0

  (685) 0x4592f4 FADD	D1, D23, D0

  (685) 0x4592f8 FADD	D2, D26, D0

  (685) 0x4592fc STR	D27, [X19, X13]

  (685) 0x459300 LDR	D7, [X21, X0,LSL #3]

  (685) 0x459304 LDR	D25, [X19, X23,LSL #3]

  (685) 0x459308 LDR	D24, [X19, X6]

  (685) 0x45930c FMUL	D31, D7, D25

  (685) 0x459310 FADD	D3, D24, D31

  (685) 0x459314 FADD	D29, D1, D31

  (685) 0x459318 FADD	D18, D2, D31

  (685) 0x45931c STR	D3, [X19, X6]

  (685) 0x459320 CMP	X5, X28

  (685) 0x459324 B.NE	459260

0x459328 LDP	X26, X23, [SP, #168]

0x45932c B	458a68

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1811 - 1837

--------------------------------------------------------------------------------

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

Coverage (%)	Name	Source Location	Module
►98.56+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.44+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1884	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.57
CQA speedup if FP arith vectorized	1.56
CQA speedup if fully vectorized	3.82
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P10,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source	par_multi_interp.c:1811-1811,par_multi_interp.c:1814-1816,par_multi_interp.c:1819-1824,par_multi_interp.c:1827-1830,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.83
CQA cycles if no scalar integer	11.33
CQA cycles if FP arith vectorized	11.42
CQA cycles if fully vectorized	4.67
Front-end cycles	16.13
P0 cycles	8.50
P1 cycles	8.50
P2 cycles	8.50
P3 cycles	8.50
P4 cycles	8.50
P5 cycles	8.50
P6 cycles	7.75
P7 cycles	7.75
P8 cycles	7.75
P9 cycles	7.75
P10 cycles	17.83
P11 cycles	17.50
P12 cycles	17.67
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	129.00
Nb loads	NA
Nb stores	9.00
Nb stack references	7.00
FLOP/cycle	1.40
Nb FLOP add-sub	19.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	26.14
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.57
CQA speedup if FP arith vectorized	1.56
CQA speedup if fully vectorized	3.82
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P10,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source	par_multi_interp.c:1811-1811,par_multi_interp.c:1814-1816,par_multi_interp.c:1819-1824,par_multi_interp.c:1827-1830,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.83
CQA cycles if no scalar integer	11.33
CQA cycles if FP arith vectorized	11.42
CQA cycles if fully vectorized	4.67
Front-end cycles	16.13
P0 cycles	8.50
P1 cycles	8.50
P2 cycles	8.50
P3 cycles	8.50
P4 cycles	8.50
P5 cycles	8.50
P6 cycles	7.75
P7 cycles	7.75
P8 cycles	7.75
P9 cycles	7.75
P10 cycles	17.83
P11 cycles	17.50
P12 cycles	17.67
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	129.00
Nb loads	NA
Nb stores	9.00
Nb stack references	7.00
FLOP/cycle	1.40
Nb FLOP add-sub	19.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	26.14
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source file and lines	par_multi_interp.c:1811-1837
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1811-1837.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1811,1814-1816,1819-1824,1827-1830,1835-1837.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 68 paths individually, rerun with max-paths=68
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 68 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.83 to 11.33 cycles (1.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 17.83 to 4.67 cycles (3.82x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

19: addition or subtraction
6: multiply

The binary loop does not load or store any data.

General properties

nb instructions	129
nb uops	129
loop length	516
used w registers	0
used x registers	23
used b registers	0
used h registers	0
used s registers	1
used d registers	23
used q registers	0
used v registers	0
used z registers	0
nb stack references	7
ADD-SUB / MUL ratio	3.17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.13 cycles
front end	16.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	8.50	8.50	8.50	8.50	7.75	7.75	7.75	7.75	17.83	17.50	17.67	1.50	1.50
cycles	8.50	8.50	8.50	8.50	8.50	8.50	7.75	7.75	7.75	7.75	17.83	17.50	17.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.13
Dispatch	17.83
Overall L1	17.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	25%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	26%
load	25%
store	33%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 458a74

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X13, [X27, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X27, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 458a9c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 458ab0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X5, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X28, [X26, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 458ff4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xce8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X7, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMN X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 458a68 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x75c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 458a58 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x74c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D28, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D18, D18, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 458a74 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x768>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X16, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X16, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459194 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X28, X17, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X28, X28, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4590bc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xdb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459084 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459054 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [X25, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D27, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X28, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D1, D0, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
UBFM X28, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X20, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D29, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D18, D18, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D2, D7, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D2, [X20, X28]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X28, [X25, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D24, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X28, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D3, D25, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
UBFM X28, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X20, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D29, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D18, D18, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D4, D5, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D4, [X20, X28]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X28, [X25, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D16, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X28, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D31, D6, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
UBFM X28, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X20, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D29, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D18, D18, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D19, D17, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D19, [X20, X28]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459194 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X26, X22, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X24, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X22, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X9, X24, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X17, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [X17, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 458a68 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x75c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X13, X28, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X6, X13, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45925c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459224 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4591f4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xee8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X13, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D23, D20, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
UBFM X6, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D26, [X19, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D29, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D18, D18, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D30, D26, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D30, [X19, X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X17, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D28, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X13, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D0, D31, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
UBFM X6, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X19, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D29, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D18, D18, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D1, D27, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D1, [X19, X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X17, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D2, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X13, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D31, D7, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
UBFM X6, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X19, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D29, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D18, D18, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D24, D25, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D24, [X19, X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X5, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 458a68 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x75c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X26, X23, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X23, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 458a68 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x75c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source file and lines	par_multi_interp.c:1811-1837
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 68 paths individually, rerun with max-paths=68
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

19: addition or subtraction
6: multiply

The binary loop does not load or store any data.

General properties

nb instructions	129
nb uops	129
loop length	516
used w registers	0
used x registers	23
used b registers	0
used h registers	0
used s registers	1
used d registers	23
used q registers	0
used v registers	0
used z registers	0
nb stack references	7
ADD-SUB / MUL ratio	3.17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.13 cycles
front end	16.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	8.50	8.50	8.50	8.50	7.75	7.75	7.75	7.75	17.83	17.50	17.67	1.50	1.50
cycles	8.50	8.50	8.50	8.50	8.50	8.50	7.75	7.75	7.75	7.75	17.83	17.50	17.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.13
Dispatch	17.83
Overall L1	17.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	25%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	26%
load	25%
store	33%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 458a74

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X13, [X27, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X27, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 458a9c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 458ab0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X5, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X28, [X26, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 458ff4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xce8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X7, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMN X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 458a68 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x75c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 458a58 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x74c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D28, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D18, D18, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 458a74 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x768>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X16, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X16, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459194 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X28, X17, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X28, X28, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4590bc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xdb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459084 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459054 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [X25, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D27, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X28, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D1, D0, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
UBFM X28, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X20, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D29, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D18, D18, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D2, D7, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D2, [X20, X28]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X28, [X25, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D24, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X28, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D3, D25, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
UBFM X28, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X20, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D29, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D18, D18, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D4, D5, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D4, [X20, X28]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X28, [X25, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D16, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X28, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D31, D6, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
UBFM X28, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X20, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D29, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D18, D18, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D19, D17, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D19, [X20, X28]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459194 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X26, X22, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X24, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X22, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X9, X24, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X17, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [X17, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 458a68 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x75c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X13, X28, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X6, X13, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45925c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459224 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4591f4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xee8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X13, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D23, D20, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
UBFM X6, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D26, [X19, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D29, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D18, D18, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D30, D26, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D30, [X19, X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X17, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D28, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X13, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D0, D31, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
UBFM X6, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X19, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D29, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D18, D18, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D1, D27, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D1, [X19, X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X17, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D2, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X13, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D31, D7, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
UBFM X6, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X19, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D29, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D18, D18, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FADD D24, D25, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D24, [X19, X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X5, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 458a68 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x75c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X26, X23, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X23, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 458a68 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x75c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code