OV - exec - Loop 765

	Loop Id: 765	Module: exec	Source: par_multi_interp.c:550-576 [...]	Coverage: 0.05%

0x45bb64 ADD	X9, X27, X4,LSL #3

0x45bb68 LDR	X5, [X27, X4,LSL #3]

0x45bb6c UBFM	X2, X5, #61, #60

0x45bb70 ADD	X6, X2, #8

0x45bb74 LDR	X0, [X28, X2]

0x45bb78 LDR	X3, [X28, X6]

0x45bb7c CMP	X0, X3

0x45bb80 B.GE	45bcfc

0x45bb84 SUB	X16, X3, X0

0x45bb88 ANDS	X17, X16, #0x7

0x45bb8c B.EQ	45bc54

0x45bb90 CMP	X17, #1

0x45bb94 B.EQ	45bc38

0x45bb98 CMP	X17, #2

0x45bb9c B.EQ	45bc24

0x45bba0 CMP	X17, #3

0x45bba4 B.EQ	45bc10

0x45bba8 CMP	X17, #4

0x45bbac B.EQ	45bbfc

0x45bbb0 CMP	X17, #5

0x45bbb4 B.EQ	45bbe8

0x45bbb8 CMP	X17, #6

0x45bbbc B.EQ	45bbd4

0x45bbc0 LDR	X18, [X20, X0,LSL #3]

0x45bbc4 ADD	X0, X0, #1

0x45bbc8 LDR	X1, [X22, X18,LSL #3]

0x45bbcc CMP	X1, X19

0x45bbd0 B.EQ	45c0c8

0x45bbd4 LDR	X13, [X20, X0,LSL #3]

0x45bbd8 ADD	X0, X0, #1

0x45bbdc LDR	X14, [X22, X13,LSL #3]

0x45bbe0 CMP	X14, X19

0x45bbe4 B.EQ	45c0c8

0x45bbe8 LDR	X12, [X20, X0,LSL #3]

0x45bbec ADD	X0, X0, #1

0x45bbf0 LDR	X10, [X22, X12,LSL #3]

0x45bbf4 CMP	X10, X19

0x45bbf8 B.EQ	45c0c8

0x45bbfc LDR	X15, [X20, X0,LSL #3]

0x45bc00 ADD	X0, X0, #1

0x45bc04 LDR	X16, [X22, X15,LSL #3]

0x45bc08 CMP	X16, X19

0x45bc0c B.EQ	45c0c8

0x45bc10 LDR	X17, [X20, X0,LSL #3]

0x45bc14 ADD	X0, X0, #1

0x45bc18 LDR	X18, [X22, X17,LSL #3]

0x45bc1c CMP	X18, X19

0x45bc20 B.EQ	45c0c8

0x45bc24 LDR	X1, [X20, X0,LSL #3]

0x45bc28 ADD	X0, X0, #1

0x45bc2c LDR	X13, [X22, X1,LSL #3]

0x45bc30 CMP	X13, X19

0x45bc34 B.EQ	45c0c8

0x45bc38 LDR	X14, [X20, X0,LSL #3]

0x45bc3c LDR	X12, [X22, X14,LSL #3]

0x45bc40 CMP	X12, X19

0x45bc44 B.EQ	45c0c8

0x45bc48 ADD	X0, X0, #1

0x45bc4c CMP	X0, X3

0x45bc50 B.EQ	45bcfc

  (767) 0x45bc54 LDR	X18, [X20, X0,LSL #3]

  (767) 0x45bc58 ADD	X10, X0, #1

  (767) 0x45bc5c ADD	X16, X0, #3

  (767) 0x45bc60 ADD	X15, X0, #4

  (767) 0x45bc64 ADD	X14, X0, #5

  (767) 0x45bc68 ADD	X13, X0, #6

  (767) 0x45bc6c ADD	X17, X0, #7

  (767) 0x45bc70 ADD	X12, X10, #1

  (767) 0x45bc74 ADD	X0, X0, #8

  (767) 0x45bc78 LDR	X1, [X22, X18,LSL #3]

  (767) 0x45bc7c CMP	X1, X19

  (767) 0x45bc80 B.EQ	45c0c8

  (767) 0x45bc84 LDR	X10, [X20, X10,LSL #3]

  (767) 0x45bc88 LDR	X18, [X22, X10,LSL #3]

  (767) 0x45bc8c CMP	X18, X19

  (767) 0x45bc90 B.EQ	45c0c8

  (767) 0x45bc94 LDR	X12, [X20, X12,LSL #3]

  (767) 0x45bc98 LDR	X1, [X22, X12,LSL #3]

  (767) 0x45bc9c CMP	X1, X19

  (767) 0x45bca0 B.EQ	45c0c8

  (767) 0x45bca4 LDR	X16, [X20, X16,LSL #3]

  (767) 0x45bca8 LDR	X10, [X22, X16,LSL #3]

  (767) 0x45bcac CMP	X10, X19

  (767) 0x45bcb0 B.EQ	45c0c8

  (767) 0x45bcb4 LDR	X15, [X20, X15,LSL #3]

  (767) 0x45bcb8 LDR	X18, [X22, X15,LSL #3]

  (767) 0x45bcbc CMP	X18, X19

  (767) 0x45bcc0 B.EQ	45c0c8

  (767) 0x45bcc4 LDR	X14, [X20, X14,LSL #3]

  (767) 0x45bcc8 LDR	X12, [X22, X14,LSL #3]

  (767) 0x45bccc CMP	X12, X19

  (767) 0x45bcd0 B.EQ	45c0c8

  (767) 0x45bcd4 LDR	X13, [X20, X13,LSL #3]

  (767) 0x45bcd8 LDR	X1, [X22, X13,LSL #3]

  (767) 0x45bcdc CMP	X1, X19

  (767) 0x45bce0 B.EQ	45c0c8

  (767) 0x45bce4 LDR	X17, [X20, X17,LSL #3]

  (767) 0x45bce8 LDR	X16, [X22, X17,LSL #3]

  (767) 0x45bcec CMP	X16, X19

  (767) 0x45bcf0 B.EQ	45c0c8

  (767) 0x45bcf4 CMP	X0, X3

  (767) 0x45bcf8 B.NE	45bc54

0x45bcfc LDR	X3, [X8, X6]

0x45bd00 LDR	X0, [X8, X2]

0x45bd04 CMP	X0, X3

0x45bd08 B.GE	45be84

0x45bd0c SUB	X6, X3, X0

0x45bd10 ANDS	X10, X6, #0x7

0x45bd14 B.EQ	45bddc

0x45bd18 CMP	X10, #1

0x45bd1c B.EQ	45bdc0

0x45bd20 CMP	X10, #2

0x45bd24 B.EQ	45bdac

0x45bd28 CMP	X10, #3

0x45bd2c B.EQ	45bd98

0x45bd30 CMP	X10, #4

0x45bd34 B.EQ	45bd84

0x45bd38 CMP	X10, #5

0x45bd3c B.EQ	45bd70

0x45bd40 CMP	X10, #6

0x45bd44 B.EQ	45bd5c

0x45bd48 LDR	X15, [X21, X0,LSL #3]

0x45bd4c ADD	X0, X0, #1

0x45bd50 LDR	X18, [X26, X15,LSL #3]

0x45bd54 CMP	X18, X19

0x45bd58 B.EQ	45c0c8

0x45bd5c LDR	X14, [X21, X0,LSL #3]

0x45bd60 ADD	X0, X0, #1

0x45bd64 LDR	X12, [X26, X14,LSL #3]

0x45bd68 CMP	X12, X19

0x45bd6c B.EQ	45c0c8

0x45bd70 LDR	X13, [X21, X0,LSL #3]

0x45bd74 ADD	X0, X0, #1

0x45bd78 LDR	X1, [X26, X13,LSL #3]

0x45bd7c CMP	X1, X19

0x45bd80 B.EQ	45c0c8

0x45bd84 LDR	X17, [X21, X0,LSL #3]

0x45bd88 ADD	X0, X0, #1

0x45bd8c LDR	X16, [X26, X17,LSL #3]

0x45bd90 CMP	X16, X19

0x45bd94 B.EQ	45c0c8

0x45bd98 LDR	X6, [X21, X0,LSL #3]

0x45bd9c ADD	X0, X0, #1

0x45bda0 LDR	X10, [X26, X6,LSL #3]

0x45bda4 CMP	X10, X19

0x45bda8 B.EQ	45c0c8

0x45bdac LDR	X15, [X21, X0,LSL #3]

0x45bdb0 ADD	X0, X0, #1

0x45bdb4 LDR	X18, [X26, X15,LSL #3]

0x45bdb8 CMP	X18, X19

0x45bdbc B.EQ	45c0c8

0x45bdc0 LDR	X14, [X21, X0,LSL #3]

0x45bdc4 LDR	X12, [X26, X14,LSL #3]

0x45bdc8 CMP	X12, X19

0x45bdcc B.EQ	45c0c8

0x45bdd0 ADD	X0, X0, #1

0x45bdd4 CMP	X0, X3

0x45bdd8 B.EQ	45be84

  (766) 0x45bddc LDR	X17, [X21, X0,LSL #3]

  (766) 0x45bde0 ADD	X1, X0, #1

  (766) 0x45bde4 ADD	X10, X0, #3

  (766) 0x45bde8 ADD	X15, X0, #4

  (766) 0x45bdec ADD	X18, X0, #5

  (766) 0x45bdf0 ADD	X6, X0, #6

  (766) 0x45bdf4 ADD	X13, X0, #7

  (766) 0x45bdf8 ADD	X16, X1, #1

  (766) 0x45bdfc ADD	X0, X0, #8

  (766) 0x45be00 LDR	X14, [X26, X17,LSL #3]

  (766) 0x45be04 CMP	X14, X19

  (766) 0x45be08 B.EQ	45c0c8

  (766) 0x45be0c LDR	X12, [X21, X1,LSL #3]

  (766) 0x45be10 LDR	X1, [X26, X12,LSL #3]

  (766) 0x45be14 CMP	X1, X19

  (766) 0x45be18 B.EQ	45c0c8

  (766) 0x45be1c LDR	X17, [X21, X16,LSL #3]

  (766) 0x45be20 LDR	X16, [X26, X17,LSL #3]

  (766) 0x45be24 CMP	X16, X19

  (766) 0x45be28 B.EQ	45c0c8

  (766) 0x45be2c LDR	X10, [X21, X10,LSL #3]

  (766) 0x45be30 LDR	X14, [X26, X10,LSL #3]

  (766) 0x45be34 CMP	X14, X19

  (766) 0x45be38 B.EQ	45c0c8

  (766) 0x45be3c LDR	X15, [X21, X15,LSL #3]

  (766) 0x45be40 LDR	X12, [X26, X15,LSL #3]

  (766) 0x45be44 CMP	X12, X19

  (766) 0x45be48 B.EQ	45c0c8

  (766) 0x45be4c LDR	X18, [X21, X18,LSL #3]

  (766) 0x45be50 LDR	X1, [X26, X18,LSL #3]

  (766) 0x45be54 CMP	X1, X19

  (766) 0x45be58 B.EQ	45c0c8

  (766) 0x45be5c LDR	X6, [X21, X6,LSL #3]

  (766) 0x45be60 LDR	X17, [X26, X6,LSL #3]

  (766) 0x45be64 CMP	X17, X19

  (766) 0x45be68 B.EQ	45c0c8

  (766) 0x45be6c LDR	X13, [X21, X13,LSL #3]

  (766) 0x45be70 LDR	X16, [X26, X13,LSL #3]

  (766) 0x45be74 CMP	X16, X19

  (766) 0x45be78 B.EQ	45c0c8

  (766) 0x45be7c CMP	X0, X3

  (766) 0x45be80 B.NE	45bddc

0x45be84 SUB	X4, X4, #1

0x45be88 CMP	X23, X4

0x45be8c B.LE	45bb64

0x45c0c8 UBFM	X3, X23, #61, #60

0x45c0cc ADD	X23, X23, #1

0x45c0d0 LDR	X0, [X27, X3]

0x45c0d4 STR	X0, [X9]

0x45c0d8 STR	X5, [X27, X3]

0x45c0dc STR	X7, [X22, X2]

0x45c0e0 B	45be88

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 550 - 576

--------------------------------------------------------------------------------

550:       for (i = pass_array_size-1; i > cnt-1; i--)

551:       {

552:          i1 = pass_array[i];

553:          no_break = 1;

554:          for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

555:          {

556:             j1 = S_diag_j[j];

557:             if (assigned[j1] == pass-1)

[...]

568:             for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

569:             {

570:                j1 = S_offd_j[j];

571:                if (assigned_offd[j1] == pass-1)

572:                {

573:                   pass_array[i++] = pass_array[cnt];

574:                   pass_array[cnt++] = i1;

575:                   assigned[i1] = pass;

576:                   break;

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:550-554,par_multi_interp.c:557-557,par_multi_interp.c:568-568,par_multi_interp.c:571-576
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	4.25
Front-end cycles	15.75
P0 cycles	17.00
P1 cycles	17.00
P2 cycles	13.75
P3 cycles	13.75
P4 cycles	13.75
P5 cycles	13.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	12.50
P11 cycles	12.17
P12 cycles	12.33
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	126.00
Nb uops	126.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:550-554,par_multi_interp.c:557-557,par_multi_interp.c:568-568,par_multi_interp.c:571-576
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	4.25
Front-end cycles	15.75
P0 cycles	17.00
P1 cycles	17.00
P2 cycles	13.75
P3 cycles	13.75
P4 cycles	13.75
P5 cycles	13.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	12.50
P11 cycles	12.17
P12 cycles	12.33
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	126.00
Nb uops	126.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:550-576
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:550-557,568-576.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:550-554,557,568,571-576.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 1820 paths individually, rerun with max-paths=1820
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 1820 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 17.00 to 4.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	126
nb uops	126
loop length	504
used w registers	0
used x registers	26
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.75 cycles
front end	15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	17.00	17.00	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	12.50	12.17	12.33	1.50	1.50
cycles	17.00	17.00	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	12.50	12.17	12.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.75
Dispatch	17.00
Overall L1	17.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45bb64

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X9, X27, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X5, [X27, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X2, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X6, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [X28, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X28, X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45bcfc <hypre_BoomerAMGBuildMultipass+0xf3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X16, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X17, X16, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 45bc54 <hypre_BoomerAMGBuildMultipass+0xe94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bc38 <hypre_BoomerAMGBuildMultipass+0xe78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bc24 <hypre_BoomerAMGBuildMultipass+0xe64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bc10 <hypre_BoomerAMGBuildMultipass+0xe50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bbfc <hypre_BoomerAMGBuildMultipass+0xe3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bbe8 <hypre_BoomerAMGBuildMultipass+0xe28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bbd4 <hypre_BoomerAMGBuildMultipass+0xe14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X1, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X10, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X10, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bcfc <hypre_BoomerAMGBuildMultipass+0xf3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X8, X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45be84 <hypre_BoomerAMGBuildMultipass+0x10c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X6, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X10, X6, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bddc <hypre_BoomerAMGBuildMultipass+0x101c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bdc0 <hypre_BoomerAMGBuildMultipass+0x1000>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bdac <hypre_BoomerAMGBuildMultipass+0xfec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bd98 <hypre_BoomerAMGBuildMultipass+0xfd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bd84 <hypre_BoomerAMGBuildMultipass+0xfc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bd70 <hypre_BoomerAMGBuildMultipass+0xfb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bd5c <hypre_BoomerAMGBuildMultipass+0xf9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X26, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X1, [X26, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X26, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X10, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X10, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X26, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45be84 <hypre_BoomerAMGBuildMultipass+0x10c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X23, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45bb64 <hypre_BoomerAMGBuildMultipass+0xda4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [X27, X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [X27, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [X22, X2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45be88 <hypre_BoomerAMGBuildMultipass+0x10c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:550-576
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 1820 paths individually, rerun with max-paths=1820
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	126
nb uops	126
loop length	504
used w registers	0
used x registers	26
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.75 cycles
front end	15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	17.00	17.00	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	12.50	12.17	12.33	1.50	1.50
cycles	17.00	17.00	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	12.50	12.17	12.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.75
Dispatch	17.00
Overall L1	17.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45bb64

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X9, X27, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X5, [X27, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X2, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X6, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [X28, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X28, X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45bcfc <hypre_BoomerAMGBuildMultipass+0xf3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X16, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X17, X16, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 45bc54 <hypre_BoomerAMGBuildMultipass+0xe94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bc38 <hypre_BoomerAMGBuildMultipass+0xe78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bc24 <hypre_BoomerAMGBuildMultipass+0xe64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bc10 <hypre_BoomerAMGBuildMultipass+0xe50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bbfc <hypre_BoomerAMGBuildMultipass+0xe3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bbe8 <hypre_BoomerAMGBuildMultipass+0xe28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bbd4 <hypre_BoomerAMGBuildMultipass+0xe14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X1, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X10, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X10, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bcfc <hypre_BoomerAMGBuildMultipass+0xf3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X8, X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45be84 <hypre_BoomerAMGBuildMultipass+0x10c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X6, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X10, X6, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bddc <hypre_BoomerAMGBuildMultipass+0x101c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bdc0 <hypre_BoomerAMGBuildMultipass+0x1000>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bdac <hypre_BoomerAMGBuildMultipass+0xfec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bd98 <hypre_BoomerAMGBuildMultipass+0xfd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bd84 <hypre_BoomerAMGBuildMultipass+0xfc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bd70 <hypre_BoomerAMGBuildMultipass+0xfb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45bd5c <hypre_BoomerAMGBuildMultipass+0xf9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X26, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X1, [X26, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X26, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X10, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X10, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X26, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c0c8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45be84 <hypre_BoomerAMGBuildMultipass+0x10c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X23, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45bb64 <hypre_BoomerAMGBuildMultipass+0xda4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [X27, X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [X27, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [X22, X2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45be88 <hypre_BoomerAMGBuildMultipass+0x10c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code