OV - exec - Loop 789

	Loop Id: 789	Module: exec	Source: par_lr_interp.c:1609-1723 [...]	Coverage: 0.06%

0x4606e8 UBFM	X8, X15, #61, #60

0x4606ec LDR	D13, [X26, X2,LSL #3]

0x4606f0 LDR	D31, [X0, X8]

0x4606f4 FADD	D18, D31, D13

0x4606f8 STR	D18, [X0, X8]

0x4606fc ADD	X2, X2, #1

0x460700 CMP	X2, X9

0x460704 B.EQ	460760

0x460708 LDR	X8, [X5, X2,LSL #3]

0x46070c UBFM	X3, X8, #61, #60

0x460710 LDR	X15, [X19, X3]

0x460714 CMP	X1, X15

0x460718 B.LE	4606e8

0x46071c CMP	X15, X30

0x460720 B.EQ	460c7c

0x460724 LDR	X12, [X20, X3]

0x460728 CMN	X12, #3

0x46072c B.EQ	4606fc

0x460730 LDR	X13, [SP, #152]

0x460734 CMP	X13, #1

0x460738 B.EQ	46074c

0x46073c LDR	X16, [X4, X3]

0x460740 LDR	X25, [X4, X21,LSL #3]

0x460744 CMP	X25, X16

0x460748 B.NE	4606fc

0x46074c LDR	D27, [X26, X2,LSL #3]

0x460750 ADD	X2, X2, #1

0x460754 FADD	D29, D29, D27

0x460758 CMP	X2, X9

0x46075c B.NE	460708

0x460c7c LDR	X10, [SP, #192]

0x460c80 ADD	X14, X3, #8

0x460c84 FMOV	D31, D15

0x460c88 STR	X14, [SP, #296]

0x460c8c LDR	X6, [X10, X3]

0x460c90 LDR	X12, [X10, X14]

0x460c94 LDR	D28, [X26, X6,LSL #3]

0x460c98 ADD	X6, X6, #1

0x460c9c ORR	X8, XZR, X6

0x460ca0 FCMPE	D28, #0

0x460ca4 FCSEL	D13, D0, D26, #4

0x460ca8 CMP	X6, X12

0x460cac B.GE	4623f8

0x460cb0 SUB	X15, X12, X6

0x460cb4 ANDS	X13, X15, #0x3

0x460cb8 B.EQ	460d4c

0x460cbc CMP	X13, #1

0x460cc0 B.EQ	460d1c

0x460cc4 CMP	X13, #2

0x460cc8 B.EQ	460cf4

0x460ccc LDR	X16, [X5, X6,LSL #3]

0x460cd0 LDR	X25, [X19, X16,LSL #3]

0x460cd4 CMP	X1, X25

0x460cd8 CCMP	X21, X16, #4, #12

0x460cdc B.NE	460cf0

0x460ce0 LDR	D1, [X26, X6,LSL #3]

0x460ce4 FMUL	D30, D1, D13

0x460ce8 FCMPE	D30, #0

0x460cec B.MI	462284

0x460cf0 ADD	X8, X6, #1

0x460cf4 LDR	X14, [X5, X8,LSL #3]

0x460cf8 LDR	X10, [X19, X14,LSL #3]

0x460cfc CMP	X1, X10

0x460d00 CCMP	X21, X14, #4, #12

0x460d04 B.NE	460d18

0x460d08 LDR	D2, [X26, X8,LSL #3]

0x460d0c FMUL	D3, D2, D13

0x460d10 FCMPE	D3, #0

0x460d14 B.MI	4620a8

0x460d18 ADD	X8, X8, #1

0x460d1c LDR	X15, [X5, X8,LSL #3]

0x460d20 LDR	X13, [X19, X15,LSL #3]

0x460d24 CMP	X1, X13

0x460d28 CCMP	X21, X15, #4, #12

0x460d2c B.NE	460d40

0x460d30 LDR	D5, [X26, X8,LSL #3]

0x460d34 FMUL	D6, D5, D13

0x460d38 FCMPE	D6, #0

0x460d3c B.MI	461c48

0x460d40 ADD	X8, X8, #1

0x460d44 CMP	X12, X8

0x460d48 B.EQ	460df4

  (793) 0x460d4c LDR	X16, [X5, X8,LSL #3]

  (793) 0x460d50 LDR	X25, [X19, X16,LSL #3]

  (793) 0x460d54 CMP	X1, X25

  (793) 0x460d58 CCMP	X21, X16, #4, #12

  (793) 0x460d5c B.NE	460d70

  (793) 0x460d60 LDR	D7, [X26, X8,LSL #3]

  (793) 0x460d64 FMUL	D16, D7, D13

  (793) 0x460d68 FCMPE	D16, #0

  (793) 0x460d6c B.MI	461660

  (793) 0x460d70 ADD	X8, X8, #1

  (793) 0x460d74 LDR	X14, [X5, X8,LSL #3]

  (793) 0x460d78 LDR	X10, [X19, X14,LSL #3]

  (793) 0x460d7c CMP	X1, X10

  (793) 0x460d80 CCMP	X21, X14, #4, #12

  (793) 0x460d84 B.NE	460d98

  (793) 0x460d88 LDR	D17, [X26, X8,LSL #3]

  (793) 0x460d8c FMUL	D18, D17, D13

  (793) 0x460d90 FCMPE	D18, #0

  (793) 0x460d94 B.MI	461670

  (793) 0x460d98 ADD	X15, X8, #1

  (793) 0x460d9c LDR	X13, [X5, X15,LSL #3]

  (793) 0x460da0 LDR	X16, [X19, X13,LSL #3]

  (793) 0x460da4 CMP	X1, X16

  (793) 0x460da8 CCMP	X21, X13, #4, #12

  (793) 0x460dac B.NE	460dc0

  (793) 0x460db0 LDR	D19, [X26, X15,LSL #3]

  (793) 0x460db4 FMUL	D20, D19, D13

  (793) 0x460db8 FCMPE	D20, #0

  (793) 0x460dbc B.MI	461668

  (793) 0x460dc0 ADD	X25, X8, #2

  (793) 0x460dc4 LDR	X10, [X5, X25,LSL #3]

  (793) 0x460dc8 LDR	X14, [X19, X10,LSL #3]

  (793) 0x460dcc CMP	X1, X14

  (793) 0x460dd0 CCMP	X21, X10, #4, #12

  (793) 0x460dd4 B.NE	460de8

  (793) 0x460dd8 LDR	D21, [X26, X25,LSL #3]

  (793) 0x460ddc FMUL	D22, D21, D13

  (793) 0x460de0 FCMPE	D22, #0

  (793) 0x460de4 B.MI	461678

  (793) 0x460de8 ADD	X8, X8, #3

  (793) 0x460dec CMP	X12, X8

  (793) 0x460df0 B.NE	460d4c

0x460df4 LDR	X15, [SP, #136]

0x460df8 LDR	D4, [X26, X2,LSL #3]

0x460dfc CMP	X15, #1

0x460e00 B.GT	461a30

0x460e04 FCMP	D31, #0

0x460e08 B.NE	461c5c

0x460e0c FADD	D29, D29, D4

0x460e10 B	4606fc

  (793) 0x461660 FADD	D31, D31, D7

  (793) 0x461664 B	460d70

  (793) 0x461668 FADD	D31, D31, D19

  (793) 0x46166c B	460dc0

  (793) 0x461670 FADD	D31, D31, D17

  (793) 0x461674 B	460d98

  (793) 0x461678 FADD	D31, D31, D21

  (793) 0x46167c B	460de8

0x461a30 LDR	X13, [SP, #296]

0x461a34 LDR	X16, [SP, #336]

0x461a38 LDR	X10, [X16, X13]

0x461a3c LDR	X14, [X16, X3]

0x461a40 STR	X10, [SP, #304]

0x461a44 CMP	X14, X10

0x461a48 B.GE	4628bc

0x461a4c SUB	X13, X10, X14

0x461a50 LDR	X10, [SP, #328]

0x461a54 ADD	X25, X17, X14,LSL #3

0x461a58 MOVZ	X8, #0

0x461a5c CNTD	X16, ALL

0x461a60 DUP	Z23.D, X7

0x461a64 CNTB	X15, ALL

0x461a68 WHILELO	P5.D, XZR, X13

0x461a6c DUP	Z24.D, Z13.D[0]

0x461a70 ADD	X10, X10, X14,LSL #3

0x461a74 HINT	#0

0x461a78 HINT	#0

0x461a7c HINT	#0

  (792) 0x461a80 LD1D	{Z25.D}, P5/Z, [X25, X8,LSL #3]

  (792) 0x461a84 LD1D	{Z27.D}, P5/Z, [X24, Z25.D,LSL #3]

  (792) 0x461a88 CMPGE	P4.D, P5/Z, Z27.D, Z23.D

  (792) 0x461a8c ADD	X8, X8, X16

  (792) 0x461a90 LD1D	{Z28.D}, P4/Z, [X10, MUL VL]

  (792) 0x461a94 WHILELO	P5.D, X8, X13

  (792) 0x461a98 MOVPRFX	Z1, Z28

  (792) 0x461a9c FMUL	Z1.D, P4/M, Z1.D, Z24.D

  (792) 0x461aa0 ADD	X10, X10, X15

  (792) 0x461aa4 FCMLT	P6.D, P4/Z, Z1.D, #0.0000000

  (792) 0x461aa8 FADDA	D31, P6, D31, Z28.D

  (792) 0x461aac B.NE	461a80

0x461ab0 FCMP	D31, #0

0x461ab4 B.EQ	460e0c

0x461ab8 FDIV	D31, D4, D31

0x461abc CMP	X6, X12

0x461ac0 B.LT	461c60

0x461ac4 LDR	X15, [SP, #304]

0x461ac8 B	461d40

0x461c48 ADD	X8, X8, #1

0x461c4c FADD	D31, D31, D5

0x461c50 CMP	X12, X8

0x461c54 B.NE	460d4c

0x461c58 B	460df4

0x461c5c FDIV	D31, D4, D31

0x461c60 LDR	X14, [X5, X6,LSL #3]

0x461c64 ORN	X25, XZR, X6

0x461c68 ADD	X16, X25, X12

0x461c6c AND	X15, X16, #0x3

0x461c70 LDR	X13, [X19, X14,LSL #3]

0x461c74 CMP	X1, X13

0x461c78 B.GT	462368

0x461c7c LDR	D30, [X26, X6,LSL #3]

0x461c80 FMUL	D2, D30, D13

0x461c84 FCMPE	D2, #0

0x461c88 B.MI	462358

0x461c8c ADD	X6, X6, #1

0x461c90 CMP	X12, X6

0x461c94 B.LE	461d20

0x461c98 CBZ	X15, 462044

0x461c9c CMP	X15, #1

0x461ca0 B.EQ	461cf4

0x461ca4 CMP	X15, #2

0x461ca8 B.EQ	461cd0

0x461cac LDR	X10, [X5, X6,LSL #3]

0x461cb0 LDR	X14, [X19, X10,LSL #3]

0x461cb4 CMP	X1, X14

0x461cb8 B.GT	46280c

0x461cbc LDR	D16, [X26, X6,LSL #3]

0x461cc0 FMUL	D17, D16, D13

0x461cc4 FCMPE	D17, #0

0x461cc8 B.MI	4627fc

0x461ccc ADD	X6, X6, #1

0x461cd0 LDR	X16, [X5, X6,LSL #3]

0x461cd4 LDR	X15, [X19, X16,LSL #3]

0x461cd8 CMP	X1, X15

0x461cdc B.GT	4622a0

0x461ce0 LDR	D22, [X26, X6,LSL #3]

0x461ce4 FMUL	D4, D22, D13

0x461ce8 FCMPE	D4, #0

0x461cec B.MI	462290

0x461cf0 ADD	X6, X6, #1

0x461cf4 LDR	X8, [X5, X6,LSL #3]

0x461cf8 LDR	X10, [X19, X8,LSL #3]

0x461cfc CMP	X1, X10

0x461d00 B.GT	4623dc

0x461d04 LDR	D28, [X26, X6,LSL #3]

0x461d08 FMUL	D1, D28, D13

0x461d0c FCMPE	D1, #0

0x461d10 B.MI	4623cc

0x461d14 ADD	X6, X6, #1

0x461d18 CMP	X12, X6

0x461d1c B.GT	462044

0x461d20 LDR	X12, [SP, #136]

0x461d24 CMP	X12, #1

0x461d28 B.LE	4606fc

0x461d2c LDR	X16, [SP, #296]

0x461d30 LDR	X25, [SP, #336]

0x461d34 LDR	X15, [X25, X16]

0x461d38 LDR	X14, [X25, X3]

0x461d3c STR	X15, [SP, #304]

0x461d40 CMP	X14, X15

0x461d44 B.GE	4606fc

0x461d48 LDR	X10, [SP, #168]

0x461d4c SUB	X8, X15, X14

0x461d50 ANDS	X13, X8, #0x7

0x461d54 LDR	X8, [X10, #200]

0x461d58 B.EQ	462958

0x461d5c CMP	X13, #1

0x461d60 B.EQ	461e68

0x461d64 CMP	X13, #2

0x461d68 B.EQ	461e54

0x461d6c CMP	X13, #3

0x461d70 B.EQ	461e2c

0x461d74 CMP	X13, #4

0x461d78 B.EQ	461e04

0x461d7c CMP	X13, #5

0x461d80 B.EQ	461ddc

0x461d84 CMP	X13, #6

0x461d88 B.EQ	461db4

0x461d8c LDR	X6, [X17, X14,LSL #3]

0x461d90 LDR	X12, [X24, X6,LSL #3]

0x461d94 CMP	X7, X12

0x461d98 B.GT	461db0

0x461d9c LDR	X25, [SP, #328]

0x461da0 LDR	D18, [X25, X14,LSL #3]

0x461da4 FMUL	D19, D18, D13

0x461da8 FCMPE	D19, #0

0x461dac B.MI	4628a8

0x461db0 ADD	X14, X14, #1

0x461db4 LDR	X16, [X17, X14,LSL #3]

0x461db8 LDR	X15, [X24, X16,LSL #3]

0x461dbc CMP	X7, X15

0x461dc0 B.GT	461dd8

0x461dc4 LDR	X13, [SP, #328]

0x461dc8 LDR	D22, [X13, X14,LSL #3]

0x461dcc FMUL	D4, D22, D13

0x461dd0 FCMPE	D4, #0

0x461dd4 B.MI	462888

0x461dd8 ADD	X14, X14, #1

0x461ddc LDR	X6, [X17, X14,LSL #3]

0x461de0 LDR	X12, [X24, X6,LSL #3]

0x461de4 CMP	X7, X12

0x461de8 B.GT	461e00

0x461dec LDR	X25, [SP, #328]

0x461df0 LDR	D25, [X25, X14,LSL #3]

0x461df4 FMUL	D27, D25, D13

0x461df8 FCMPE	D27, #0

0x461dfc B.MI	462874

0x461e00 ADD	X14, X14, #1

0x461e04 LDR	X16, [X17, X14,LSL #3]

0x461e08 LDR	X15, [X24, X16,LSL #3]

0x461e0c CMP	X7, X15

0x461e10 B.GT	461e28

0x461e14 LDR	X13, [SP, #328]

0x461e18 LDR	D2, [X13, X14,LSL #3]

0x461e1c FMUL	D30, D2, D13

0x461e20 FCMPE	D30, #0

0x461e24 B.MI	462860

0x461e28 ADD	X14, X14, #1

0x461e2c LDR	X6, [X17, X14,LSL #3]

0x461e30 LDR	X12, [X24, X6,LSL #3]

0x461e34 CMP	X7, X12

0x461e38 B.GT	461e50

0x461e3c LDR	X25, [SP, #328]

0x461e40 LDR	D6, [X25, X14,LSL #3]

0x461e44 FMUL	D7, D6, D13

0x461e48 FCMPE	D7, #0

0x461e4c B.MI	462848

0x461e50 ADD	X14, X14, #1

0x461e54 LDR	X16, [X17, X14,LSL #3]

0x461e58 LDR	X15, [X24, X16,LSL #3]

0x461e5c CMP	X7, X15

0x461e60 B.LE	4626cc

0x461e64 ADD	X14, X14, #1

0x461e68 LDR	X6, [X17, X14,LSL #3]

0x461e6c LDR	X12, [X24, X6,LSL #3]

0x461e70 CMP	X7, X12

0x461e74 B.LE	462678

0x461e78 LDR	X16, [SP, #304]

0x461e7c ADD	X14, X14, #1

0x461e80 CMP	X14, X16

0x461e84 B.EQ	4606fc

0x461e88 LDR	X6, [SP, #328]

0x461e8c ORR	X15, XZR, X16

  (790) 0x461e90 LDR	X13, [X17, X14,LSL #3]

  (790) 0x461e94 LDR	X10, [X24, X13,LSL #3]

  (790) 0x461e98 CMP	X7, X10

  (790) 0x461e9c B.GT	461eb0

  (790) 0x461ea0 LDR	D25, [X6, X14,LSL #3]

  (790) 0x461ea4 FMUL	D27, D25, D13

  (790) 0x461ea8 FCMPE	D27, #0

  (790) 0x461eac B.MI	462768

  (790) 0x461eb0 ADD	X14, X14, #1

  (790) 0x461eb4 LDR	X25, [X17, X14,LSL #3]

  (790) 0x461eb8 LDR	X3, [X24, X25,LSL #3]

  (790) 0x461ebc CMP	X7, X3

  (790) 0x461ec0 B.GT	461ed4

  (790) 0x461ec4 LDR	D2, [X6, X14,LSL #3]

  (790) 0x461ec8 FMUL	D30, D2, D13

  (790) 0x461ecc FCMPE	D30, #0

  (790) 0x461ed0 B.MI	46277c

  (790) 0x461ed4 ADD	X13, X14, #1

  (790) 0x461ed8 LDR	X10, [X17, X13,LSL #3]

  (790) 0x461edc LDR	X12, [X24, X10,LSL #3]

  (790) 0x461ee0 CMP	X7, X12

  (790) 0x461ee4 B.GT	461ef8

  (790) 0x461ee8 LDR	D6, [X6, X13,LSL #3]

  (790) 0x461eec FMUL	D7, D6, D13

  (790) 0x461ef0 FCMPE	D7, #0

  (790) 0x461ef4 B.MI	4627b8

  (790) 0x461ef8 ADD	X3, X14, #2

  (790) 0x461efc LDR	X16, [X17, X3,LSL #3]

  (790) 0x461f00 LDR	X13, [X24, X16,LSL #3]

  (790) 0x461f04 CMP	X7, X13

  (790) 0x461f08 B.GT	461f1c

  (790) 0x461f0c LDR	D18, [X6, X3,LSL #3]

  (790) 0x461f10 FMUL	D19, D18, D13

  (790) 0x461f14 FCMPE	D19, #0

  (790) 0x461f18 B.MI	462740

  (790) 0x461f1c ADD	X12, X14, #3

  (790) 0x461f20 LDR	X25, [X17, X12,LSL #3]

  (790) 0x461f24 LDR	X3, [X24, X25,LSL #3]

  (790) 0x461f28 CMP	X7, X3

  (790) 0x461f2c B.GT	461f40

  (790) 0x461f30 LDR	D22, [X6, X12,LSL #3]

  (790) 0x461f34 FMUL	D4, D22, D13

  (790) 0x461f38 FCMPE	D4, #0

  (790) 0x461f3c B.MI	462790

  (790) 0x461f40 ADD	X13, X14, #4

  (790) 0x461f44 LDR	X10, [X17, X13,LSL #3]

  (790) 0x461f48 LDR	X12, [X24, X10,LSL #3]

  (790) 0x461f4c CMP	X7, X12

  (790) 0x461f50 B.GT	461f64

  (790) 0x461f54 LDR	D25, [X6, X13,LSL #3]

  (790) 0x461f58 FMUL	D27, D25, D13

  (790) 0x461f5c FCMPE	D27, #0

  (790) 0x461f60 B.MI	46272c

  (790) 0x461f64 ADD	X3, X14, #5

  (790) 0x461f68 LDR	X16, [X17, X3,LSL #3]

  (790) 0x461f6c LDR	X13, [X24, X16,LSL #3]

  (790) 0x461f70 CMP	X7, X13

  (790) 0x461f74 B.GT	461f88

  (790) 0x461f78 LDR	D2, [X6, X3,LSL #3]

  (790) 0x461f7c FMUL	D30, D2, D13

  (790) 0x461f80 FCMPE	D30, #0

  (790) 0x461f84 B.MI	462754

  (790) 0x461f88 ADD	X12, X14, #6

  (790) 0x461f8c LDR	X25, [X17, X12,LSL #3]

  (790) 0x461f90 LDR	X3, [X24, X25,LSL #3]

  (790) 0x461f94 CMP	X7, X3

  (790) 0x461f98 B.GT	461fac

  (790) 0x461f9c LDR	D6, [X6, X12,LSL #3]

  (790) 0x461fa0 FMUL	D7, D6, D13

  (790) 0x461fa4 FCMPE	D7, #0

  (790) 0x461fa8 B.MI	4627a4

  (790) 0x461fac ADD	X14, X14, #7

  (790) 0x461fb0 CMP	X14, X15

  (790) 0x461fb4 B.NE	461e90

0x461fb8 B	4606fc

  (791) 0x461fbc LDR	D6, [X26, X6,LSL #3]

  (791) 0x461fc0 FMUL	D7, D6, D13

  (791) 0x461fc4 FCMPE	D7, #0

  (791) 0x461fc8 B.MI	462418

  (791) 0x461fcc ADD	X6, X6, #1

  (791) 0x461fd0 LDR	X13, [X5, X6,LSL #3]

  (791) 0x461fd4 LDR	X8, [X19, X13,LSL #3]

  (791) 0x461fd8 CMP	X1, X8

  (791) 0x461fdc B.GT	462334

  (791) 0x461fe0 LDR	D20, [X26, X6,LSL #3]

  (791) 0x461fe4 FMUL	D21, D20, D13

  (791) 0x461fe8 FCMPE	D21, #0

  (791) 0x461fec B.MI	462324

  (791) 0x461ff0 ADD	X14, X6, #1

  (791) 0x461ff4 LDR	X25, [X5, X14,LSL #3]

  (791) 0x461ff8 LDR	X16, [X19, X25,LSL #3]

  (791) 0x461ffc CMP	X1, X16

  (791) 0x462000 B.GT	462300

  (791) 0x462004 LDR	D25, [X26, X14,LSL #3]

  (791) 0x462008 FMUL	D27, D25, D13

  (791) 0x46200c FCMPE	D27, #0

  (791) 0x462010 B.MI	4622f0

  (791) 0x462014 ADD	X8, X6, #2

  (791) 0x462018 LDR	X13, [X5, X8,LSL #3]

  (791) 0x46201c LDR	X10, [X19, X13,LSL #3]

  (791) 0x462020 CMP	X1, X10

  (791) 0x462024 B.GT	4622cc

  (791) 0x462028 LDR	D3, [X26, X8,LSL #3]

  (791) 0x46202c FMUL	D5, D3, D13

  (791) 0x462030 FCMPE	D5, #0

  (791) 0x462034 B.MI	4622bc

  (791) 0x462038 ADD	X6, X6, #3

  (791) 0x46203c CMP	X12, X6

  (791) 0x462040 B.LE	461d20

  (791) 0x462044 LDR	X25, [X5, X6,LSL #3]

  (791) 0x462048 LDR	X16, [X19, X25,LSL #3]

  (791) 0x46204c CMP	X1, X16

  (791) 0x462050 B.LE	461fbc

  (791) 0x462054 CMP	X21, X25

  (791) 0x462058 B.NE	461fcc

  (791) 0x46205c LDR	D18, [X26, X6,LSL #3]

  (791) 0x462060 FMUL	D19, D18, D13

  (791) 0x462064 FCMPE	D19, #0

  (791) 0x462068 B.MI	46227c

  (791) 0x46206c B	461fcc

0x4620a8 FADD	D31, D31, D2

0x4620ac ADD	X8, X8, #1

0x4620b0 B	460d1c

  (791) 0x46227c FMADD	D29, D31, D18, D29

  (791) 0x462280 B	461fcc

0x462284 FADD	D31, D15, D1

0x462288 ADD	X8, X6, #1

0x46228c B	460cf4

0x462290 UBFM	X13, X15, #61, #60

0x462294 LDR	D23, [X0, X13]

0x462298 FMADD	D24, D31, D22, D23

0x46229c STR	D24, [X0, X13]

0x4622a0 CMP	X21, X16

0x4622a4 B.NE	461cf0

0x4622a8 LDR	D25, [X26, X6,LSL #3]

0x4622ac FMUL	D27, D25, D13

0x4622b0 FCMPE	D27, #0

0x4622b4 B.MI	4627e0

0x4622b8 B	461cf0

  (791) 0x4622bc UBFM	X14, X10, #61, #60

  (791) 0x4622c0 LDR	D6, [X0, X14]

  (791) 0x4622c4 FMADD	D7, D31, D3, D6

  (791) 0x4622c8 STR	D7, [X0, X14]

  (791) 0x4622cc CMP	X21, X13

  (791) 0x4622d0 B.NE	462038

  (791) 0x4622d4 LDR	D16, [X26, X8,LSL #3]

  (791) 0x4622d8 FMUL	D17, D16, D13

  (791) 0x4622dc FCMPE	D17, #0

  (791) 0x4622e0 B.MI	4622e8

  (791) 0x4622e4 B	462038

  (791) 0x4622e8 FMADD	D29, D31, D16, D29

  (791) 0x4622ec B	462038

  (791) 0x4622f0 UBFM	X15, X16, #61, #60

  (791) 0x4622f4 LDR	D28, [X0, X15]

  (791) 0x4622f8 FMADD	D1, D31, D25, D28

  (791) 0x4622fc STR	D1, [X0, X15]

  (791) 0x462300 CMP	X21, X25

  (791) 0x462304 B.NE	462014

  (791) 0x462308 LDR	D30, [X26, X14,LSL #3]

  (791) 0x46230c FMUL	D2, D30, D13

  (791) 0x462310 FCMPE	D2, #0

  (791) 0x462314 B.MI	46231c

  (791) 0x462318 B	462014

  (791) 0x46231c FMADD	D29, D31, D30, D29

  (791) 0x462320 B	462014

  (791) 0x462324 UBFM	X10, X8, #61, #60

  (791) 0x462328 LDR	D22, [X0, X10]

  (791) 0x46232c FMADD	D4, D31, D20, D22

  (791) 0x462330 STR	D4, [X0, X10]

  (791) 0x462334 CMP	X21, X13

  (791) 0x462338 B.NE	461ff0

  (791) 0x46233c LDR	D23, [X26, X6,LSL #3]

  (791) 0x462340 FMUL	D24, D23, D13

  (791) 0x462344 FCMPE	D24, #0

  (791) 0x462348 B.MI	462350

  (791) 0x46234c B	461ff0

  (791) 0x462350 FMADD	D29, D31, D23, D29

  (791) 0x462354 B	461ff0

0x462358 UBFM	X8, X13, #61, #60

0x46235c LDR	D3, [X0, X8]

0x462360 FMADD	D5, D31, D30, D3

0x462364 STR	D5, [X0, X8]

0x462368 CMP	X21, X14

0x46236c B.NE	461c8c

0x462370 LDR	D6, [X26, X6,LSL #3]

0x462374 FMUL	D7, D6, D13

0x462378 FCMPE	D7, #0

0x46237c B.MI	4626ac

0x462380 B	461c8c

0x4623cc UBFM	X14, X10, #61, #60

0x4623d0 LDR	D30, [X0, X14]

0x4623d4 FMADD	D2, D31, D28, D30

0x4623d8 STR	D2, [X0, X14]

0x4623dc CMP	X21, X8

0x4623e0 B.NE	461d14

0x4623e4 LDR	D3, [X26, X6,LSL #3]

0x4623e8 FMUL	D5, D3, D13

0x4623ec FCMPE	D5, #0

0x4623f0 B.MI	462724

0x4623f4 B	461d14

0x4623f8 LDR	X8, [SP, #136]

0x4623fc LDR	D4, [X26, X2,LSL #3]

0x462400 CMP	X8, #1

0x462404 B.GT	461a30

0x462408 FCMP	D15, #0

0x46240c B.NE	4606fc

0x462410 FADD	D29, D29, D4

0x462414 B	4606fc

  (791) 0x462418 UBFM	X15, X16, #61, #60

  (791) 0x46241c LDR	D16, [X0, X15]

  (791) 0x462420 FMADD	D17, D31, D6, D16

  (791) 0x462424 STR	D17, [X0, X15]

  (791) 0x462428 B	462054

0x462678 LDR	X25, [SP, #328]

0x46267c LDR	D22, [X25, X14,LSL #3]

0x462680 FMUL	D4, D22, D13

0x462684 FCMPE	D4, #0

0x462688 B.MI	4627cc

0x46268c B	461e78

0x4626ac FMADD	D29, D31, D6, D29

0x4626b0 B	461c8c

0x4626cc LDR	X13, [SP, #328]

0x4626d0 LDR	D18, [X13, X14,LSL #3]

0x4626d4 FMUL	D19, D18, D13

0x4626d8 FCMPE	D19, #0

0x4626dc B.MI	4627e8

0x4626e0 B	461e64

0x462724 FMADD	D29, D31, D3, D29

0x462728 B	461d14

  (790) 0x46272c UBFM	X25, X12, #61, #60

  (790) 0x462730 LDR	D28, [X8, X25]

  (790) 0x462734 FMADD	D1, D31, D25, D28

  (790) 0x462738 STR	D1, [X8, X25]

  (790) 0x46273c B	461f64

  (790) 0x462740 UBFM	X10, X13, #61, #60

  (790) 0x462744 LDR	D20, [X8, X10]

  (790) 0x462748 FMADD	D21, D31, D18, D20

  (790) 0x46274c STR	D21, [X8, X10]

  (790) 0x462750 B	461f1c

  (790) 0x462754 UBFM	X10, X13, #61, #60

  (790) 0x462758 LDR	D3, [X8, X10]

  (790) 0x46275c FMADD	D5, D31, D2, D3

  (790) 0x462760 STR	D5, [X8, X10]

  (790) 0x462764 B	461f88

  (790) 0x462768 UBFM	X12, X10, #61, #60

  (790) 0x46276c LDR	D28, [X8, X12]

  (790) 0x462770 FMADD	D1, D31, D25, D28

  (790) 0x462774 STR	D1, [X8, X12]

  (790) 0x462778 B	461eb0

  (790) 0x46277c UBFM	X16, X3, #61, #60

  (790) 0x462780 LDR	D3, [X8, X16]

  (790) 0x462784 FMADD	D5, D31, D2, D3

  (790) 0x462788 STR	D5, [X8, X16]

  (790) 0x46278c B	461ed4

  (790) 0x462790 UBFM	X16, X3, #61, #60

  (790) 0x462794 LDR	D23, [X8, X16]

  (790) 0x462798 FMADD	D24, D31, D22, D23

  (790) 0x46279c STR	D24, [X8, X16]

  (790) 0x4627a0 B	461f40

  (790) 0x4627a4 UBFM	X16, X3, #61, #60

  (790) 0x4627a8 LDR	D16, [X8, X16]

  (790) 0x4627ac FMADD	D17, D31, D6, D16

  (790) 0x4627b0 STR	D17, [X8, X16]

  (790) 0x4627b4 B	461fac

  (790) 0x4627b8 UBFM	X25, X12, #61, #60

  (790) 0x4627bc LDR	D16, [X8, X25]

  (790) 0x4627c0 FMADD	D17, D31, D6, D16

  (790) 0x4627c4 STR	D17, [X8, X25]

  (790) 0x4627c8 B	461ef8

0x4627cc UBFM	X3, X12, #61, #60

0x4627d0 LDR	D23, [X8, X3]

0x4627d4 FMADD	D24, D31, D22, D23

0x4627d8 STR	D24, [X8, X3]

0x4627dc B	461e78

0x4627e0 FMADD	D29, D31, D25, D29

0x4627e4 B	461cf0

0x4627e8 UBFM	X10, X15, #61, #60

0x4627ec LDR	D20, [X8, X10]

0x4627f0 FMADD	D21, D31, D18, D20

0x4627f4 STR	D21, [X8, X10]

0x4627f8 B	461e64

0x4627fc UBFM	X25, X14, #61, #60

0x462800 LDR	D18, [X0, X25]

0x462804 FMADD	D19, D31, D16, D18

0x462808 STR	D19, [X0, X25]

0x46280c CMP	X21, X10

0x462810 B.NE	461ccc

0x462814 LDR	D20, [X26, X6,LSL #3]

0x462818 FMUL	D21, D20, D13

0x46281c FCMPE	D21, #0

0x462820 B.MI	46283c

0x462824 ADD	X6, X6, #1

0x462828 B	461cd0

0x46283c FMADD	D29, D31, D20, D29

0x462840 ADD	X6, X6, #1

0x462844 B	461cd0

0x462848 UBFM	X3, X12, #61, #60

0x46284c ADD	X14, X14, #1

0x462850 LDR	D16, [X8, X3]

0x462854 FMADD	D17, D31, D6, D16

0x462858 STR	D17, [X8, X3]

0x46285c B	461e54

0x462860 UBFM	X10, X15, #61, #60

0x462864 LDR	D3, [X8, X10]

0x462868 FMADD	D5, D31, D2, D3

0x46286c STR	D5, [X8, X10]

0x462870 B	461e28

0x462874 UBFM	X3, X12, #61, #60

0x462878 LDR	D28, [X8, X3]

0x46287c FMADD	D1, D31, D25, D28

0x462880 STR	D1, [X8, X3]

0x462884 B	461e00

0x462888 UBFM	X10, X15, #61, #60

0x46288c LDR	D23, [X8, X10]

0x462890 FMADD	D24, D31, D22, D23

0x462894 STR	D24, [X8, X10]

0x462898 B	461dd8

0x4628a8 UBFM	X3, X12, #61, #60

0x4628ac LDR	D20, [X8, X3]

0x4628b0 FMADD	D21, D31, D18, D20

0x4628b4 STR	D21, [X8, X3]

0x4628b8 B	461db0

0x4628bc FCMP	D31, #0

0x4628c0 B.EQ	460e0c

0x4628c4 FDIV	D31, D4, D31

0x4628c8 CMP	X6, X12

0x4628cc B.LT	461c60

0x4628d0 B	4606fc

0x462958 LDR	X15, [SP, #304]

0x46295c LDR	X6, [SP, #328]

0x462960 B	461e90

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1609 - 1723

--------------------------------------------------------------------------------

1609:            for (jj = A_diag_i[i]+1; jj < A_diag_i[i+1]; jj++)

1610:            { /* i1 is a c-point and strongly influences i, accumulate

1611:               * a_(i,i1) into interpolation weight */

1612:              i1 = A_diag_j[jj];

1613:              if (P_marker[i1] >= jj_begin_row)

1614:              {

1615:                P_diag_data[P_marker[i1]] += A_diag_data[jj];

1616:              }

1617:              else if(P_marker[i1] == strong_f_marker)

1618:              {

1619:                sum = zero;

1620:                sgn = 1;

1621:                if(A_diag_data[A_diag_i[i1]] < 0) sgn = -1;

1622:                /* Loop over row of A for point i1 and calculate the sum

1623:                 * of the connections to c-points that strongly influence i. */

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

1629:                }

1630:                if(num_procs > 1)

1631:                {

1632:                  for(jj1 = A_offd_i[i1]; jj1< A_offd_i[i1+1]; jj1++)

1633:                  {

1634:                    i2 = A_offd_j[jj1];

1635:                    if(P_marker_offd[i2] >= jj_begin_row_offd &&

1636:                       (sgn*A_offd_data[jj1]) < 0)

1637:                       sum += A_offd_data[jj1];

1638:                  }

1639:                }

1640:                if(sum != 0)

1641:                {

1642:                  distribute = A_diag_data[jj]/sum;

1643:                  /* Loop over row of A for point i1 and do the distribution */

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

1652:                  }

1653:                  if(num_procs > 1)

1654:                  {

1655:                    for(jj1 = A_offd_i[i1]; jj1 < A_offd_i[i1+1]; jj1++)

1656:                    {

1657:                      i2 = A_offd_j[jj1];

1658:                      if(P_marker_offd[i2] >= jj_begin_row_offd &&

1659:                                 (sgn*A_offd_data[jj1]) < 0)

1660:                        P_offd_data[P_marker_offd[i2]] +=

[...]

1667:                  diagonal += A_diag_data[jj];

1668:                }

1669:              }

1670:              /* neighbor i1 weakly influences i, accumulate a_(i,i1) into

1671:               * diagonal */

1672:              else if (CF_marker[i1] != -3)

1673:              {

1674:                if(num_functions == 1 || dof_func[i] == dof_func[i1])

1675:                  diagonal += A_diag_data[jj];

[...]

1723:                          P_offd_data[P_marker_offd[loc_col]] += distribute*

Coverage (%)	Name	Source Location	Module
►98.64+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.36+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildExtPIInter[...]	par_lr_interp.c:1196	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:850	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.43
CQA speedup if FP arith vectorized	2.09
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1609-1609,par_lr_interp.c:1613-1621,par_lr_interp.c:1624-1632,par_lr_interp.c:1640-1655,par_lr_interp.c:1658-1660,par_lr_interp.c:1667-1667,par_lr_interp.c:1672-1675,par_lr_interp.c:1723-1723
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	49.50
CQA cycles if no scalar integer	20.33
CQA cycles if FP arith vectorized	23.69
CQA cycles if fully vectorized	49.50
Front-end cycles	48.25
P0 cycles	49.50
P1 cycles	49.50
P2 cycles	26.25
P3 cycles	26.25
P4 cycles	26.25
P5 cycles	26.25
P6 cycles	23.00
P7 cycles	19.50
P8 cycles	19.25
P9 cycles	19.25
P10 cycles	37.83
P11 cycles	37.50
P12 cycles	37.67
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	389.00
Nb uops	386.00
Nb loads	NA
Nb stores	15.00
Nb stack references	26.00
FLOP/cycle	1.17
Nb FLOP add-sub	7.00
Nb FLOP mul	18.00
Nb FLOP fma	15.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.59
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	1.30
Vector-efficiency ratio all	25.44
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.97

Metric	Value
CQA speedup if no scalar integer	2.43
CQA speedup if FP arith vectorized	2.09
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1609-1609,par_lr_interp.c:1613-1621,par_lr_interp.c:1624-1632,par_lr_interp.c:1640-1655,par_lr_interp.c:1658-1660,par_lr_interp.c:1667-1667,par_lr_interp.c:1672-1675,par_lr_interp.c:1723-1723
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	49.50
CQA cycles if no scalar integer	20.33
CQA cycles if FP arith vectorized	23.69
CQA cycles if fully vectorized	49.50
Front-end cycles	48.25
P0 cycles	49.50
P1 cycles	49.50
P2 cycles	26.25
P3 cycles	26.25
P4 cycles	26.25
P5 cycles	26.25
P6 cycles	23.00
P7 cycles	19.50
P8 cycles	19.25
P9 cycles	19.25
P10 cycles	37.83
P11 cycles	37.50
P12 cycles	37.67
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	389.00
Nb uops	386.00
Nb loads	NA
Nb stores	15.00
Nb stack references	26.00
FLOP/cycle	1.17
Nb FLOP add-sub	7.00
Nb FLOP mul	18.00
Nb FLOP fma	15.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.59
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	1.30
Vector-efficiency ratio all	25.44
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.97

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1609-1723
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1609-1660,1667-1675,1723.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1609,1613-1621,1624-1632,1640-1655,1658-1660,1667,1672-1675,1723.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 49.50 to 20.33 cycles (2.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 25% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

FMA

Detected 15 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 58 FP arithmetical operations:

22: addition or subtraction (15 inside FMA instructions)
33: multiply (15 inside FMA instructions)
3: divide

The binary loop does not load or store any data.

General properties

nb instructions	389
nb uops	386
loop length	1556
used w registers	0
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	26
used q registers	0
used v registers	0
used z registers	3
nb stack references	26
ADD-SUB / MUL ratio	0.39

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	48.25 cycles
front end	48.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	49.50	49.50	26.25	26.25	26.25	26.25	23.00	19.50	19.25	19.25	37.83	37.50	37.67	1.50	1.50
cycles	49.50	49.50	26.25	26.25	26.25	26.25	23.00	19.50	19.25	19.25	37.83	37.50	37.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	48.25
Dispatch	49.50
DIV/SQRT	5.25-10.49
Overall L1	49.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	1%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	1%

Vector efficiency ratios

INT

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 49.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 460708

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
UBFM X8, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D13, [X26, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D31, [X0, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D18, D31, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D18, [X0, X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X2, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460760 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X5, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X3, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [X19, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4606e8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460c7c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xf90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X20, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMN X12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 46074c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X4, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X4, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X25, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D27, [X26, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D29, D29, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X2, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 460708 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D31, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X14, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X10, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D28, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FCMPE D28, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D13, D0, D26, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP X6, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4623f8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x270c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X15, X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X13, X15, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 460d4c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1060>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460d1c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1030>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460cf4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1008>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X5, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X16, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 460cf0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1004>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D30, D1, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D30, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462284 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2598>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X5, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X14, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 460d18 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x102c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D2, [X26, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D3, D2, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4620a8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [X5, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X19, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X15, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 460d40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1054>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X26, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D6, D5, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 461c48 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460df4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X26, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461a30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 461c5c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D29, D29, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X16, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X16, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X14, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4628bc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2bd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X13, X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X25, X17, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
DUP Z23.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
CNTB X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P5.D, XZR, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
DUP Z24.D, Z13.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X10, X10, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
FCMP D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 460e0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D31, D4, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
CMP X6, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 461c60 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 461d40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2054>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D31, D31, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 460d4c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1060>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 460df4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D31, D4, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR X14, [X5, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X25, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X25, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X15, X16, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X19, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462368 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x267c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D30, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D2, D30, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462358 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x266c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 461d20 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2034>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X15, 462044 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461cf4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2008>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461cd0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X5, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 46280c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D16, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D17, D16, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4627fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X5, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 4622a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D22, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D4, D22, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462290 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X5, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 4623dc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x26f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D28, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D1, D28, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4623cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x26e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462044 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X25, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X25, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X13, X8, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDR X8, [X10, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.EQ 462958 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461e68 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x217c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461e54 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461e2c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461e04 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461ddc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x20f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461db4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x20c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X24, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461db0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x20c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D18, [X25, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D19, D18, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4628a8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2bbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461dd8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x20ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D4, D22, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462888 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X24, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461e00 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D25, [X25, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D27, D25, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D27, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462874 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461e28 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x213c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D2, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D30, D2, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D30, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462860 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X24, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461e50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D6, [X25, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D7, D6, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462848 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4626cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X24, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 462678 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x298c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X15, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D31, D31, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 460d1c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1030>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D31, D15, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X8, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 460cf4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1008>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X13, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X0, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D24, D31, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D24, [X0, X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 461cf0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2004>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D25, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D27, D25, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D27, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4627e0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2af4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 461cf0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2004>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X8, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X0, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D5, D31, D30, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D5, [X0, X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 461c8c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D7, D6, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4626ac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 461c8c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X14, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X0, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D2, D31, D28, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D2, [X0, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 461d14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2028>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D3, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D5, D3, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D5, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462724 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 461d14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2028>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X26, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461a30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D15, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D29, D29, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X25, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D4, D22, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4627cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2ae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 461e78 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x218c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMADD D29, D31, D6, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
B 461c8c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D18, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D19, D18, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4627e8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2afc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 461e64 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMADD D29, D31, D3, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
B 461d14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2028>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X8, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D24, D31, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D24, [X8, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461e78 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x218c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMADD D29, D31, D25, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
B 461cf0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2004>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X8, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D21, D31, D18, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D21, [X8, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461e64 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X25, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X0, X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D19, D31, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D19, [X0, X25]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 461ccc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D20, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D21, D20, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 46283c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 461cd0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMADD D29, D31, D20, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 461cd0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X8, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D17, D31, D6, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D17, [X8, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461e54 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X8, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D5, D31, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D5, [X8, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461e28 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x213c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D28, [X8, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D1, D31, D25, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D1, [X8, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461e00 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X8, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D24, D31, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D24, [X8, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461dd8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x20ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X8, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D21, D31, D18, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D21, [X8, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461db0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x20c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 460e0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D31, D4, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
CMP X6, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 461c60 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 461e90 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x21a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1609-1723
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 25% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

FMA

Detected 15 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 58 FP arithmetical operations:

22: addition or subtraction (15 inside FMA instructions)
33: multiply (15 inside FMA instructions)
3: divide

The binary loop does not load or store any data.

General properties

nb instructions	389
nb uops	386
loop length	1556
used w registers	0
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	26
used q registers	0
used v registers	0
used z registers	3
nb stack references	26
ADD-SUB / MUL ratio	0.39

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	48.25 cycles
front end	48.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	49.50	49.50	26.25	26.25	26.25	26.25	23.00	19.50	19.25	19.25	37.83	37.50	37.67	1.50	1.50
cycles	49.50	49.50	26.25	26.25	26.25	26.25	23.00	19.50	19.25	19.25	37.83	37.50	37.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	48.25
Dispatch	49.50
DIV/SQRT	5.25-10.49
Overall L1	49.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	1%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	1%

Vector efficiency ratios

INT

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 49.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 460708

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
UBFM X8, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D13, [X26, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D31, [X0, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D18, D31, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D18, [X0, X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X2, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460760 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X5, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X3, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [X19, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4606e8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460c7c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xf90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X20, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMN X12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 46074c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X4, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X4, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X25, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D27, [X26, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D29, D29, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X2, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 460708 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D31, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X14, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X10, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D28, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FCMPE D28, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D13, D0, D26, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP X6, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4623f8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x270c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X15, X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X13, X15, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 460d4c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1060>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460d1c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1030>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460cf4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1008>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X5, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X16, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 460cf0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1004>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D30, D1, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D30, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462284 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2598>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X5, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X14, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 460d18 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x102c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D2, [X26, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D3, D2, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4620a8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [X5, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X19, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X15, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 460d40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1054>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X26, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D6, D5, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 461c48 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460df4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X26, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461a30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 461c5c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D29, D29, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X16, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X16, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X14, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4628bc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2bd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X13, X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X25, X17, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
DUP Z23.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
CNTB X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P5.D, XZR, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
DUP Z24.D, Z13.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X10, X10, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
FCMP D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 460e0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D31, D4, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
CMP X6, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 461c60 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 461d40 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2054>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D31, D31, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 460d4c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1060>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 460df4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D31, D4, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR X14, [X5, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X25, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X25, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X15, X16, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X19, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462368 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x267c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D30, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D2, D30, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462358 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x266c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 461d20 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2034>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X15, 462044 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461cf4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2008>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461cd0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X5, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 46280c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D16, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D17, D16, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4627fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X5, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 4622a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D22, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D4, D22, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462290 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x25a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X5, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 4623dc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x26f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D28, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D1, D28, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4623cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x26e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462044 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X25, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X25, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X13, X8, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDR X8, [X10, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.EQ 462958 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2c6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461e68 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x217c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461e54 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461e2c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461e04 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461ddc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x20f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461db4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x20c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X24, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461db0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x20c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D18, [X25, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D19, D18, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4628a8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2bbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461dd8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x20ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D4, D22, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462888 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X24, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461e00 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D25, [X25, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D27, D25, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D27, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462874 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461e28 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x213c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D2, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D30, D2, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D30, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462860 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X24, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461e50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D6, [X25, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D7, D6, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462848 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4626cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X24, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 462678 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x298c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X15, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D31, D31, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 460d1c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1030>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D31, D15, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X8, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 460cf4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1008>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X13, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X0, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D24, D31, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D24, [X0, X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 461cf0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2004>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D25, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D27, D25, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D27, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4627e0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2af4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 461cf0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2004>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X8, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X0, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D5, D31, D30, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D5, [X0, X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 461c8c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D7, D6, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4626ac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 461c8c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X14, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X0, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D2, D31, D28, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D2, [X0, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 461d14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2028>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D3, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D5, D3, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D5, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 462724 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 461d14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2028>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X26, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 461a30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D15, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D29, D29, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X25, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D4, D22, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4627cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2ae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 461e78 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x218c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMADD D29, D31, D6, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
B 461c8c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D18, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D19, D18, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4627e8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2afc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 461e64 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMADD D29, D31, D3, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
B 461d14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2028>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X8, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D24, D31, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D24, [X8, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461e78 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x218c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMADD D29, D31, D25, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
B 461cf0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2004>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X8, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D21, D31, D18, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D21, [X8, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461e64 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X25, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X0, X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D19, D31, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D19, [X0, X25]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 461ccc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D20, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D21, D20, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 46283c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 461cd0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMADD D29, D31, D20, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 461cd0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1fe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X8, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D17, D31, D6, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D17, [X8, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461e54 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X8, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D5, D31, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D5, [X8, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461e28 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x213c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D28, [X8, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D1, D31, D25, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D1, [X8, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461e00 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X10, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X8, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D24, D31, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D24, [X8, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461dd8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x20ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X8, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D21, D31, D18, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D21, [X8, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 461db0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x20c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 460e0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D31, D4, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
CMP X6, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 461c60 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4606fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 461e90 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x21a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code