OV - exec - Function hypre_BoomerAMGBuildMultipass.omp

	Function: hypre_BoomerAMGBuildMultipass.omp_outlined.17	Module: exec	Source: par_multi_interp.c:1575-1663 [...]	Coverage (incl. loops): 0.27% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663

--------------------------------------------------------------------------------

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1585:            if (n_fine)

1586:            {   tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1587:            tmp_marker_offd = NULL;

1588:            if (num_cols_offd)

1589:            {   tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1590:            for (i=0; i < n_fine; i++)

1591:            {   tmp_marker[i] = -1; }

1592:            for (i=0; i < num_cols_offd; i++)

1593:            {   tmp_marker_offd[i] = -1; }

1594:

1595:            /* Compute this thread's range of pass_length */

1596:            my_thread_num = hypre_GetThreadNum();

1597:            num_threads = hypre_NumActiveThreads();

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

1599:            if (my_thread_num == num_threads-1)

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

1661:           }

1662:           hypre_TFree(tmp_marker);

1663:           hypre_TFree(tmp_marker_offd);

0x436a50 SUB	SP, SP, #304

0x436a54 STP	X29, X30, [SP, #208]

0x436a58 STP	X28, X27, [SP, #224]

0x436a5c STP	X26, X25, [SP, #240]

0x436a60 STP	X24, X23, [SP, #256]

0x436a64 STP	X22, X21, [SP, #272]

0x436a68 STP	X20, X19, [SP, #288]

0x436a6c ADD	X29, SP, #208

0x436a70 LDP	X8, X9, [X29, #288]

0x436a74 STP	X7, X6, [X29, #992]

0x436a78 ORR	X24, XZR, X5

0x436a7c ORR	X25, XZR, X3

0x436a80 ORR	X26, XZR, X2

0x436a84 LDR	X0, [X2]

0x436a88 STUR	X4, [X29, #472]

0x436a8c STUR	X9, [X29, #416]

0x436a90 STR	X8, [SP, #104]

0x436a94 LDP	X8, X9, [X29, #272]

0x436a98 STUR	X9, [X29, #440]

0x436a9c STR	X8, [SP, #96]

0x436aa0 LDR	X8, [X29, #264]

0x436aa4 STR	X8, [SP, #88]

0x436aa8 LDP	X8, X21, [X29, #248]

0x436aac STR	X8, [SP, #80]

0x436ab0 LDR	X8, [X29, #240]

0x436ab4 STR	X8, [SP, #72]

0x436ab8 LDP	X8, X10, [X29, #192]

0x436abc LDP	X9, X28, [X29, #208]

0x436ac0 LDP	X27, X22, [X29, #224]

0x436ac4 STUR	X8, [X29, #464]

0x436ac8 LDR	X8, [X29, #184]

0x436acc STP	X10, X9, [X29, #960]

0x436ad0 STR	X8, [SP, #64]

0x436ad4 LDR	X8, [X29, #176]

0x436ad8 STR	X8, [SP, #56]

0x436adc LDP	X8, X9, [X29, #160]

0x436ae0 STP	X8, X9, [X29, #936]

0x436ae4 LDP	X23, X8, [X29, #144]

0x436ae8 STUR	X8, [X29, #496]

0x436aec LDR	X8, [X29, #136]

0x436af0 STR	X8, [SP, #40]

0x436af4 LDR	X8, [X29, #128]

0x436af8 STR	X8, [SP, #32]

0x436afc LDR	X8, [X29, #120]

0x436b00 STR	X8, [SP, #24]

0x436b04 LDR	X8, [X29, #112]

0x436b08 STR	X8, [SP, #16]

0x436b0c LDR	X8, [X29, #104]

0x436b10 STR	X8, [SP, #48]

0x436b14 LDR	X8, [X29, #96]

0x436b18 STR	X8, [SP, #8]

0x436b1c CBZ	X0, 436b50

0x436b20 MOVZ	W1, #8

0x436b24 BL	4ac4b0

0x436b28 ORR	X19, XZR, X0

0x436b2c LDR	X0, [X25]

0x436b30 CBZ	X0, 436b5c

0x436b34 MOVZ	W1, #8

0x436b38 BL	4ac4b0

0x436b3c ORR	X20, XZR, X0

0x436b40 LDR	X8, [X26]

0x436b44 CMP	X8, #1

0x436b48 B.GE	436b6c

0x436b4c B	436b94

0x436b50 ORR	X19, XZR, XZR

0x436b54 LDR	X0, [X25]

0x436b58 CBNZ	X0, 436b34

0x436b5c ORR	X20, XZR, XZR

0x436b60 LDR	X8, [X26]

0x436b64 CMP	X8, #1

0x436b68 B.LT	436b94

0x436b6c MOVN	X9, #0

0x436b70 ORR	X8, XZR, XZR

0x436b74 HINT	#0

0x436b78 HINT	#0

0x436b7c HINT	#0

(755) 0x436b80 STR	X9, [X19, X8,LSL #3]

(755) 0x436b84 ADD	X8, X8, #1

(755) 0x436b88 LDR	X10, [X26]

(755) 0x436b8c CMP	X8, X10

(755) 0x436b90 B.LT	436b80

0x436b94 LDR	X8, [X25]

0x436b98 CMP	X8, #1

0x436b9c B.LT	436bbc

0x436ba0 MOVN	X9, #0

0x436ba4 ORR	X8, XZR, XZR

(756) 0x436ba8 STR	X9, [X20, X8,LSL #3]

(756) 0x436bac ADD	X8, X8, #1

(756) 0x436bb0 LDR	X10, [X25]

(756) 0x436bb4 CMP	X8, X10

(756) 0x436bb8 B.LT	436ba8

0x436bbc BL	4ae1b0

0x436bc0 ORR	X25, XZR, X0

0x436bc4 BL	4ae190

0x436bc8 LDR	X9, [X24]

0x436bcc SUB	X11, X0, #1

0x436bd0 SDIV	X10, X9, X0

0x436bd4 MUL	X8, X10, X25

0x436bd8 ADD	X10, X10, X8

0x436bdc CMP	X25, X11

0x436be0 CSEL	X9, X9, X10, #0

0x436be4 CMP	X8, X9

0x436be8 B.GE	437138

0x436bec LDUR	X10, [X29, #472]

0x436bf0 LDR	X0, [X28]

0x436bf4 LDR	X3, [X27]

0x436bf8 LDR	X4, [X22]

0x436bfc LDR	X5, [X21]

0x436c00 LDR	X11, [X10]

0x436c04 LDUR	X10, [X29, #488]

0x436c08 LDR	X10, [X10]

0x436c0c LDR	X11, [X11, #8]

0x436c10 STUR	X10, [X29, #488]

0x436c14 LDUR	X10, [X29, #480]

0x436c18 ADD	X2, X8, X11

0x436c1c ADD	X9, X9, X11

0x436c20 LDR	X10, [X10]

0x436c24 STUR	X10, [X29, #480]

0x436c28 LDP	X15, X12, [SP, #40]

0x436c2c LDR	X10, [SP, #8]

0x436c30 LDR	X14, [SP, #32]

0x436c34 LDR	X12, [X12]

0x436c38 LDR	X10, [X10]

0x436c3c LDR	X14, [X14]

0x436c40 LDR	X15, [X15]

0x436c44 STR	X12, [SP, #48]

0x436c48 LDP	X12, X13, [SP, #16]

0x436c4c LDUR	X16, [X29, #464]

0x436c50 LDR	X12, [X12]

0x436c54 LDR	X13, [X13]

0x436c58 LDR	X16, [X16]

0x436c5c STUR	X16, [X29, #464]

0x436c60 LDUR	X16, [X29, #448]

0x436c64 LDR	X17, [X16]

0x436c68 LDUR	X16, [X29, #456]

0x436c6c LDR	X16, [X16]

0x436c70 STR	X16, [SP, #40]

0x436c74 LDUR	X8, [X29, #424]

0x436c78 LDR	X8, [X8]

0x436c7c STP	X8, X9, [X29, #960]

0x436c80 LDP	X11, X8, [X29, #944]

0x436c84 LDR	X9, [X11]

0x436c88 LDR	X8, [X8]

0x436c8c STP	X8, X9, [SP, #24]

0x436c90 ADD	X9, X9, #16

0x436c94 ADD	X8, X8, #16

0x436c98 STP	X8, X9, [SP, #8]

0x436c9c STUR	X10, [X29, #472]

0x436ca0 B	436cb4

  (744) 0x436ca4 LDUR	X8, [X29, #456]

  (744) 0x436ca8 ADD	X2, X2, #1

  (744) 0x436cac CMP	X2, X8

  (744) 0x436cb0 B.GE	437138

  (744) 0x436cb4 LDP	X8, X9, [X29, #992]

  (744) 0x436cb8 LDR	X30, [X9, X2,LSL #3]

  (744) 0x436cbc ADD	X26, X30, #1

  (744) 0x436cc0 LDR	X8, [X8, X30,LSL #3]

  (744) 0x436cc4 LDR	X25, [X10, X30,LSL #3]

  (744) 0x436cc8 LDR	X9, [X10, X26,LSL #3]

  (744) 0x436ccc ADD	X11, X9, X8

  (744) 0x436cd0 SUB	X11, X11, X25

  (744) 0x436cd4 CMP	X8, X11

  (744) 0x436cd8 B.GE	436d8c

  (744) 0x436cdc LDR	X11, [SP, #48]

  (744) 0x436ce0 SUB	W16, W9, W25

  (744) 0x436ce4 ANDS	X18, X16, #0x3

  (744) 0x436ce8 LDR	X11, [X11, #8]

  (744) 0x436cec B.EQ	436d28

  (744) 0x436cf0 ORR	X16, XZR, X8

  (744) 0x436cf4 HINT	#0

  (744) 0x436cf8 HINT	#0

  (744) 0x436cfc HINT	#0

    (750) 0x436d00 LDR	X1, [X11, X16,LSL #3]

    (750) 0x436d04 ADD	X16, X16, #1

    (750) 0x436d08 SUBS	X18, X18, #1

    (750) 0x436d0c LDR	X1, [X12, X1,LSL #3]

    (750) 0x436d10 STR	X30, [X19, X1,LSL #3]

    (750) 0x436d14 B.NE	436d00

  (744) 0x436d18 SUB	X18, X25, X9

  (744) 0x436d1c CMN	X18, #4

  (744) 0x436d20 B.LS	436d38

  (744) 0x436d24 B	436d88

  (744) 0x436d28 ORR	X16, XZR, X8

  (744) 0x436d2c SUB	X18, X25, X9

  (744) 0x436d30 CMN	X18, #4

  (744) 0x436d34 B.HI	436d88

  (744) 0x436d38 ADD	X8, X9, X8

  (744) 0x436d3c ADD	X9, X11, X16,LSL #3

  (744) 0x436d40 SUB	X8, X8, X16

  (744) 0x436d44 ADD	X9, X9, #16

  (744) 0x436d48 SUB	X8, X8, X25

    (749) 0x436d4c LDUR	X11, [X9, #496]

    (749) 0x436d50 SUBS	X8, X8, #4

    (749) 0x436d54 LDR	X11, [X12, X11,LSL #3]

    (749) 0x436d58 STR	X30, [X19, X11,LSL #3]

    (749) 0x436d5c LDUR	X11, [X9, #504]

    (749) 0x436d60 LDR	X11, [X12, X11,LSL #3]

    (749) 0x436d64 STR	X30, [X19, X11,LSL #3]

    (749) 0x436d68 LDR	X11, [X9]

    (749) 0x436d6c LDR	X11, [X12, X11,LSL #3]

    (749) 0x436d70 STR	X30, [X19, X11,LSL #3]

    (749) 0x436d74 LDR	X11, [X9, #8]

    (749) 0x436d78 ADD	X9, X9, #32

    (749) 0x436d7c LDR	X11, [X12, X11,LSL #3]

    (749) 0x436d80 STR	X30, [X19, X11,LSL #3]

    (749) 0x436d84 B.NE	436d4c

  (744) 0x436d88 LDR	X25, [X10, X30,LSL #3]

  (744) 0x436d8c LDR	X8, [X13, X30,LSL #3]

  (744) 0x436d90 LDR	X16, [X13, X26,LSL #3]

  (744) 0x436d94 MOVI	D2, #0

  (744) 0x436d98 ADD	X8, X8, #1

  (744) 0x436d9c CMP	X8, X16

  (744) 0x436da0 B.GE	436e60

  (744) 0x436da4 LDUR	X10, [X29, #424]

  (744) 0x436da8 LDUR	X9, [X29, #496]

  (744) 0x436dac MOVI	D1, #0

  (744) 0x436db0 LDR	X11, [X10]

  (744) 0x436db4 LDUR	X10, [X29, #432]

  (744) 0x436db8 LDR	X9, [X9]

  (744) 0x436dbc LDR	X18, [X10]

  (744) 0x436dc0 LDR	X10, [SP, #64]

  (744) 0x436dc4 LDR	X7, [X10]

  (744) 0x436dc8 LDR	X10, [SP, #56]

  (744) 0x436dcc LDR	X21, [X10]

  (744) 0x436dd0 B	436dec

0x436dd4 HINT	#0

0x436dd8 HINT	#0

0x436ddc HINT	#0

    (748) 0x436de0 ADD	X8, X8, #1

    (748) 0x436de4 CMP	X8, X16

    (748) 0x436de8 B.GE	436e64

    (748) 0x436dec LDR	X22, [X14, X8,LSL #3]

    (748) 0x436df0 LDR	X1, [X15, X22,LSL #3]

    (748) 0x436df4 CMN	X1, #3

    (748) 0x436df8 B.EQ	436e20

    (748) 0x436dfc LDR	X1, [X23]

    (748) 0x436e00 CMP	X1, #1

    (748) 0x436e04 B.EQ	436e18

    (748) 0x436e08 LDR	X1, [X9, X30,LSL #3]

    (748) 0x436e0c LDR	X24, [X9, X22,LSL #3]

    (748) 0x436e10 CMP	X1, X24

    (748) 0x436e14 B.NE	436e20

    (748) 0x436e18 LDR	D3, [X11, X8,LSL #3]

    (748) 0x436e1c FADD	D1, D3, D1

    (748) 0x436e20 CMN	X22, #1

    (748) 0x436e24 B.EQ	436de0

    (748) 0x436e28 LDR	X1, [X19, X22,LSL #3]

    (748) 0x436e2c CMP	X1, X30

    (748) 0x436e30 B.NE	436de0

    (748) 0x436e34 LDR	X16, [X7, X22,LSL #3]

    (748) 0x436e38 LDR	D3, [X11, X8,LSL #3]

    (748) 0x436e3c STR	X16, [X21, X25,LSL #3]

    (748) 0x436e40 LDR	X16, [X13, X26,LSL #3]

    (748) 0x436e44 FADD	D2, D3, D2

    (748) 0x436e48 STR	D3, [X18, X25,LSL #3]

    (748) 0x436e4c ADD	X25, X25, #1

    (748) 0x436e50 B	436de0

0x436e54 HINT	#0

0x436e58 HINT	#0

0x436e5c HINT	#0

  (744) 0x436e60 MOVI	D1, #0

  (744) 0x436e64 LDUR	X8, [X29, #464]

  (744) 0x436e68 LDR	X9, [X17, X26,LSL #3]

  (744) 0x436e6c LDR	X7, [X17, X30,LSL #3]

  (744) 0x436e70 LDR	X8, [X8, X30,LSL #3]

  (744) 0x436e74 ADD	X11, X9, X8

  (744) 0x436e78 SUB	X11, X11, X7

  (744) 0x436e7c CMP	X8, X11

  (744) 0x436e80 B.GE	436f2c

  (744) 0x436e84 LDR	X10, [SP, #40]

  (744) 0x436e88 SUB	W16, W9, W7

  (744) 0x436e8c ANDS	X18, X16, #0x3

  (744) 0x436e90 LDR	X11, [X10, #8]

  (744) 0x436e94 B.EQ	436ec8

  (744) 0x436e98 ORR	X16, XZR, X8

  (744) 0x436e9c HINT	#0

    (747) 0x436ea0 LDR	X1, [X11, X16,LSL #3]

    (747) 0x436ea4 ADD	X16, X16, #1

    (747) 0x436ea8 SUBS	X18, X18, #1

    (747) 0x436eac LDR	X1, [X0, X1,LSL #3]

    (747) 0x436eb0 STR	X30, [X20, X1,LSL #3]

    (747) 0x436eb4 B.NE	436ea0

  (744) 0x436eb8 SUB	X18, X7, X9

  (744) 0x436ebc CMN	X18, #4

  (744) 0x436ec0 B.LS	436ed8

  (744) 0x436ec4 B	436f28

  (744) 0x436ec8 ORR	X16, XZR, X8

  (744) 0x436ecc SUB	X18, X7, X9

  (744) 0x436ed0 CMN	X18, #4

  (744) 0x436ed4 B.HI	436f28

  (744) 0x436ed8 ADD	X8, X9, X8

  (744) 0x436edc ADD	X9, X11, X16,LSL #3

  (744) 0x436ee0 SUB	X8, X8, X16

  (744) 0x436ee4 ADD	X9, X9, #16

  (744) 0x436ee8 SUB	X8, X8, X7

    (746) 0x436eec LDUR	X11, [X9, #496]

    (746) 0x436ef0 SUBS	X8, X8, #4

    (746) 0x436ef4 LDR	X11, [X0, X11,LSL #3]

    (746) 0x436ef8 STR	X30, [X20, X11,LSL #3]

    (746) 0x436efc LDUR	X11, [X9, #504]

    (746) 0x436f00 LDR	X11, [X0, X11,LSL #3]

    (746) 0x436f04 STR	X30, [X20, X11,LSL #3]

    (746) 0x436f08 LDR	X11, [X9]

    (746) 0x436f0c LDR	X11, [X0, X11,LSL #3]

    (746) 0x436f10 STR	X30, [X20, X11,LSL #3]

    (746) 0x436f14 LDR	X11, [X9, #8]

    (746) 0x436f18 ADD	X9, X9, #32

    (746) 0x436f1c LDR	X11, [X0, X11,LSL #3]

    (746) 0x436f20 STR	X30, [X20, X11,LSL #3]

    (746) 0x436f24 B.NE	436eec

  (744) 0x436f28 LDR	X7, [X17, X30,LSL #3]

  (744) 0x436f2c LDR	X24, [X3, X30,LSL #3]

  (744) 0x436f30 LDR	X28, [X3, X26,LSL #3]

  (744) 0x436f34 CMP	X24, X28

  (744) 0x436f38 B.GE	437008

(745) 0x436f3c LDP	X9, X8, [SP, #72]

(745) 0x436f40 LDR	X16, [X8]

(745) 0x436f44 LDUR	X8, [X29, #496]

(745) 0x436f48 LDR	X21, [X9]

(745) 0x436f4c LDR	X27, [X8]

(745) 0x436f50 LDP	X9, X8, [SP, #88]

(745) 0x436f54 ADD	X16, X16, X24,LSL #3

(745) 0x436f58 LDR	X18, [X8]

(745) 0x436f5c LDUR	X8, [X29, #440]

(745) 0x436f60 LDR	X11, [X9]

(745) 0x436f64 LDR	X9, [SP, #104]

(745) 0x436f68 LDR	X22, [X8]

(745) 0x436f6c LDUR	X8, [X29, #416]

(745) 0x436f70 LDR	X9, [X9]

(745) 0x436f74 LDR	X8, [X8]

(745) 0x436f78 B	436f90

0x436f7c HINT	#0

(745) 0x436f80 ADD	X24, X24, #1

(745) 0x436f84 ADD	X16, X16, #8

(745) 0x436f88 CMP	X24, X28

(745) 0x436f8c B.GE	437008

(745) 0x436f90 ORR	X1, XZR, X16

(745) 0x436f94 CBZ	X4, 436fa0

(745) 0x436f98 LDR	X1, [X16]

(745) 0x436f9c ADD	X1, X21, X1,LSL #3

(745) 0x436fa0 LDR	X1, [X1]

(745) 0x436fa4 LDR	X6, [X5, X1,LSL #3]

(745) 0x436fa8 CMN	X6, #3

(745) 0x436fac B.EQ	436fd4

(745) 0x436fb0 LDR	X6, [X23]

(745) 0x436fb4 CMP	X6, #1

(745) 0x436fb8 B.EQ	436fcc

(745) 0x436fbc LDR	X6, [X27, X30,LSL #3]

(745) 0x436fc0 LDR	X10, [X11, X1,LSL #3]

(745) 0x436fc4 CMP	X6, X10

(745) 0x436fc8 B.NE	436fd4

(745) 0x436fcc LDR	D3, [X18, X24,LSL #3]

(745) 0x436fd0 FADD	D1, D3, D1

(745) 0x436fd4 CMN	X1, #1

(745) 0x436fd8 B.EQ	436f80

(745) 0x436fdc LDR	X10, [X20, X1,LSL #3]

(745) 0x436fe0 CMP	X10, X30

(745) 0x436fe4 B.NE	436f80

(745) 0x436fe8 LDR	X10, [X8, X1,LSL #3]

(745) 0x436fec LDR	D3, [X18, X24,LSL #3]

(745) 0x436ff0 STR	X10, [X9, X7,LSL #3]

(745) 0x436ff4 LDR	X28, [X3, X26,LSL #3]

(745) 0x436ff8 FADD	D2, D3, D2

(745) 0x436ffc STR	D3, [X22, X7,LSL #3]

(745) 0x437000 ADD	X7, X7, #1

(745) 0x437004 B	436f80

  (744) 0x437008 LDR	X8, [X13, X30,LSL #3]

  (744) 0x43700c LDUR	X9, [X29, #448]

  (744) 0x437010 LDR	D3, [X9, X8,LSL #3]

  (744) 0x437014 FMUL	D2, D3, D2

  (744) 0x437018 FCMP	D2, #0

  (744) 0x43701c B.EQ	437028

  (744) 0x437020 FNEG	D0, D1

  (744) 0x437024 FDIV	D0, D0, D2

  (744) 0x437028 LDUR	X10, [X29, #472]

  (744) 0x43702c LDR	X16, [X10, X30,LSL #3]

  (744) 0x437030 SUBS	X8, X25, X16

  (744) 0x437034 B.LE	4370b4

  (744) 0x437038 CMP	X8, #4

  (744) 0x43703c ORR	X9, XZR, X16

  (744) 0x437040 B.CC	437084

  (744) 0x437044 LDR	X18, [SP, #16]

  (744) 0x437048 AND	X11, X8, #0x0

  (744) 0x43704c ADD	X9, X16, X11

  (744) 0x437050 ADD	X16, X18, X16,LSL #3

  (744) 0x437054 AND	X18, X8, #0x0

  (744) 0x437058 HINT	#0

  (744) 0x43705c HINT	#0

    (754) 0x437060 LDP	Q1, Q2, [X16, #2032]

    (754) 0x437064 SUBS	X18, X18, #4

    (754) 0x437068 FMUL	V2.2D, V2.2D, V0.D[0]

    (754) 0x43706c FMUL	V1.2D, V1.2D, V0.D[0]

    (754) 0x437070 STP	Q1, Q2, [X16, #2032]

    (754) 0x437074 ADD	X16, X16, #32

    (754) 0x437078 B.NE	437060

  (744) 0x43707c CMP	X8, X11

  (744) 0x437080 B.EQ	4370b4

  (744) 0x437084 LDR	X8, [SP, #32]

  (744) 0x437088 ADD	X8, X8, X9,LSL #3

  (744) 0x43708c SUB	X9, X25, X9

  (744) 0x437090 HINT	#0

  (744) 0x437094 HINT	#0

  (744) 0x437098 HINT	#0

  (744) 0x43709c HINT	#0

    (753) 0x4370a0 LDR	D1, [X8]

    (753) 0x4370a4 SUBS	X9, X9, #1

    (753) 0x4370a8 FMUL	D1, D1, D0

    (753) 0x4370ac STR	D1, [X8], #8

    (753) 0x4370b0 B.NE	4370a0

  (744) 0x4370b4 LDR	X16, [X17, X30,LSL #3]

  (744) 0x4370b8 SUBS	X8, X7, X16

  (744) 0x4370bc B.LE	436ca4

  (744) 0x4370c0 CMP	X8, #4

  (744) 0x4370c4 ORR	X9, XZR, X16

  (744) 0x4370c8 B.CC	437104

  (744) 0x4370cc LDR	X18, [SP, #8]

  (744) 0x4370d0 AND	X11, X8, #0x0

  (744) 0x4370d4 ADD	X9, X16, X11

  (744) 0x4370d8 ADD	X16, X18, X16,LSL #3

  (744) 0x4370dc AND	X18, X8, #0x0

    (752) 0x4370e0 LDP	Q1, Q2, [X16, #2032]

    (752) 0x4370e4 SUBS	X18, X18, #4

    (752) 0x4370e8 FMUL	V2.2D, V2.2D, V0.D[0]

    (752) 0x4370ec FMUL	V1.2D, V1.2D, V0.D[0]

    (752) 0x4370f0 STP	Q1, Q2, [X16, #2032]

    (752) 0x4370f4 ADD	X16, X16, #32

    (752) 0x4370f8 B.NE	4370e0

  (744) 0x4370fc CMP	X8, X11

  (744) 0x437100 B.EQ	436ca4

  (744) 0x437104 LDR	X8, [SP, #24]

  (744) 0x437108 ADD	X8, X8, X9,LSL #3

  (744) 0x43710c SUB	X9, X7, X9

  (744) 0x437110 HINT	#0

  (744) 0x437114 HINT	#0

  (744) 0x437118 HINT	#0

  (744) 0x43711c HINT	#0

    (751) 0x437120 LDR	D1, [X8]

    (751) 0x437124 SUBS	X9, X9, #1

    (751) 0x437128 FMUL	D1, D1, D0

    (751) 0x43712c STR	D1, [X8], #8

    (751) 0x437130 B.NE	437120

  (744) 0x437134 B	436ca4

0x437138 ORR	X0, XZR, X19

0x43713c BL	4ac5b0

0x437140 ORR	X0, XZR, X20

0x437144 LDP	X20, X19, [SP, #288]

0x437148 LDP	X22, X21, [SP, #272]

0x43714c LDP	X24, X23, [SP, #256]

0x437150 LDP	X26, X25, [SP, #240]

0x437154 LDP	X28, X27, [SP, #224]

0x437158 LDP	X29, X30, [SP, #208]

0x43715c ADD	SP, SP, #304

0x437160 B	4ac5b0

0x437164 HINT	#0

0x437168 HINT	#0

0x43716c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.56+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.44+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1669	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:785	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 33.00 to 10.00 cycles (3.30x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	160
nb uops	147
loop length	640
used w registers	1
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.38 cycles
front end	18.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.50	7.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	33.00	33.00	33.00	18.00	18.00
cycles	7.50	7.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	33.00	33.00	33.00	18.00	18.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	18.38
Dispatch	33.00
DIV/SQRT	5.00-20.00
Overall L1	33.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	29%
load	27%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 33.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 436a50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X7, X6, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X4, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X21, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X10, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X9, X28, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X22, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X23, X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X0, 436b50 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 436b5c <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 436b6c <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 436b94 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X0, 436b34 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 436b94 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 436bbc <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ae1b0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ae190 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MUL X8, X10, X25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437138 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X4, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X5, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X12, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X12, X13, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X16, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X16, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X16, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X16, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X8, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X8, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X8, X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 436cb4 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ac5b0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ac5b0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	160
nb uops	147
loop length	640
used w registers	1
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.38 cycles
front end	18.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.50	7.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	33.00	33.00	33.00	18.00	18.00
cycles	7.50	7.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	33.00	33.00	33.00	18.00	18.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	18.38
Dispatch	33.00
DIV/SQRT	5.00-20.00
Overall L1	33.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	29%
load	27%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 33.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 436a50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X7, X6, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X4, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X21, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X10, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X9, X28, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X22, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X23, X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X0, 436b50 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 436b5c <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 436b6c <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 436b94 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X0, 436b34 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 436b94 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 436bbc <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ae1b0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ae190 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MUL X8, X10, X25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437138 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X4, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X5, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X12, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X12, X13, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X16, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X16, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X16, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X16, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X8, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X8, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X8, X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 436cb4 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ac5b0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ac5b0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.omp_outlined.17–	0.27	0.13
○Loop 755 - par_multi_interp.c:1590-1591 - exec	0.08	0.03
▼Loop 745 - par_multi_interp.c:1605-1660 - exec–	0.00	0.00
▼Loop 744 - par_multi_interp.c:1605-1660 - exec–	0.04	0.01
○Loop 748 - par_multi_interp.c:1618-1628 - exec	0.14	0.05
○Loop 750 - par_multi_interp.c:1612-1615 - exec	0.00	0.01
○Loop 753 - par_multi_interp.c:1657-1658 - exec	0.00	0.00
○Loop 752 - par_multi_interp.c:1659-1660 - exec	0.00	0.00
○Loop 747 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 751 - par_multi_interp.c:1659-1660 - exec	0.00	0.00
○Loop 754 - par_multi_interp.c:1657-1658 - exec	0.00	0.00
○Loop 749 - par_multi_interp.c:1612-1615 - exec	0.00	0.00
○Loop 746 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 756 - par_multi_interp.c:1592-1593 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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Vector efficiency ratios

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ASM code