OV - exec - Function hypre_BoomerAMGBuildMultipass.omp

	Function: hypre_BoomerAMGBuildMultipass.omp_outlined.19	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage (incl. loops): 1.14% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

1755:              tmp_array_offd = NULL;

1756:              if (new_num_cols_offd > n_coarse_offd)

1757:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1758:              else

1759:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);}

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x437170 SUB	SP, SP, #464

0x437174 STP	X29, X30, [SP, #368]

0x437178 STP	X28, X27, [SP, #384]

0x43717c STP	X26, X25, [SP, #400]

0x437180 STP	X24, X23, [SP, #416]

0x437184 STP	X22, X21, [SP, #432]

0x437188 STP	X20, X19, [SP, #448]

0x43718c ADD	X29, SP, #368

0x437190 LDR	X8, [X29, #376]

0x437194 STUR	X7, [X29, #440]

0x437198 LDR	X0, [X2]

0x43719c ORR	X22, XZR, X6

0x4371a0 ORR	X26, XZR, X5

0x4371a4 ORR	X21, XZR, X4

0x4371a8 ORR	X24, XZR, X3

0x4371ac ORR	X25, XZR, X2

0x4371b0 STR	X8, [SP, #136]

0x4371b4 LDR	X8, [X29, #368]

0x4371b8 STR	X8, [SP, #128]

0x4371bc LDR	X8, [X29, #360]

0x4371c0 STR	X8, [SP, #120]

0x4371c4 LDR	X8, [X29, #352]

0x4371c8 STR	X8, [SP, #112]

0x4371cc LDR	X8, [X29, #344]

0x4371d0 STR	X8, [SP, #104]

0x4371d4 LDR	X8, [X29, #336]

0x4371d8 STR	X8, [SP, #96]

0x4371dc LDR	X8, [X29, #328]

0x4371e0 STR	X8, [SP, #88]

0x4371e4 LDR	X8, [X29, #320]

0x4371e8 STR	X8, [SP, #80]

0x4371ec LDR	X8, [X29, #312]

0x4371f0 STR	X8, [SP, #72]

0x4371f4 LDP	X8, X9, [X29, #296]

0x4371f8 STP	X8, X9, [X29, #976]

0x4371fc LDP	X8, X9, [X29, #280]

0x437200 STP	X8, X9, [X29, #960]

0x437204 LDR	X8, [X29, #272]

0x437208 STR	X8, [SP, #64]

0x43720c LDR	X8, [X29, #264]

0x437210 STR	X8, [SP, #160]

0x437214 LDP	X10, X9, [X29, #248]

0x437218 STUR	X9, [X29, #496]

0x43721c LDP	X11, X9, [X29, #232]

0x437220 STP	X10, X9, [X29, #864]

0x437224 LDP	X10, X9, [X29, #216]

0x437228 STP	X11, X9, [X29, #880]

0x43722c LDP	X8, X9, [X29, #200]

0x437230 STUR	X8, [X29, #400]

0x437234 LDR	X8, [X29, #192]

0x437238 STP	X10, X9, [X29, #896]

0x43723c STR	X8, [SP, #152]

0x437240 LDP	X10, X9, [X29, #176]

0x437244 STUR	X9, [X29, #488]

0x437248 LDP	X8, X9, [X29, #160]

0x43724c STP	X10, X8, [X29, #920]

0x437250 LDR	X8, [X29, #152]

0x437254 STUR	X9, [X29, #344]

0x437258 STR	X8, [SP, #144]

0x43725c LDP	X10, X9, [X29, #136]

0x437260 LDP	X27, X23, [X29, #104]

0x437264 LDR	X28, [X29, #96]

0x437268 STUR	X9, [X29, #480]

0x43726c LDP	X8, X9, [X29, #120]

0x437270 STUR	X9, [X29, #336]

0x437274 STP	X10, X8, [X29, #936]

0x437278 CBZ	X0, 4372b4

0x43727c MOVZ	W1, #8

0x437280 BL	4ac4b0

0x437284 ORR	X19, XZR, X0

0x437288 LDR	X0, [X24]

0x43728c CBZ	X0, 4372c0

0x437290 MOVZ	W1, #8

0x437294 BL	4ac4b0

0x437298 ORR	X20, XZR, X0

0x43729c LDR	X0, [X21]

0x4372a0 CBZ	X0, 4372cc

0x4372a4 MOVZ	W1, #8

0x4372a8 BL	4ac4b0

0x4372ac ORR	X21, XZR, X0

0x4372b0 B	4372d0

0x4372b4 ORR	X19, XZR, XZR

0x4372b8 LDR	X0, [X24]

0x4372bc CBNZ	X0, 437290

0x4372c0 ORR	X20, XZR, XZR

0x4372c4 LDR	X0, [X21]

0x4372c8 CBNZ	X0, 4372a4

0x4372cc ORR	X21, XZR, XZR

0x4372d0 LDR	X8, [X26]

0x4372d4 LDR	X9, [X22]

0x4372d8 MOVZ	W1, #8

0x4372dc CMP	X8, X9

0x4372e0 CSEL	X0, X8, X9, #12

0x4372e4 BL	4ac4b0

0x4372e8 LDR	X8, [X25]

0x4372ec ORR	X22, XZR, X0

0x4372f0 CMP	X8, #1

0x4372f4 B.LT	437314

0x4372f8 MOVN	X9, #0

0x4372fc ORR	X8, XZR, XZR

(772) 0x437300 STR	X9, [X19, X8,LSL #3]

(772) 0x437304 ADD	X8, X8, #1

(772) 0x437308 LDR	X10, [X25]

(772) 0x43730c CMP	X8, X10

(772) 0x437310 B.LT	437300

0x437314 LDR	X8, [X24]

0x437318 CMP	X8, #1

0x43731c B.LT	43733c

0x437320 MOVN	X9, #0

0x437324 ORR	X8, XZR, XZR

(771) 0x437328 STR	X9, [X20, X8,LSL #3]

(771) 0x43732c ADD	X8, X8, #1

(771) 0x437330 LDR	X10, [X24]

(771) 0x437334 CMP	X8, X10

(771) 0x437338 B.LT	437328

0x43733c BL	4ae1b0

0x437340 ORR	X24, XZR, X0

0x437344 BL	4ae190

0x437348 LDR	X9, [X27]

0x43734c SUB	X11, X0, #1

0x437350 SDIV	X10, X9, X0

0x437354 MUL	X8, X10, X24

0x437358 ADD	X10, X10, X8

0x43735c CMP	X24, X11

0x437360 CSEL	X9, X9, X10, #0

0x437364 CMP	X8, X9

0x437368 B.GE	437bd8

0x43736c LDUR	X10, [X29, #440]

0x437370 LDUR	X12, [X29, #480]

0x437374 LDR	X11, [X28]

0x437378 LDR	X10, [X10]

0x43737c LDR	X13, [X12]

0x437380 LDR	X12, [SP, #144]

0x437384 LDR	X15, [X12]

0x437388 LDUR	X12, [X29, #488]

0x43738c LDR	X10, [X10, X11,LSL #3]

0x437390 LDR	X11, [X23]

0x437394 LDR	X16, [X12]

0x437398 LDR	X12, [SP, #152]

0x43739c STUR	X11, [X29, #440]

0x4373a0 LDUR	X11, [X29, #432]

0x4373a4 ADD	X9, X9, X10

0x4373a8 LDR	X11, [X11]

0x4373ac LDR	X12, [X12]

0x4373b0 STUR	X11, [X29, #432]

0x4373b4 LDUR	X11, [X29, #336]

0x4373b8 LDR	X14, [X11]

0x4373bc LDUR	X11, [X29, #424]

0x4373c0 LDR	X0, [X11]

0x4373c4 LDUR	X11, [X29, #416]

0x4373c8 LDR	X11, [X11]

0x4373cc STUR	X11, [X29, #416]

0x4373d0 LDUR	X11, [X29, #344]

0x4373d4 LDR	X17, [X11]

0x4373d8 LDUR	X11, [X29, #408]

0x4373dc LDR	X1, [X11]

0x4373e0 LDUR	X11, [X29, #400]

0x4373e4 LDR	X2, [X11]

0x4373e8 LDUR	X11, [X29, #392]

0x4373ec LDR	X3, [X11]

0x4373f0 LDUR	X11, [X29, #384]

0x4373f4 LDR	X4, [X11]

0x4373f8 LDUR	X11, [X29, #376]

0x4373fc LDR	X5, [X11]

0x437400 LDUR	X11, [X29, #368]

0x437404 LDR	X6, [X11]

0x437408 LDUR	X11, [X29, #360]

0x43740c LDR	X7, [X11]

0x437410 LDUR	X11, [X29, #352]

0x437414 LDR	X11, [X11]

0x437418 STUR	X11, [X29, #352]

0x43741c LDUR	X11, [X29, #496]

0x437420 LDR	X11, [X11]

0x437424 STUR	X11, [X29, #496]

0x437428 LDUR	X11, [X29, #464]

0x43742c LDR	X11, [X11]

0x437430 STP	X9, X11, [X29, #848]

0x437434 ADD	X9, X8, X10

0x437438 LDUR	X8, [X29, #472]

0x43743c ADD	X10, X13, #8

0x437440 STP	X12, X15, [SP, #48]

0x437444 STR	X16, [SP, #168]

0x437448 LDR	X30, [X8]

0x43744c ADD	X8, X15, #8

0x437450 STP	X8, X10, [SP, #32]

0x437454 LDR	X8, [SP, #160]

0x437458 ADD	X10, X16, #8

0x43745c LDR	X8, [X8]

0x437460 STP	X13, X8, [SP, #176]

0x437464 ADD	X8, X12, #8

0x437468 STP	X8, X10, [SP, #16]

0x43746c ADD	X10, X13, #16

0x437470 ADD	X8, X16, #16

0x437474 STP	X8, X10, [SP]

0x437478 STUR	X0, [X29, #424]

0x43747c STP	X2, X1, [X29, #912]

0x437480 STP	X4, X3, [X29, #896]

0x437484 STP	X6, X5, [X29, #880]

0x437488 STUR	X7, [X29, #360]

0x43748c B	4374b4

0x437490 HINT	#0

0x437494 HINT	#0

0x437498 HINT	#0

0x43749c HINT	#0

(757) 0x4374a0 LDUR	X9, [X29, #472]

(757) 0x4374a4 LDUR	X8, [X29, #336]

(757) 0x4374a8 ADD	X9, X9, #1

(757) 0x4374ac CMP	X9, X8

(757) 0x4374b0 B.GE	437bd8

(757) 0x4374b4 LDP	X8, X10, [X29, #944]

(757) 0x4374b8 STUR	X9, [X29, #472]

(757) 0x4374bc LDR	X11, [X10, X9,LSL #3]

(757) 0x4374c0 LDR	X9, [X8, X11,LSL #3]

(757) 0x4374c4 ADD	X8, X11, #1

(757) 0x4374c8 LDR	X12, [X14, X11,LSL #3]

(757) 0x4374cc LDR	X13, [X14, X8,LSL #3]

(757) 0x4374d0 ADD	X10, X13, X9

(757) 0x4374d4 SUB	X10, X10, X12

(757) 0x4374d8 CMP	X9, X10

(757) 0x4374dc B.GE	437570

(757) 0x4374e0 SUB	W16, W13, W12

(757) 0x4374e4 ADD	X15, X12, #1

(757) 0x4374e8 TBZ	W16, #0, 437514

(757) 0x4374ec LDR	X16, [X28]

(757) 0x4374f0 LDR	X18, [SP, #176]

(757) 0x4374f4 LDR	X16, [X0, X16,LSL #3]

(757) 0x4374f8 STR	XZR, [X18, X12,LSL #3]

(757) 0x4374fc LDR	X18, [SP, #56]

(757) 0x437500 LDR	X16, [X16, X9,LSL #3]

(757) 0x437504 ADD	X9, X9, #1

(757) 0x437508 STR	X12, [X21, X16,LSL #3]

(757) 0x43750c STR	X16, [X18, X12,LSL #3]

(757) 0x437510 ORR	X12, XZR, X15

(757) 0x437514 CMP	X13, X15

(757) 0x437518 B.EQ	437570

(757) 0x43751c LDP	X15, X13, [SP, #32]

(757) 0x437520 ADD	X13, X13, X12,LSL #3

(757) 0x437524 ADD	X15, X15, X12,LSL #3

  (766) 0x437528 LDR	X16, [X28]

  (766) 0x43752c ADD	X18, X12, #1

  (766) 0x437530 LDR	X16, [X0, X16,LSL #3]

  (766) 0x437534 LDR	X16, [X16, X9,LSL #3]

  (766) 0x437538 STR	X12, [X21, X16,LSL #3]

  (766) 0x43753c STP	XZR, XZR, [X13, #1016]

  (766) 0x437540 STUR	X16, [X15, #504]

  (766) 0x437544 ADD	X13, X13, #16

  (766) 0x437548 ADD	X12, X12, #2

  (766) 0x43754c LDR	X16, [X28]

  (766) 0x437550 LDR	X16, [X0, X16,LSL #3]

  (766) 0x437554 ADD	X16, X16, X9,LSL #3

  (766) 0x437558 ADD	X9, X9, #2

  (766) 0x43755c LDR	X16, [X16, #8]

  (766) 0x437560 CMP	X10, X9

  (766) 0x437564 STR	X18, [X21, X16,LSL #3]

  (766) 0x437568 STR	X16, [X15], #16

  (766) 0x43756c B.NE	437528

(757) 0x437570 LDUR	X9, [X29, #416]

(757) 0x437574 LDR	X13, [X17, X8,LSL #3]

(757) 0x437578 LDR	X12, [X17, X11,LSL #3]

(757) 0x43757c LDR	X9, [X9, X11,LSL #3]

(757) 0x437580 ADD	X10, X13, X9

(757) 0x437584 SUB	X10, X10, X12

(757) 0x437588 CMP	X9, X10

(757) 0x43758c B.GE	437628

(757) 0x437590 SUB	W16, W13, W12

(757) 0x437594 ADD	X15, X12, #1

(757) 0x437598 TBZ	W16, #0, 4375c4

(757) 0x43759c LDR	X16, [X28]

(757) 0x4375a0 LDR	X18, [SP, #168]

(757) 0x4375a4 LDR	X16, [X1, X16,LSL #3]

(757) 0x4375a8 STR	XZR, [X18, X12,LSL #3]

(757) 0x4375ac LDR	X18, [SP, #48]

(757) 0x4375b0 LDR	X16, [X16, X9,LSL #3]

(757) 0x4375b4 ADD	X9, X9, #1

(757) 0x4375b8 STR	X12, [X22, X16,LSL #3]

(757) 0x4375bc STR	X16, [X18, X12,LSL #3]

(757) 0x4375c0 ORR	X12, XZR, X15

(757) 0x4375c4 CMP	X13, X15

(757) 0x4375c8 B.EQ	437628

(757) 0x4375cc LDP	X15, X13, [SP, #16]

(757) 0x4375d0 ADD	X13, X13, X12,LSL #3

(757) 0x4375d4 ADD	X15, X15, X12,LSL #3

(757) 0x4375d8 HINT	#0

(757) 0x4375dc HINT	#0

  (765) 0x4375e0 LDR	X16, [X28]

  (765) 0x4375e4 ADD	X18, X12, #1

  (765) 0x4375e8 LDR	X16, [X1, X16,LSL #3]

  (765) 0x4375ec LDR	X16, [X16, X9,LSL #3]

  (765) 0x4375f0 STR	X12, [X22, X16,LSL #3]

  (765) 0x4375f4 STP	XZR, XZR, [X13, #1016]

  (765) 0x4375f8 STUR	X16, [X15, #504]

  (765) 0x4375fc ADD	X13, X13, #16

  (765) 0x437600 ADD	X12, X12, #2

  (765) 0x437604 LDR	X16, [X28]

  (765) 0x437608 LDR	X16, [X1, X16,LSL #3]

  (765) 0x43760c ADD	X16, X16, X9,LSL #3

  (765) 0x437610 ADD	X9, X9, #2

  (765) 0x437614 LDR	X16, [X16, #8]

  (765) 0x437618 CMP	X10, X9

  (765) 0x43761c STR	X18, [X22, X16,LSL #3]

  (765) 0x437620 STR	X16, [X15], #16

  (765) 0x437624 B.NE	4375e0

(757) 0x437628 LDR	X9, [X2, X11,LSL #3]

(757) 0x43762c LDR	X10, [X2, X8,LSL #3]

(757) 0x437630 B	437644

0x437634 HINT	#0

0x437638 HINT	#0

0x43763c HINT	#0

  (764) 0x437640 ADD	X9, X9, #1

  (764) 0x437644 CMP	X9, X10

  (764) 0x437648 B.GE	437680

  (764) 0x43764c LDR	X12, [X3, X9,LSL #3]

  (764) 0x437650 LDR	X15, [X28]

  (764) 0x437654 LDR	X13, [X4, X12,LSL #3]

  (764) 0x437658 SUB	X15, X15, #1

  (764) 0x43765c CMP	X13, X15

  (764) 0x437660 B.NE	437640

  (764) 0x437664 STR	X11, [X19, X12,LSL #3]

  (764) 0x437668 LDR	X10, [X2, X8,LSL #3]

  (764) 0x43766c B	437640

0x437670 HINT	#0

0x437674 HINT	#0

0x437678 HINT	#0

0x43767c HINT	#0

(757) 0x437680 LDR	X9, [X5, X11,LSL #3]

(757) 0x437684 LDR	X10, [X5, X8,LSL #3]

(757) 0x437688 B	437690

  (763) 0x43768c ADD	X9, X9, #1

  (763) 0x437690 CMP	X9, X10

  (763) 0x437694 B.GE	4376c0

  (763) 0x437698 LDR	X12, [X6, X9,LSL #3]

  (763) 0x43769c LDR	X15, [X28]

  (763) 0x4376a0 LDR	X13, [X7, X12,LSL #3]

  (763) 0x4376a4 SUB	X15, X15, #1

  (763) 0x4376a8 CMP	X13, X15

  (763) 0x4376ac B.NE	43768c

  (763) 0x4376b0 STR	X11, [X20, X12,LSL #3]

  (763) 0x4376b4 LDR	X10, [X5, X8,LSL #3]

  (763) 0x4376b8 B	43768c

0x4376bc HINT	#0

(757) 0x4376c0 LDUR	X9, [X29, #352]

(757) 0x4376c4 MOVI	D2, #0

(757) 0x4376c8 LDR	X10, [X9, X11,LSL #3]

(757) 0x4376cc LDR	X12, [X9, X8,LSL #3]

(757) 0x4376d0 ADD	X13, X10, #1

(757) 0x4376d4 STUR	X10, [X29, #464]

(757) 0x4376d8 CMP	X13, X12

(757) 0x4376dc B.GE	437924

(757) 0x4376e0 LDR	X9, [SP, #64]

(757) 0x4376e4 MOVI	D1, #0

(757) 0x4376e8 LDR	X16, [X9]

(757) 0x4376ec LDP	X10, X9, [X29, #960]

(757) 0x4376f0 LDR	X25, [X10]

(757) 0x4376f4 LDR	X10, [SP, #160]

(757) 0x4376f8 LDR	X9, [X9]

(757) 0x4376fc LDR	X6, [X10]

(757) 0x437700 LDR	X10, [SP, #144]

(757) 0x437704 LDR	X4, [X10]

(757) 0x437708 LDUR	X10, [X29, #480]

(757) 0x43770c LDR	X23, [X10]

(757) 0x437710 LDR	X10, [SP, #152]

(757) 0x437714 ADD	X5, X4, #8

(757) 0x437718 LDR	X27, [X10]

(757) 0x43771c LDUR	X10, [X29, #488]

(757) 0x437720 ADD	X7, X23, #8

(757) 0x437724 LDR	X10, [X10]

(757) 0x437728 B	43774c

  (760) 0x43772c LDR	D3, [X6, X13,LSL #3]

  (760) 0x437730 FADD	D1, D3, D1

  (760) 0x437734 HINT	#0

  (760) 0x437738 HINT	#0

  (760) 0x43773c HINT	#0

  (760) 0x437740 ADD	X13, X13, #1

  (760) 0x437744 CMP	X13, X12

  (760) 0x437748 B.EQ	437928

  (760) 0x43774c LDUR	X15, [X29, #496]

  (760) 0x437750 LDR	X0, [X15, X13,LSL #3]

  (760) 0x437754 LDR	X15, [X19, X0,LSL #3]

  (760) 0x437758 CMP	X15, X11

  (760) 0x43775c B.NE	43778c

  (760) 0x437760 ADD	X1, X0, #1

  (760) 0x437764 LDR	X15, [X14, X0,LSL #3]

  (760) 0x437768 LDR	X3, [X14, X1,LSL #3]

  (760) 0x43776c CMP	X3, X15

  (760) 0x437770 B.LE	437858

  (760) 0x437774 SUB	W2, W3, W15

  (760) 0x437778 ADD	X18, X15, #1

  (760) 0x43777c TBNZ	W2, #0, 4377b4

  (760) 0x437780 CMP	X3, X18

  (760) 0x437784 B.NE	4377e8

  (760) 0x437788 B	437858

  (760) 0x43778c LDR	X15, [X16, X0,LSL #3]

  (760) 0x437790 CMN	X15, #3

  (760) 0x437794 B.EQ	437740

  (760) 0x437798 CMP	X25, #1

  (760) 0x43779c B.EQ	43772c

  (760) 0x4377a0 LDR	X15, [X9, X11,LSL #3]

  (760) 0x4377a4 LDR	X18, [X9, X0,LSL #3]

  (760) 0x4377a8 CMP	X15, X18

  (760) 0x4377ac B.EQ	43772c

  (760) 0x4377b0 B	437740

  (760) 0x4377b4 LDR	X2, [X4, X15,LSL #3]

  (760) 0x4377b8 LDR	D0, [X6, X13,LSL #3]

  (760) 0x4377bc LDR	D3, [X23, X15,LSL #3]

  (760) 0x4377c0 FMUL	D0, D3, D0

  (760) 0x4377c4 LDR	X15, [X21, X2,LSL #3]

  (760) 0x4377c8 LDR	D3, [X23, X15,LSL #3]

  (760) 0x4377cc FADD	D2, D0, D2

  (760) 0x4377d0 FADD	D1, D0, D1

  (760) 0x4377d4 FADD	D3, D3, D0

  (760) 0x4377d8 STR	D3, [X23, X15,LSL #3]

  (760) 0x4377dc ORR	X15, XZR, X18

  (760) 0x4377e0 CMP	X3, X18

  (760) 0x4377e4 B.EQ	437858

  (760) 0x4377e8 SUB	X3, X3, X15

  (760) 0x4377ec ADD	X26, X5, X15,LSL #3

  (760) 0x4377f0 ADD	X24, X7, X15,LSL #3

  (760) 0x4377f4 HINT	#0

  (760) 0x4377f8 HINT	#0

  (760) 0x4377fc HINT	#0

    (762) 0x437800 LDP	X15, X18, [X26, #1016]

    (762) 0x437804 LDR	D0, [X6, X13,LSL #3]

    (762) 0x437808 SUBS	X3, X3, #2

    (762) 0x43780c ADD	X26, X26, #16

    (762) 0x437810 LDUR	D3, [X24, #504]

    (762) 0x437814 FMUL	D0, D3, D0

    (762) 0x437818 LDR	X15, [X21, X15,LSL #3]

    (762) 0x43781c LDR	D3, [X23, X15,LSL #3]

    (762) 0x437820 FADD	D2, D0, D2

    (762) 0x437824 FADD	D1, D0, D1

    (762) 0x437828 FADD	D3, D3, D0

    (762) 0x43782c STR	D3, [X23, X15,LSL #3]

    (762) 0x437830 LDR	X15, [X21, X18,LSL #3]

    (762) 0x437834 LDR	D0, [X6, X13,LSL #3]

    (762) 0x437838 LDR	D3, [X24], #16

    (762) 0x43783c FMUL	D0, D3, D0

    (762) 0x437840 LDR	D3, [X23, X15,LSL #3]

    (762) 0x437844 FADD	D2, D0, D2

    (762) 0x437848 FADD	D1, D0, D1

    (762) 0x43784c FADD	D3, D3, D0

    (762) 0x437850 STR	D3, [X23, X15,LSL #3]

    (762) 0x437854 B.NE	437800

  (760) 0x437858 LDR	X15, [X17, X0,LSL #3]

  (760) 0x43785c LDR	X0, [X17, X1,LSL #3]

  (760) 0x437860 CMP	X0, X15

  (760) 0x437864 B.LE	437740

  (760) 0x437868 SUB	W1, W0, W15

  (760) 0x43786c ADD	X18, X15, #1

  (760) 0x437870 TBNZ	W1, #0, 437880

  (760) 0x437874 CMP	X0, X18

  (760) 0x437878 B.EQ	437740

  (760) 0x43787c B	4378b4

  (760) 0x437880 LDR	X1, [X27, X15,LSL #3]

  (760) 0x437884 LDR	D0, [X6, X13,LSL #3]

  (760) 0x437888 LDR	D3, [X10, X15,LSL #3]

  (760) 0x43788c FMUL	D0, D3, D0

  (760) 0x437890 LDR	X15, [X22, X1,LSL #3]

  (760) 0x437894 LDR	D3, [X10, X15,LSL #3]

  (760) 0x437898 FADD	D2, D0, D2

  (760) 0x43789c FADD	D1, D0, D1

  (760) 0x4378a0 FADD	D3, D3, D0

  (760) 0x4378a4 STR	D3, [X10, X15,LSL #3]

  (760) 0x4378a8 ORR	X15, XZR, X18

  (760) 0x4378ac CMP	X0, X18

  (760) 0x4378b0 B.EQ	437740

  (760) 0x4378b4 ADD	X18, X27, #8

  (760) 0x4378b8 SUB	X0, X0, X15

  (760) 0x4378bc ADD	X1, X18, X15,LSL #3

  (760) 0x4378c0 ADD	X18, X10, #8

  (760) 0x4378c4 ADD	X3, X18, X15,LSL #3

    (761) 0x4378c8 LDP	X15, X18, [X1, #1016]

    (761) 0x4378cc LDR	D0, [X6, X13,LSL #3]

    (761) 0x4378d0 SUBS	X0, X0, #2

    (761) 0x4378d4 ADD	X1, X1, #16

    (761) 0x4378d8 LDUR	D3, [X3, #504]

    (761) 0x4378dc FMUL	D0, D3, D0

    (761) 0x4378e0 LDR	X15, [X22, X15,LSL #3]

    (761) 0x4378e4 LDR	D3, [X10, X15,LSL #3]

    (761) 0x4378e8 FADD	D2, D0, D2

    (761) 0x4378ec FADD	D1, D0, D1

    (761) 0x4378f0 FADD	D3, D3, D0

    (761) 0x4378f4 STR	D3, [X10, X15,LSL #3]

    (761) 0x4378f8 LDR	X15, [X22, X18,LSL #3]

    (761) 0x4378fc LDR	D0, [X6, X13,LSL #3]

    (761) 0x437900 LDR	D3, [X3], #16

    (761) 0x437904 FMUL	D0, D3, D0

    (761) 0x437908 LDR	D3, [X10, X15,LSL #3]

    (761) 0x43790c FADD	D2, D0, D2

    (761) 0x437910 FADD	D1, D0, D1

    (761) 0x437914 FADD	D3, D3, D0

    (761) 0x437918 STR	D3, [X10, X15,LSL #3]

    (761) 0x43791c B.NE	4378c8

  (760) 0x437920 B	437740

(757) 0x437924 MOVI	D1, #0

(757) 0x437928 LDUR	X10, [X29, #344]

(757) 0x43792c LDR	X9, [X10, X11,LSL #3]

(757) 0x437930 LDR	X10, [X10, X8,LSL #3]

(757) 0x437934 CMP	X9, X10

(757) 0x437938 B.GE	437aa0

(757) 0x43793c LDR	X15, [SP, #128]

(757) 0x437940 LDP	X12, X13, [SP, #72]

(757) 0x437944 LDR	X3, [X28]

(757) 0x437948 LDR	X16, [X15]

(757) 0x43794c LDUR	X15, [X29, #448]

(757) 0x437950 LDR	X12, [X12]

(757) 0x437954 LDR	X13, [X13]

(757) 0x437958 LDR	X6, [X15]

(757) 0x43795c LDR	X15, [SP, #136]

(757) 0x437960 LDR	X23, [X15]

(757) 0x437964 LDUR	X15, [X29, #456]

(757) 0x437968 LDR	X24, [X15]

(757) 0x43796c LDR	X15, [SP, #112]

(757) 0x437970 LDR	X25, [X15]

(757) 0x437974 LDR	X15, [SP, #88]

(757) 0x437978 LDR	X27, [X15]

(757) 0x43797c LDR	X15, [SP, #96]

(757) 0x437980 LDR	X26, [X15]

(757) 0x437984 LDR	X15, [SP, #104]

(757) 0x437988 LDR	X0, [X15]

(757) 0x43798c LDR	X15, [SP, #120]

(757) 0x437990 LDR	X1, [X15]

(757) 0x437994 B	4379b4

0x437998 HINT	#0

0x43799c HINT	#0

  (758) 0x4379a0 LDR	D3, [X25, X9,LSL #3]

  (758) 0x4379a4 FADD	D1, D3, D1

  (758) 0x4379a8 ADD	X9, X9, #1

  (758) 0x4379ac CMP	X9, X10

  (758) 0x4379b0 B.EQ	437aa0

  (758) 0x4379b4 ADD	X15, X13, X9,LSL #3

  (758) 0x4379b8 CBZ	X30, 4379c4

  (758) 0x4379bc LDR	X15, [X15]

  (758) 0x4379c0 ADD	X15, X12, X15,LSL #3

  (758) 0x4379c4 LDR	X15, [X15]

  (758) 0x4379c8 TBNZ	X15, #63, 437a6c

  (758) 0x4379cc LDR	X18, [X20, X15,LSL #3]

  (758) 0x4379d0 CMP	X18, X11

  (758) 0x4379d4 B.NE	437a6c

  (758) 0x4379d8 ADD	X18, X26, X15,LSL #3

  (758) 0x4379dc LDR	X18, [X18, #8]

  (758) 0x4379e0 CMP	X18, #1

  (758) 0x4379e4 B.LT	4379a8

  (758) 0x4379e8 UBFM	X15, X15, #61, #60

  (758) 0x4379ec LDR	X2, [X27, X15]

  (758) 0x4379f0 LDR	X15, [X0, X3,LSL #3]

  (758) 0x4379f4 ADD	X4, X18, X2

  (758) 0x4379f8 LDP	X18, X7, [X29, #992]

  (758) 0x4379fc LDR	X5, [X7]

  (758) 0x437a00 LDR	X18, [X18]

  (758) 0x437a04 B	437a30

    (759) 0x437a08 ORN	X7, XZR, X7

    (759) 0x437a0c LDR	X7, [X21, X7,LSL #3]

    (759) 0x437a10 LDR	D3, [X18, X7,LSL #3]

    (759) 0x437a14 FADD	D3, D3, D0

    (759) 0x437a18 STR	D3, [X18, X7,LSL #3]

    (759) 0x437a1c FADD	D2, D0, D2

    (759) 0x437a20 FADD	D1, D0, D1

    (759) 0x437a24 ADD	X2, X2, #1

    (759) 0x437a28 CMP	X2, X4

    (759) 0x437a2c B.GE	4379a8

    (759) 0x437a30 LDR	D0, [X25, X9,LSL #3]

    (759) 0x437a34 LDR	D3, [X1, X2,LSL #3]

    (759) 0x437a38 LDR	X7, [X15, X2,LSL #3]

    (759) 0x437a3c FMUL	D0, D3, D0

    (759) 0x437a40 TBNZ	X7, #63, 437a08

    (759) 0x437a44 LDR	X7, [X22, X7,LSL #3]

    (759) 0x437a48 LDR	D3, [X5, X7,LSL #3]

    (759) 0x437a4c FADD	D3, D3, D0

    (759) 0x437a50 STR	D3, [X5, X7,LSL #3]

    (759) 0x437a54 FADD	D2, D0, D2

    (759) 0x437a58 FADD	D1, D0, D1

    (759) 0x437a5c ADD	X2, X2, #1

    (759) 0x437a60 CMP	X2, X4

    (759) 0x437a64 B.LT	437a30

  (758) 0x437a68 B	4379a8

  (758) 0x437a6c LDR	X18, [X16, X15,LSL #3]

  (758) 0x437a70 CMN	X18, #3

  (758) 0x437a74 B.EQ	4379a8

  (758) 0x437a78 CMP	X6, #1

  (758) 0x437a7c B.EQ	4379a0

  (758) 0x437a80 LDR	X15, [X23, X15,LSL #3]

  (758) 0x437a84 LDR	X18, [X24, X11,LSL #3]

  (758) 0x437a88 CMP	X15, X18

  (758) 0x437a8c B.EQ	4379a0

  (758) 0x437a90 B	4379a8

0x437a94 HINT	#0

0x437a98 HINT	#0

0x437a9c HINT	#0

(757) 0x437aa0 LDR	X9, [SP, #184]

(757) 0x437aa4 LDUR	X10, [X29, #464]

(757) 0x437aa8 LDR	D3, [X9, X10,LSL #3]

(757) 0x437aac FMUL	D2, D3, D2

(757) 0x437ab0 FCMP	D2, #0

(757) 0x437ab4 B.EQ	437ac0

(757) 0x437ab8 FNEG	D0, D1

(757) 0x437abc FDIV	D0, D0, D2

(757) 0x437ac0 LDR	X15, [X14, X11,LSL #3]

(757) 0x437ac4 LDR	X9, [X14, X8,LSL #3]

(757) 0x437ac8 LDUR	X0, [X29, #424]

(757) 0x437acc SUBS	X10, X9, X15

(757) 0x437ad0 LDP	X2, X1, [X29, #912]

(757) 0x437ad4 LDP	X4, X3, [X29, #896]

(757) 0x437ad8 LDP	X6, X5, [X29, #880]

(757) 0x437adc LDUR	X7, [X29, #360]

(757) 0x437ae0 B.LE	437b54

(757) 0x437ae4 CMP	X10, #4

(757) 0x437ae8 ORR	X12, XZR, X15

(757) 0x437aec B.CC	437b28

(757) 0x437af0 LDR	X16, [SP, #8]

(757) 0x437af4 AND	X13, X10, #0x0

(757) 0x437af8 ADD	X12, X15, X13

(757) 0x437afc ADD	X15, X16, X15,LSL #3

(757) 0x437b00 AND	X16, X10, #0x0

  (770) 0x437b04 LDP	Q1, Q2, [X15, #2032]

  (770) 0x437b08 SUBS	X16, X16, #4

  (770) 0x437b0c FMUL	V2.2D, V2.2D, V0.D[0]

  (770) 0x437b10 FMUL	V1.2D, V1.2D, V0.D[0]

  (770) 0x437b14 STP	Q1, Q2, [X15, #2032]

  (770) 0x437b18 ADD	X15, X15, #32

  (770) 0x437b1c B.NE	437b04

(757) 0x437b20 CMP	X10, X13

(757) 0x437b24 B.EQ	437b54

(757) 0x437b28 LDR	X10, [SP, #176]

(757) 0x437b2c SUB	X9, X9, X12

(757) 0x437b30 ADD	X10, X10, X12,LSL #3

(757) 0x437b34 HINT	#0

(757) 0x437b38 HINT	#0

(757) 0x437b3c HINT	#0

  (769) 0x437b40 LDR	D1, [X10]

  (769) 0x437b44 SUBS	X9, X9, #1

  (769) 0x437b48 FMUL	D1, D1, D0

  (769) 0x437b4c STR	D1, [X10], #8

  (769) 0x437b50 B.NE	437b40

(757) 0x437b54 LDR	X12, [X17, X11,LSL #3]

(757) 0x437b58 LDR	X8, [X17, X8,LSL #3]

(757) 0x437b5c SUBS	X9, X8, X12

(757) 0x437b60 B.LE	4374a0

(757) 0x437b64 CMP	X9, #4

(757) 0x437b68 ORR	X10, XZR, X12

(757) 0x437b6c B.CC	437ba8

(757) 0x437b70 LDR	X13, [SP]

(757) 0x437b74 AND	X11, X9, #0x0

(757) 0x437b78 ADD	X10, X12, X11

(757) 0x437b7c ADD	X12, X13, X12,LSL #3

(757) 0x437b80 AND	X13, X9, #0x0

  (768) 0x437b84 LDP	Q1, Q2, [X12, #2032]

  (768) 0x437b88 SUBS	X13, X13, #4

  (768) 0x437b8c FMUL	V2.2D, V2.2D, V0.D[0]

  (768) 0x437b90 FMUL	V1.2D, V1.2D, V0.D[0]

  (768) 0x437b94 STP	Q1, Q2, [X12, #2032]

  (768) 0x437b98 ADD	X12, X12, #32

  (768) 0x437b9c B.NE	437b84

(757) 0x437ba0 CMP	X9, X11

(757) 0x437ba4 B.EQ	4374a0

(757) 0x437ba8 LDR	X9, [SP, #168]

(757) 0x437bac SUB	X8, X8, X10

(757) 0x437bb0 ADD	X9, X9, X10,LSL #3

(757) 0x437bb4 HINT	#0

(757) 0x437bb8 HINT	#0

(757) 0x437bbc HINT	#0

  (767) 0x437bc0 LDR	D1, [X9]

  (767) 0x437bc4 SUBS	X8, X8, #1

  (767) 0x437bc8 FMUL	D1, D1, D0

  (767) 0x437bcc STR	D1, [X9], #8

  (767) 0x437bd0 B.NE	437bc0

(757) 0x437bd4 B	4374a0

0x437bd8 ORR	X0, XZR, X19

0x437bdc BL	4ac5b0

0x437be0 ORR	X0, XZR, X20

0x437be4 BL	4ac5b0

0x437be8 ORR	X0, XZR, X21

0x437bec BL	4ac5b0

0x437bf0 ORR	X0, XZR, X22

0x437bf4 LDP	X20, X19, [SP, #448]

0x437bf8 LDP	X22, X21, [SP, #432]

0x437bfc LDP	X24, X23, [SP, #416]

0x437c00 LDP	X26, X25, [SP, #400]

0x437c04 LDP	X28, X27, [SP, #384]

0x437c08 LDP	X29, X30, [SP, #368]

0x437c0c ADD	SP, SP, #464

0x437c10 B	4ac5b0

0x437c14 HINT	#0

0x437c18 HINT	#0

0x437c1c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.45+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.55+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1884	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:785	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 30% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 46.00 to 10.62 cycles (4.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1748
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1751
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1754
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1756
hypre_Free: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1879
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1880
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1766
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1767

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	225
nb uops	205
loop length	900
used w registers	1
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	34

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.63 cycles
front end	25.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	46.00	46.00	46.00	25.00	25.00
cycles	10.00	10.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	46.00	46.00	46.00	25.00	25.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	25.63
Dispatch	46.00
DIV/SQRT	5.00-20.00
Overall L1	46.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	26%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 437170

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X7, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X22, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X11, X9, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X10, X9, [X29, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X11, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X9, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X10, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X23, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X28, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X10, X8, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 4372b4 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 4372c0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 4372cc <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4372d0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X0, 437290 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X0, 4372a4 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X0, X8, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 437314 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43733c <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ae1b0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ae190 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MUL X8, X10, X24	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437bd8 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0xa68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X12, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X11, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X9, X11, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X12, X15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X16, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X8, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X8, X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X13, X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X8, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X10, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X8, X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X2, X1, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X4, X3, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X6, X5, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X7, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 4374b4 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ac5b0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ac5b0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ac5b0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X19, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ac5b0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1748
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1751
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1754
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1756
hypre_Free: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1879
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1880
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1766
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1767

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	225
nb uops	205
loop length	900
used w registers	1
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	34

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.63 cycles
front end	25.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	46.00	46.00	46.00	25.00	25.00
cycles	10.00	10.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	46.00	46.00	46.00	25.00	25.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	25.63
Dispatch	46.00
DIV/SQRT	5.00-20.00
Overall L1	46.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	26%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 437170

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X7, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X22, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X11, X9, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X10, X9, [X29, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X11, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X9, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X10, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X23, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X28, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X10, X8, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 4372b4 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 4372c0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 4372cc <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4372d0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X0, 437290 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X0, 4372a4 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X0, X8, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 437314 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43733c <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ae1b0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ae190 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MUL X8, X10, X24	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437bd8 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0xa68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X12, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X11, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X9, X11, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X12, X15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X16, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X8, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X8, X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X13, X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X8, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X10, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X8, X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X2, X1, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X4, X3, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X6, X5, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X7, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 4374b4 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ac5b0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ac5b0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ac5b0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X19, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ac5b0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.omp_outlined.19–	1.14	0.55
○Loop 772 - par_multi_interp.c:1760-1761 - exec	0.17	0.06
▼Loop 757 - par_multi_interp.c:1774-1876 - exec–	0.13	0.04
▼Loop 760 - par_multi_interp.c:1811-1837 - exec–	0.54	0.18
○Loop 762 - par_multi_interp.c:1816-1822 - exec	0.03	0.01
○Loop 761 - par_multi_interp.c:1824-1830 - exec	0.00	0.00
○Loop 764 - par_multi_interp.c:1799-1803 - exec	0.26	0.09
○Loop 766 - par_multi_interp.c:1782-1787 - exec	0.02	0.01
○Loop 769 - par_multi_interp.c:1873-1874 - exec	0.00	0.01
▼Loop 758 - par_multi_interp.c:1840-1867 - exec–	0.00	0.00
○Loop 759 - par_multi_interp.c:1851-1860 - exec	0.00	0.00
○Loop 770 - par_multi_interp.c:1873-1874 - exec	0.00	0.00
○Loop 768 - par_multi_interp.c:1875-1876 - exec	0.00	0.00
○Loop 765 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
○Loop 767 - par_multi_interp.c:1875-1876 - exec	0.00	0.00
○Loop 763 - par_multi_interp.c:1805-1809 - exec	0.00	0.00
○Loop 771 - par_multi_interp.c:1762-1763 - exec	0.00	0.00

Report Configuration

Vectorization

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Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code