OV - exec - Function hypre_BoomerAMGCreateS.omp

	Function: hypre_BoomerAMGCreateS.omp_outlined.1	Module: exec	Source: par_strength.c:246-513 [...]	Coverage (incl. loops): 0.20% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 246 - 513

--------------------------------------------------------------------------------

246: #pragma omp parallel private(i,diag,row_scale,row_sum,jA,jS)

247: #endif

248:    {

249:    HYPRE_Int start, stop;

250:    hypre_GetSimpleThreadPartition(&start, &stop, num_variables);

251:    HYPRE_Int jS_diag = 0, jS_offd = 0;

252:

253:    for (i = start; i < stop; i++)

254:    {

255:       S_diag_i[i] = jS_diag;

256:       if (num_cols_offd)

257:       {

258:          S_offd_i[i] = jS_offd;

259:       }

260:

261:       diag = A_diag_data[A_diag_i[i]];

262:

263:       /* compute scaling factor and row sum */

264:       row_scale = 0.0;

265:       row_sum = diag;

266:       if (num_functions > 1)

267:       {

268:          if (diag < 0)

269:          {

270:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

271:             {

272:                if (dof_func[i] == dof_func[A_diag_j[jA]])

273:                {

274:                   row_scale = hypre_max(row_scale, A_diag_data[jA]);

275:                   row_sum += A_diag_data[jA];

276:                }

277:             }

278:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

279:             {

280:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

281:                {

282:                   row_scale = hypre_max(row_scale, A_offd_data[jA]);

283:                   row_sum += A_offd_data[jA];

[...]

289:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

290:             {

291:                if (dof_func[i] == dof_func[A_diag_j[jA]])

292:                {

293:                   row_scale = hypre_min(row_scale, A_diag_data[jA]);

294:                   row_sum += A_diag_data[jA];

295:                }

296:             }

297:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

298:             {

299:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

300:                {

301:                   row_scale = hypre_min(row_scale, A_offd_data[jA]);

302:                   row_sum += A_offd_data[jA];

[...]

309:          if (diag < 0)

310:          {

311:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

312:             {

313:                row_scale = hypre_max(row_scale, A_diag_data[jA]);

314:                row_sum += A_diag_data[jA];

315:             }

316:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

317:             {

318:                row_scale = hypre_max(row_scale, A_offd_data[jA]);

319:                row_sum += A_offd_data[jA];

320:             }

321:          }

322:          else

323:          {

324:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

325:             {

326:                row_scale = hypre_min(row_scale, A_diag_data[jA]);

327:                row_sum += A_diag_data[jA];

328:             }

329:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

330:             {

331:                row_scale = hypre_min(row_scale, A_offd_data[jA]);

332:                row_sum += A_offd_data[jA];

333:             }

334:          } /* diag >= 0*/

335:       } /* num_functions <= 1 */

336:

337:       jS_diag += A_diag_i[i + 1] - A_diag_i[i] - 1;

338:       jS_offd += A_offd_i[i + 1] - A_offd_i[i];

339:

340:       /* compute row entries of S */

341:       S_temp_diag_j[A_diag_i[i]] = -1;

342:       if ((fabs(row_sum) > fabs(diag)*max_row_sum) && (max_row_sum < 1.0))

343:       {

344:          /* make all dependencies weak */

345:          for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

346:          {

347:             S_temp_diag_j[jA] = -1;

348:          }

349:          jS_diag -= A_diag_i[i + 1] - (A_diag_i[i] + 1);

350:

351:          for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

352:          {

353:             S_temp_offd_j[jA] = -1;

354:          }

355:          jS_offd -= A_offd_i[i + 1] - A_offd_i[i];

356:       }

357:       else

358:       {

359:          if (num_functions > 1)

360:          {

361:             if (diag < 0)

362:             {

363:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

364:                {

365:                   if (A_diag_data[jA] <= strength_threshold * row_scale

366:                       || dof_func[i] != dof_func[A_diag_j[jA]])

367:                   {

368:                      S_temp_diag_j[jA] = -1;

369:                      --jS_diag;

370:                   }

371:                   else

372:                   {

373:                      S_temp_diag_j[jA] = A_diag_j[jA];

374:                   }

375:                }

376:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

377:                {

378:                   if (A_offd_data[jA] <= strength_threshold * row_scale

379:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

380:                   {

381:                      S_temp_offd_j[jA] = -1;

382:                      --jS_offd;

383:                   }

384:                   else

385:                   {

386:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

392:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

393:                {

394:                   if (A_diag_data[jA] >= strength_threshold * row_scale

395:                       || dof_func[i] != dof_func[A_diag_j[jA]])

396:                   {

397:                      S_temp_diag_j[jA] = -1;

398:                      --jS_diag;

399:                   }

400:                   else

401:                   {

402:                      S_temp_diag_j[jA] = A_diag_j[jA];

403:                   }

404:                }

405:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

406:                {

407:                   if (A_offd_data[jA] >= strength_threshold * row_scale

408:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

409:                   {

410:                      S_temp_offd_j[jA] = -1;

411:                      --jS_offd;

412:                   }

413:                   else

414:                   {

415:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

422:             if (diag < 0)

423:             {

424:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

425:                {

426:                   if (A_diag_data[jA] <= strength_threshold * row_scale)

427:                   {

428:                      S_temp_diag_j[jA] = -1;

429:                      --jS_diag;

430:                   }

431:                   else

432:                   {

433:                      S_temp_diag_j[jA] = A_diag_j[jA];

434:                   }

435:                }

436:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

437:                {

438:                   if (A_offd_data[jA] <= strength_threshold * row_scale)

439:                   {

440:                      S_temp_offd_j[jA] = -1;

441:                      --jS_offd;

442:                   }

443:                   else

444:                   {

445:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

451:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

452:                {

453:                   if (A_diag_data[jA] >= strength_threshold * row_scale)

454:                   {

455:                      S_temp_diag_j[jA] = -1;

456:                      --jS_diag;

457:                   }

458:                   else

459:                   {

460:                      S_temp_diag_j[jA] = A_diag_j[jA];

461:                   }

462:                }

463:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

464:                {

465:                   if (A_offd_data[jA] >= strength_threshold * row_scale)

466:                   {

467:                      S_temp_offd_j[jA] = -1;

468:                      --jS_offd;

469:                   }

470:                   else

471:                   {

472:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

480:    hypre_prefix_sum_pair(&jS_diag, S_diag_i + num_variables, &jS_offd, S_offd_i + num_variables, prefix_sum_workspace);

[...]

492:    for (i = start; i < stop; i++)

493:    {

494:       S_diag_i[i] += jS_diag;

495:       S_offd_i[i] += jS_offd;

496:

497:       jS = S_diag_i[i];

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

501:          {

502:             S_diag_j[jS]    = S_temp_diag_j[jA];

503:             jS++;

504:          }

505:       }

506:

507:       jS = S_offd_i[i];

508:       for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

509:       {

510:          if (S_temp_offd_j[jA] > -1)

511:          {

512:             S_offd_j[jS]    = S_temp_offd_j[jA];

513:             jS++;

0x467560 SUB	SP, SP, #240

0x467564 STP	X29, X30, [SP, #144]

0x467568 STP	X28, X27, [SP, #160]

0x46756c STP	X26, X25, [SP, #176]

0x467570 STP	X24, X23, [SP, #192]

0x467574 STP	X22, X21, [SP, #208]

0x467578 STP	X20, X19, [SP, #224]

0x46757c ADD	X29, SP, #144

0x467580 LDR	X8, [X29, #184]

0x467584 STR	X2, [SP, #8]

0x467588 LDR	X2, [X2]

0x46758c SUB	X0, X29, #16

0x467590 SUB	X1, X29, #24

0x467594 ORR	X24, XZR, X6

0x467598 ORR	X22, XZR, X4

0x46759c LDR	X25, [X29, #168]

0x4675a0 STR	X7, [SP, #40]

0x4675a4 STUR	X5, [X29, #456]

0x4675a8 ORR	X19, XZR, X3

0x4675ac STR	X8, [SP, #16]

0x4675b0 LDR	X8, [X29, #152]

0x4675b4 STR	X8, [SP, #24]

0x4675b8 LDR	X8, [X29, #120]

0x4675bc STR	X8, [SP, #32]

0x4675c0 BL	4ae1d0

0x4675c4 LDP	X9, X12, [X29, #1000]

0x4675c8 LDR	X8, [X19]

0x4675cc CMP	X12, X9

0x4675d0 STP	XZR, XZR, [X29, #984]

0x4675d4 STR	X19, [SP]

0x4675d8 B.GE	46816c

0x4675dc LDR	X5, [X29, #128]

0x4675e0 LDR	X11, [X29, #176]

0x4675e4 LDR	X14, [X29, #160]

0x4675e8 MOVI	D2, #0

0x4675ec FMOV	D3, #1.0000000

0x4675f0 MOVN	X26, #0

0x4675f4 ORR	X9, XZR, XZR

0x4675f8 ORR	X10, XZR, XZR

0x4675fc LDP	X16, X15, [X29, #104]

0x467600 LDP	X13, X3, [X29, #136]

0x467604 LDUR	X18, [X29, #456]

0x467608 LDR	X17, [X29, #96]

0x46760c LDR	X0, [X24]

0x467610 LDR	X30, [X25]

0x467614 STUR	X5, [X29, #448]

0x467618 LDP	X2, X1, [SP, #32]

0x46761c LDR	X6, [X5]

0x467620 LDR	X5, [SP, #24]

0x467624 LDR	X7, [X15]

0x467628 LDR	D0, [X14]

0x46762c LDR	D1, [X11]

0x467630 ADD	X11, X7, #8

0x467634 LDR	X19, [X13]

0x467638 LDR	X18, [X18]

0x46763c LDR	X1, [X1]

0x467640 LDR	X2, [X2]

0x467644 STUR	X3, [X29, #464]

0x467648 LDR	X3, [X3]

0x46764c LDR	X4, [X16]

0x467650 LDR	X24, [X5]

0x467654 STP	X19, X7, [SP, #64]

0x467658 STR	X11, [SP, #56]

0x46765c ADD	X11, X19, #8

0x467660 STR	X11, [SP, #48]

0x467664 B	467680

    (2131) 0x467668 SUB	X11, X11, X14

    (2131) 0x46766c ADD	X9, X11, X9

    (2131) 0x467670 STUR	X9, [X29, #472]

    (2131) 0x467674 LDUR	X11, [X29, #488]

    (2131) 0x467678 CMP	X12, X11

    (2131) 0x46767c B.GE	46816c

    (2131) 0x467680 STR	X10, [X8, X12,LSL #3]

    (2131) 0x467684 ORR	X27, XZR, X12

    (2131) 0x467688 LDR	X11, [X22]

    (2131) 0x46768c CBZ	X11, 467694

    (2131) 0x467690 STR	X9, [X18, X27,LSL #3]

    (2131) 0x467694 LDR	X19, [X1, X27,LSL #3]

    (2131) 0x467698 LDR	X11, [X17]

    (2131) 0x46769c ADD	X12, X27, #1

    (2131) 0x4676a0 MOVI	D5, #0

    (2131) 0x4676a4 LDR	X28, [X1, X12,LSL #3]

    (2131) 0x4676a8 LDR	D4, [X0, X19,LSL #3]

    (2131) 0x4676ac ADD	X20, X19, #1

    (2131) 0x4676b0 CMP	X11, #2

    (2131) 0x4676b4 B.LT	467720

    (2131) 0x4676b8 FCMP	D4, #0

    (2131) 0x4676bc B.GE	467800

    (2131) 0x4676c0 FMOV	D6, D4

    (2131) 0x4676c4 CMP	X20, X28

    (2131) 0x4676c8 B.GE	467940

    (2131) 0x4676cc LDR	X21, [X4, X27,LSL #3]

    (2131) 0x4676d0 MOVI	D5, #0

    (2131) 0x4676d4 SUB	W11, W19, W28

    (2131) 0x4676d8 TBNZ	W11, #0, 467920

    (2131) 0x4676dc LDR	X11, [SP, #72]

    (2131) 0x4676e0 MOVI	D5, #0

    (2131) 0x4676e4 FMOV	D6, D4

    (2131) 0x4676e8 LDR	X11, [X11, X20,LSL #3]

    (2131) 0x4676ec LDR	X11, [X4, X11,LSL #3]

    (2131) 0x4676f0 CMP	X21, X11

    (2131) 0x4676f4 B.NE	467704

    (2131) 0x4676f8 LDR	D6, [X0, X20,LSL #3]

    (2131) 0x4676fc FMAXNM	D5, D6, D2

    (2131) 0x467700 FADD	D6, D6, D4

    (2131) 0x467704 ADD	X20, X19, #2

    (2131) 0x467708 SUB	X11, X28, #2

    (2131) 0x46770c CMP	X11, X19

    (2131) 0x467710 B.EQ	467940

    (2131) 0x467714 B	467ac0

0x467718 HINT	#0

0x46771c HINT	#0

    (2131) 0x467720 FCMP	D4, #0

    (2131) 0x467724 B.GE	467860

    (2131) 0x467728 FMOV	D6, D4

    (2131) 0x46772c CMP	X20, X28

    (2131) 0x467730 B.GE	4677d4

    (2131) 0x467734 ORN	X11, XZR, X19

    (2131) 0x467738 MOVI	D5, #0

    (2131) 0x46773c FMOV	D6, D4

    (2131) 0x467740 ADD	X14, X28, X11

    (2131) 0x467744 CMP	X14, #4

    (2131) 0x467748 B.CC	4677b8

    (2131) 0x46774c MOVI	V6.2D, #0

    (2131) 0x467750 AND	X5, X14, #0x0

    (2131) 0x467754 MOVI	V5.2D, #0

    (2131) 0x467758 ADD	X11, X0, #24

    (2131) 0x46775c MOVI	V7.2D, #0

    (2131) 0x467760 MOVI	V16.2D, #0

    (2131) 0x467764 AND	X21, X14, #0x0

    (2131) 0x467768 ADD	X20, X20, X5

    (2131) 0x46776c ADD	X7, X11, X19,LSL #3

    (2131) 0x467770 MOV	V6.D[0], V4.D[0]

    (2131) 0x467774 HINT	#0

    (2131) 0x467778 HINT	#0

    (2131) 0x46777c HINT	#0

      (2139) 0x467780 LDP	Q17, Q18, [X7, #2032]

      (2139) 0x467784 ADD	X7, X7, #32

      (2139) 0x467788 SUBS	X21, X21, #4

      (2139) 0x46778c FMAXNM	V16.2D, V16.2D, V18.2D

      (2139) 0x467790 FADD	V5.2D, V18.2D, V5.2D

      (2139) 0x467794 FMAXNM	V7.2D, V7.2D, V17.2D

      (2139) 0x467798 FADD	V6.2D, V17.2D, V6.2D

      (2139) 0x46779c B.NE	467780

    (2131) 0x4677a0 FADD	V5.2D, V5.2D, V6.2D

    (2131) 0x4677a4 CMP	X14, X5

    (2131) 0x4677a8 FADDP	D6, V5.2D

    (2131) 0x4677ac FMAXNM	V5.2D, V7.2D, V16.2D

    (2131) 0x4677b0 FMAXNMP	D5, V5.2D

    (2131) 0x4677b4 B.EQ	4677d4

    (2131) 0x4677b8 SUB	X11, X28, X20

    (2131) 0x4677bc ADD	X14, X0, X20,LSL #3

      (2138) 0x4677c0 LDR	D7, [X14], #8

      (2138) 0x4677c4 SUBS	X11, X11, #1

      (2138) 0x4677c8 FMAXNM	D5, D5, D7

      (2138) 0x4677cc FADD	D6, D7, D6

      (2138) 0x4677d0 B.NE	4677c0

    (2131) 0x4677d4 LDR	X21, [X2, X27,LSL #3]

    (2131) 0x4677d8 LDR	X20, [X2, X12,LSL #3]

    (2131) 0x4677dc SUBS	X14, X20, X21

    (2131) 0x4677e0 B.LE	467cc0

    (2131) 0x4677e4 CMP	X14, #4

    (2131) 0x4677e8 B.CS	467978

    (2131) 0x4677ec ORR	X23, XZR, X21

    (2131) 0x4677f0 B	4679e0

0x4677f4 HINT	#0

0x4677f8 HINT	#0

0x4677fc HINT	#0

    (2131) 0x467800 FMOV	D6, D4

    (2131) 0x467804 CMP	X20, X28

    (2131) 0x467808 B.GE	467a0c

    (2131) 0x46780c LDR	X21, [X4, X27,LSL #3]

    (2131) 0x467810 MOVI	D5, #0

    (2131) 0x467814 SUB	W11, W19, W28

    (2131) 0x467818 TBNZ	W11, #0, 4679fc

    (2131) 0x46781c LDR	X11, [SP, #72]

    (2131) 0x467820 MOVI	D5, #0

    (2131) 0x467824 FMOV	D6, D4

    (2131) 0x467828 LDR	X11, [X11, X20,LSL #3]

    (2131) 0x46782c LDR	X11, [X4, X11,LSL #3]

    (2131) 0x467830 CMP	X21, X11

    (2131) 0x467834 B.NE	467844

    (2131) 0x467838 LDR	D6, [X0, X20,LSL #3]

    (2131) 0x46783c FMINNM	D5, D6, D2

    (2131) 0x467840 FADD	D6, D6, D4

    (2131) 0x467844 ADD	X20, X19, #2

    (2131) 0x467848 SUB	X11, X28, #2

    (2131) 0x46784c CMP	X11, X19

    (2131) 0x467850 B.EQ	467a0c

    (2131) 0x467854 B	467c0c

0x467858 HINT	#0

0x46785c HINT	#0

    (2131) 0x467860 FMOV	D6, D4

    (2131) 0x467864 CMP	X20, X28

    (2131) 0x467868 B.GE	467900

    (2131) 0x46786c ORN	X11, XZR, X19

    (2131) 0x467870 MOVI	D5, #0

    (2131) 0x467874 FMOV	D6, D4

    (2131) 0x467878 ADD	X14, X28, X11

    (2131) 0x46787c CMP	X14, #4

    (2131) 0x467880 B.CC	4678e4

    (2131) 0x467884 MOVI	V6.2D, #0

    (2131) 0x467888 AND	X5, X14, #0x0

    (2131) 0x46788c MOVI	V5.2D, #0

    (2131) 0x467890 ADD	X11, X0, #24

    (2131) 0x467894 MOVI	V7.2D, #0

    (2131) 0x467898 MOVI	V16.2D, #0

    (2131) 0x46789c AND	X21, X14, #0x0

    (2131) 0x4678a0 ADD	X20, X20, X5

    (2131) 0x4678a4 ADD	X7, X11, X19,LSL #3

    (2131) 0x4678a8 MOV	V6.D[0], V4.D[0]

      (2135) 0x4678ac LDP	Q17, Q18, [X7, #2032]

      (2135) 0x4678b0 ADD	X7, X7, #32

      (2135) 0x4678b4 SUBS	X21, X21, #4

      (2135) 0x4678b8 FMINNM	V16.2D, V16.2D, V18.2D

      (2135) 0x4678bc FADD	V5.2D, V18.2D, V5.2D

      (2135) 0x4678c0 FMINNM	V7.2D, V7.2D, V17.2D

      (2135) 0x4678c4 FADD	V6.2D, V17.2D, V6.2D

      (2135) 0x4678c8 B.NE	4678ac

    (2131) 0x4678cc FADD	V5.2D, V5.2D, V6.2D

    (2131) 0x4678d0 CMP	X14, X5

    (2131) 0x4678d4 FADDP	D6, V5.2D

    (2131) 0x4678d8 FMINNM	V5.2D, V7.2D, V16.2D

    (2131) 0x4678dc FMINNMP	D5, V5.2D

    (2131) 0x4678e0 B.EQ	467900

    (2131) 0x4678e4 SUB	X11, X28, X20

    (2131) 0x4678e8 ADD	X14, X0, X20,LSL #3

      (2134) 0x4678ec LDR	D7, [X14], #8

      (2134) 0x4678f0 SUBS	X11, X11, #1

      (2134) 0x4678f4 FMINNM	D5, D5, D7

      (2134) 0x4678f8 FADD	D6, D7, D6

      (2134) 0x4678fc B.NE	4678ec

    (2131) 0x467900 LDR	X21, [X2, X27,LSL #3]

    (2131) 0x467904 LDR	X20, [X2, X12,LSL #3]

    (2131) 0x467908 SUBS	X14, X20, X21

    (2131) 0x46790c B.LE	467cc0

    (2131) 0x467910 CMP	X14, #4

    (2131) 0x467914 B.CS	467a44

    (2131) 0x467918 ORR	X23, XZR, X21

    (2131) 0x46791c B	467aa4

    (2131) 0x467920 FMOV	D6, D4

    (2131) 0x467924 SUB	X11, X28, #2

    (2131) 0x467928 CMP	X11, X19

    (2131) 0x46792c B.NE	467ac0

    (2131) 0x467930 HINT	#0

    (2131) 0x467934 HINT	#0

    (2131) 0x467938 HINT	#0

    (2131) 0x46793c HINT	#0

    (2131) 0x467940 LDR	X21, [X2, X27,LSL #3]

    (2131) 0x467944 LDR	X20, [X2, X12,LSL #3]

    (2131) 0x467948 CMP	X20, X21

    (2131) 0x46794c B.LE	467cc0

    (2131) 0x467950 LDUR	X11, [X29, #464]

    (2131) 0x467954 LDR	X23, [X4, X27,LSL #3]

    (2131) 0x467958 LDR	X5, [X11]

    (2131) 0x46795c SUB	W11, W20, W21

    (2131) 0x467960 TBNZ	W11, #0, 467b4c

    (2131) 0x467964 ORR	X11, XZR, X21

    (2131) 0x467968 ADD	X14, X21, #1

    (2131) 0x46796c CMP	X20, X14

    (2131) 0x467970 B.NE	467b7c

    (2131) 0x467974 B	467cc0

    (2131) 0x467978 MOVI	V16.2D, #0

    (2131) 0x46797c DUP	V5.2D, V5.D[0]

    (2131) 0x467980 AND	X5, X14, #0x0

    (2131) 0x467984 MOVI	V7.2D, #0

    (2131) 0x467988 ADD	X11, X3, #16

    (2131) 0x46798c ADD	X23, X21, X5

    (2131) 0x467990 ADD	X7, X11, X21,LSL #3

    (2131) 0x467994 AND	X11, X14, #0x0

    (2131) 0x467998 MOV	V16.D[0], V6.D[0]

    (2131) 0x46799c ORR	V17.16B, V5.16B, V5.16B

      (2136) 0x4679a0 LDP	Q6, Q18, [X7, #2032]

      (2136) 0x4679a4 ADD	X7, X7, #32

      (2136) 0x4679a8 SUBS	X11, X11, #4

      (2136) 0x4679ac FMAXNM	V17.2D, V17.2D, V18.2D

      (2136) 0x4679b0 FADD	V7.2D, V18.2D, V7.2D

      (2136) 0x4679b4 FMAXNM	V5.2D, V5.2D, V6.2D

      (2136) 0x4679b8 FADD	V16.2D, V6.2D, V16.2D

      (2136) 0x4679bc B.NE	4679a0

    (2131) 0x4679c0 FADD	V6.2D, V7.2D, V16.2D

    (2131) 0x4679c4 FMAXNM	V5.2D, V5.2D, V17.2D

    (2131) 0x4679c8 CMP	X14, X5

    (2131) 0x4679cc FADDP	D6, V6.2D

    (2131) 0x4679d0 FMAXNMP	D5, V5.2D

    (2131) 0x4679d4 B.EQ	467cc0

    (2131) 0x4679d8 HINT	#0

    (2131) 0x4679dc HINT	#0

      (2137) 0x4679e0 LDR	D7, [X3, X23,LSL #3]

      (2137) 0x4679e4 ADD	X23, X23, #1

      (2137) 0x4679e8 CMP	X20, X23

      (2137) 0x4679ec FMAXNM	D5, D5, D7

      (2137) 0x4679f0 FADD	D6, D7, D6

      (2137) 0x4679f4 B.NE	4679e0

    (2131) 0x4679f8 B	467cc0

    (2131) 0x4679fc FMOV	D6, D4

    (2131) 0x467a00 SUB	X11, X28, #2

    (2131) 0x467a04 CMP	X11, X19

    (2131) 0x467a08 B.NE	467c0c

    (2131) 0x467a0c LDR	X21, [X2, X27,LSL #3]

    (2131) 0x467a10 LDR	X20, [X2, X12,LSL #3]

    (2131) 0x467a14 CMP	X20, X21

    (2131) 0x467a18 B.LE	467cc0

    (2131) 0x467a1c LDUR	X11, [X29, #464]

    (2131) 0x467a20 LDR	X23, [X4, X27,LSL #3]

    (2131) 0x467a24 LDR	X5, [X11]

    (2131) 0x467a28 SUB	W11, W20, W21

    (2131) 0x467a2c TBNZ	W11, #0, 467c8c

    (2131) 0x467a30 ORR	X11, XZR, X21

    (2131) 0x467a34 ADD	X14, X21, #1

    (2131) 0x467a38 CMP	X20, X14

    (2131) 0x467a3c B.EQ	467cc0

  (2141) 0x467a40 B	4680e8

    (2131) 0x467a44 MOVI	V16.2D, #0

    (2131) 0x467a48 DUP	V5.2D, V5.D[0]

    (2131) 0x467a4c AND	X5, X14, #0x0

    (2131) 0x467a50 MOVI	V7.2D, #0

    (2131) 0x467a54 ADD	X11, X3, #16

    (2131) 0x467a58 ADD	X23, X21, X5

    (2131) 0x467a5c ADD	X7, X11, X21,LSL #3

    (2131) 0x467a60 AND	X11, X14, #0x0

    (2131) 0x467a64 MOV	V16.D[0], V6.D[0]

    (2131) 0x467a68 ORR	V17.16B, V5.16B, V5.16B

      (2132) 0x467a6c LDP	Q6, Q18, [X7, #2032]

      (2132) 0x467a70 ADD	X7, X7, #32

      (2132) 0x467a74 SUBS	X11, X11, #4

      (2132) 0x467a78 FMINNM	V17.2D, V17.2D, V18.2D

      (2132) 0x467a7c FADD	V7.2D, V18.2D, V7.2D

      (2132) 0x467a80 FMINNM	V5.2D, V5.2D, V6.2D

      (2132) 0x467a84 FADD	V16.2D, V6.2D, V16.2D

      (2132) 0x467a88 B.NE	467a6c

    (2131) 0x467a8c FADD	V6.2D, V7.2D, V16.2D

    (2131) 0x467a90 FMINNM	V5.2D, V5.2D, V17.2D

    (2131) 0x467a94 CMP	X14, X5

    (2131) 0x467a98 FADDP	D6, V6.2D

    (2131) 0x467a9c FMINNMP	D5, V5.2D

    (2131) 0x467aa0 B.EQ	467cc0

      (2133) 0x467aa4 LDR	D7, [X3, X23,LSL #3]

      (2133) 0x467aa8 ADD	X23, X23, #1

      (2133) 0x467aac CMP	X20, X23

      (2133) 0x467ab0 FMINNM	D5, D5, D7

      (2133) 0x467ab4 FADD	D6, D7, D6

      (2133) 0x467ab8 B.NE	467aa4

    (2131) 0x467abc B	467cc0

    (2131) 0x467ac0 ADD	X11, X0, #8

    (2131) 0x467ac4 SUB	X23, X28, X20

    (2131) 0x467ac8 ADD	X14, X11, X20,LSL #3

    (2131) 0x467acc LDR	X11, [SP, #56]

    (2131) 0x467ad0 ADD	X20, X11, X20,LSL #3

    (2131) 0x467ad4 B	467af0

0x467ad8 HINT	#0

0x467adc HINT	#0

      (2144) 0x467ae0 ADD	X20, X20, #16

      (2144) 0x467ae4 SUBS	X23, X23, #2

      (2144) 0x467ae8 ADD	X14, X14, #16

      (2144) 0x467aec B.EQ	467940

      (2144) 0x467af0 LDUR	X11, [X20, #504]

      (2144) 0x467af4 LDR	X11, [X4, X11,LSL #3]

      (2144) 0x467af8 CMP	X21, X11

      (2144) 0x467afc B.EQ	467b20

      (2144) 0x467b00 LDR	X11, [X20]

      (2144) 0x467b04 LDR	X11, [X4, X11,LSL #3]

      (2144) 0x467b08 CMP	X21, X11

      (2144) 0x467b0c B.NE	467ae0

      (2144) 0x467b10 B	467b3c

0x467b14 HINT	#0

0x467b18 HINT	#0

0x467b1c HINT	#0

      (2144) 0x467b20 LDUR	D7, [X14, #504]

      (2144) 0x467b24 FMAXNM	D5, D5, D7

      (2144) 0x467b28 FADD	D6, D7, D6

      (2144) 0x467b2c LDR	X11, [X20]

      (2144) 0x467b30 LDR	X11, [X4, X11,LSL #3]

      (2144) 0x467b34 CMP	X21, X11

      (2144) 0x467b38 B.NE	467ae0

      (2144) 0x467b3c LDR	D7, [X14]

      (2144) 0x467b40 FMAXNM	D5, D5, D7

      (2144) 0x467b44 FADD	D6, D7, D6

      (2144) 0x467b48 B	467ae0

    (2131) 0x467b4c LDR	X11, [SP, #64]

    (2131) 0x467b50 LDR	X11, [X11, X21,LSL #3]

    (2131) 0x467b54 LDR	X11, [X6, X11,LSL #3]

    (2131) 0x467b58 CMP	X23, X11

    (2131) 0x467b5c B.NE	467b6c

    (2131) 0x467b60 LDR	D7, [X5, X21,LSL #3]

    (2131) 0x467b64 FMAXNM	D5, D5, D7

    (2131) 0x467b68 FADD	D6, D7, D6

    (2131) 0x467b6c ADD	X11, X21, #1

    (2131) 0x467b70 ADD	X14, X21, #1

    (2131) 0x467b74 CMP	X20, X14

    (2131) 0x467b78 B.EQ	467cc0

    (2131) 0x467b7c LDR	X7, [SP, #48]

    (2131) 0x467b80 ADD	X5, X5, X11,LSL #3

    (2131) 0x467b84 SUB	X14, X20, X11

    (2131) 0x467b88 ADD	X5, X5, #8

    (2131) 0x467b8c ADD	X7, X7, X11,LSL #3

    (2131) 0x467b90 B	467bac

0x467b94 HINT	#0

0x467b98 HINT	#0

0x467b9c HINT	#0

      (2143) 0x467ba0 SUBS	X14, X14, #2

      (2143) 0x467ba4 ADD	X5, X5, #16

      (2143) 0x467ba8 B.EQ	467cc0

      (2143) 0x467bac LDUR	X11, [X7, #504]

      (2143) 0x467bb0 LDR	X11, [X6, X11,LSL #3]

      (2143) 0x467bb4 CMP	X23, X11

      (2143) 0x467bb8 B.EQ	467be0

      (2143) 0x467bbc LDR	X11, [X7], #16

      (2143) 0x467bc0 LDR	X11, [X6, X11,LSL #3]

      (2143) 0x467bc4 CMP	X23, X11

      (2143) 0x467bc8 B.NE	467ba0

      (2143) 0x467bcc B	467bfc

0x467bd0 HINT	#0

0x467bd4 HINT	#0

0x467bd8 HINT	#0

0x467bdc HINT	#0

      (2143) 0x467be0 LDUR	D7, [X5, #504]

      (2143) 0x467be4 FMAXNM	D5, D5, D7

      (2143) 0x467be8 FADD	D6, D7, D6

      (2143) 0x467bec LDR	X11, [X7], #16

      (2143) 0x467bf0 LDR	X11, [X6, X11,LSL #3]

      (2143) 0x467bf4 CMP	X23, X11

      (2143) 0x467bf8 B.NE	467ba0

      (2143) 0x467bfc LDR	D7, [X5]

      (2143) 0x467c00 FMAXNM	D5, D5, D7

      (2143) 0x467c04 FADD	D6, D7, D6

      (2143) 0x467c08 B	467ba0

    (2131) 0x467c0c ADD	X11, X0, #8

    (2131) 0x467c10 SUB	X23, X28, X20

    (2131) 0x467c14 ADD	X14, X11, X20,LSL #3

    (2131) 0x467c18 LDR	X11, [SP, #56]

    (2131) 0x467c1c ADD	X20, X11, X20,LSL #3

    (2131) 0x467c20 B	467c34

      (2142) 0x467c24 ADD	X20, X20, #16

      (2142) 0x467c28 SUBS	X23, X23, #2

      (2142) 0x467c2c ADD	X14, X14, #16

      (2142) 0x467c30 B.EQ	467a0c

      (2142) 0x467c34 LDUR	X11, [X20, #504]

      (2142) 0x467c38 LDR	X11, [X4, X11,LSL #3]

      (2142) 0x467c3c CMP	X21, X11

      (2142) 0x467c40 B.EQ	467c60

      (2142) 0x467c44 LDR	X11, [X20]

      (2142) 0x467c48 LDR	X11, [X4, X11,LSL #3]

      (2142) 0x467c4c CMP	X21, X11

      (2142) 0x467c50 B.NE	467c24

      (2142) 0x467c54 B	467c7c

0x467c58 HINT	#0

0x467c5c HINT	#0

      (2142) 0x467c60 LDUR	D7, [X14, #504]

      (2142) 0x467c64 FMINNM	D5, D5, D7

      (2142) 0x467c68 FADD	D6, D7, D6

      (2142) 0x467c6c LDR	X11, [X20]

      (2142) 0x467c70 LDR	X11, [X4, X11,LSL #3]

      (2142) 0x467c74 CMP	X21, X11

      (2142) 0x467c78 B.NE	467c24

      (2142) 0x467c7c LDR	D7, [X14]

      (2142) 0x467c80 FMINNM	D5, D5, D7

      (2142) 0x467c84 FADD	D6, D7, D6

      (2142) 0x467c88 B	467c24

    (2131) 0x467c8c LDR	X11, [SP, #64]

    (2131) 0x467c90 LDR	X11, [X11, X21,LSL #3]

    (2131) 0x467c94 LDR	X11, [X6, X11,LSL #3]

    (2131) 0x467c98 CMP	X23, X11

    (2131) 0x467c9c B.NE	467cac

    (2131) 0x467ca0 LDR	D7, [X5, X21,LSL #3]

    (2131) 0x467ca4 FMINNM	D5, D5, D7

    (2131) 0x467ca8 FADD	D6, D7, D6

    (2131) 0x467cac ADD	X11, X21, #1

    (2131) 0x467cb0 ADD	X14, X21, #1

    (2131) 0x467cb4 CMP	X20, X14

    (2131) 0x467cb8 B.NE	4680e8

    (2131) 0x467cbc HINT	#0

    (2131) 0x467cc0 FABS	D7, D4

    (2131) 0x467cc4 FABS	D6, D6

    (2131) 0x467cc8 ORN	X11, XZR, X19

    (2131) 0x467ccc ADD	X10, X28, X10

    (2131) 0x467cd0 ADD	X10, X10, X11

    (2131) 0x467cd4 SUB	X11, X20, X21

    (2131) 0x467cd8 FMUL	D7, D0, D7

    (2131) 0x467cdc ADD	X9, X11, X9

    (2131) 0x467ce0 STP	X9, X10, [X29, #984]

    (2131) 0x467ce4 STR	X26, [X24, X19,LSL #3]

    (2131) 0x467ce8 FCMP	D6, D7

    (2131) 0x467cec FCCMP	D0, D3, #0, #12

    (2131) 0x467cf0 B.LT	467e00

    (2131) 0x467cf4 LDR	X11, [X1, X27,LSL #3]

    (2131) 0x467cf8 LDR	X14, [X17]

    (2131) 0x467cfc ADD	X19, X11, #1

    (2131) 0x467d00 LDR	X11, [X1, X12,LSL #3]

    (2131) 0x467d04 CMP	X14, #2

    (2131) 0x467d08 B.LT	467e80

    (2131) 0x467d0c FCMP	D4, #0

    (2131) 0x467d10 B.GE	467f44

    (2131) 0x467d14 CMP	X19, X11

    (2131) 0x467d18 B.GE	467d7c

    (2131) 0x467d1c LDR	X14, [X16]

    (2131) 0x467d20 LDR	X5, [X15]

    (2131) 0x467d24 FMUL	D4, D1, D5

    (2131) 0x467d28 B	467d48

      (2154) 0x467d2c SUB	X10, X10, #1

      (2154) 0x467d30 STR	X26, [X24, X19,LSL #3]

      (2154) 0x467d34 STUR	X10, [X29, #480]

      (2154) 0x467d38 LDR	X11, [X1, X12,LSL #3]

      (2154) 0x467d3c ADD	X19, X19, #1

      (2154) 0x467d40 CMP	X19, X11

      (2154) 0x467d44 B.GE	467d7c

      (2154) 0x467d48 LDR	D6, [X0, X19,LSL #3]

      (2154) 0x467d4c FCMP	D6, D4

      (2154) 0x467d50 B.LE	467d2c

      (2154) 0x467d54 LDR	X11, [X5, X19,LSL #3]

      (2154) 0x467d58 LDR	X7, [X14, X27,LSL #3]

      (2154) 0x467d5c LDR	X20, [X14, X11,LSL #3]

      (2154) 0x467d60 CMP	X7, X20

      (2154) 0x467d64 B.NE	467d2c

      (2154) 0x467d68 STR	X11, [X24, X19,LSL #3]

      (2154) 0x467d6c LDR	X11, [X1, X12,LSL #3]

      (2154) 0x467d70 ADD	X19, X19, #1

      (2154) 0x467d74 CMP	X19, X11

      (2154) 0x467d78 B.LT	467d48

    (2131) 0x467d7c LDR	X14, [X2, X27,LSL #3]

    (2131) 0x467d80 LDR	X11, [X2, X12,LSL #3]

    (2131) 0x467d84 CMP	X14, X11

    (2131) 0x467d88 B.GE	467674

    (2131) 0x467d8c LDUR	X11, [X29, #448]

    (2131) 0x467d90 LDR	X5, [X16]

    (2131) 0x467d94 LDR	X19, [X13]

    (2131) 0x467d98 FMUL	D4, D1, D5

    (2131) 0x467d9c LDR	X20, [X25]

    (2131) 0x467da0 LDR	X7, [X11]

    (2131) 0x467da4 B	467dc4

      (2153) 0x467da8 SUB	X9, X9, #1

      (2153) 0x467dac STR	X26, [X20, X14,LSL #3]

      (2153) 0x467db0 STUR	X9, [X29, #472]

      (2153) 0x467db4 LDR	X11, [X2, X12,LSL #3]

      (2153) 0x467db8 ADD	X14, X14, #1

      (2153) 0x467dbc CMP	X14, X11

      (2153) 0x467dc0 B.GE	467674

      (2153) 0x467dc4 LDR	D5, [X3, X14,LSL #3]

      (2153) 0x467dc8 FCMP	D5, D4

      (2153) 0x467dcc B.LE	467da8

      (2153) 0x467dd0 LDR	X11, [X19, X14,LSL #3]

      (2153) 0x467dd4 LDR	X21, [X5, X27,LSL #3]

      (2153) 0x467dd8 LDR	X23, [X7, X11,LSL #3]

      (2153) 0x467ddc CMP	X21, X23

      (2153) 0x467de0 B.NE	467da8

      (2153) 0x467de4 STR	X11, [X20, X14,LSL #3]

      (2153) 0x467de8 LDR	X11, [X2, X12,LSL #3]

      (2153) 0x467dec ADD	X14, X14, #1

      (2153) 0x467df0 CMP	X14, X11

      (2153) 0x467df4 B.LT	467dc4

    (2131) 0x467df8 B	467674

0x467dfc HINT	#0

    (2131) 0x467e00 LDR	X11, [X1, X27,LSL #3]

    (2131) 0x467e04 LDR	X14, [X1, X12,LSL #3]

    (2131) 0x467e08 ADD	X11, X11, #1

    (2131) 0x467e0c CMP	X11, X14

    (2131) 0x467e10 B.GE	467e3c

    (2131) 0x467e14 HINT	#0

    (2131) 0x467e18 HINT	#0

    (2131) 0x467e1c HINT	#0

      (2146) 0x467e20 STR	X26, [X24, X11,LSL #3]

      (2146) 0x467e24 ADD	X11, X11, #1

      (2146) 0x467e28 LDR	X14, [X1, X12,LSL #3]

      (2146) 0x467e2c CMP	X11, X14

      (2146) 0x467e30 B.LT	467e20

    (2131) 0x467e34 LDR	X11, [X1, X27,LSL #3]

    (2131) 0x467e38 ADD	X11, X11, #1

    (2131) 0x467e3c SUB	X11, X11, X14

    (2131) 0x467e40 ADD	X10, X11, X10

    (2131) 0x467e44 STUR	X10, [X29, #480]

    (2131) 0x467e48 LDR	X11, [X2, X27,LSL #3]

    (2131) 0x467e4c LDR	X14, [X2, X12,LSL #3]

    (2131) 0x467e50 CMP	X11, X14

    (2131) 0x467e54 B.GE	467668

    (2131) 0x467e58 HINT	#0

    (2131) 0x467e5c HINT	#0

      (2145) 0x467e60 STR	X26, [X30, X11,LSL #3]

      (2145) 0x467e64 ADD	X11, X11, #1

      (2145) 0x467e68 LDR	X14, [X2, X12,LSL #3]

      (2145) 0x467e6c CMP	X11, X14

      (2145) 0x467e70 B.LT	467e60

    (2131) 0x467e74 LDR	X11, [X2, X27,LSL #3]

    (2131) 0x467e78 B	467668

0x467e7c HINT	#0

    (2131) 0x467e80 FCMP	D4, #0

    (2131) 0x467e84 B.GE	468034

    (2131) 0x467e88 CMP	X19, X11

    (2131) 0x467e8c B.GE	467ee0

    (2131) 0x467e90 LDR	X14, [X15]

    (2131) 0x467e94 FMUL	D4, D1, D5

    (2131) 0x467e98 B	467eb8

0x467e9c HINT	#0

      (2150) 0x467ea0 LDR	X11, [X14, X19,LSL #3]

      (2150) 0x467ea4 STR	X11, [X24, X19,LSL #3]

      (2150) 0x467ea8 LDR	X11, [X1, X12,LSL #3]

      (2150) 0x467eac ADD	X19, X19, #1

      (2150) 0x467eb0 CMP	X19, X11

      (2150) 0x467eb4 B.GE	467ee0

      (2150) 0x467eb8 LDR	D6, [X0, X19,LSL #3]

      (2150) 0x467ebc FCMP	D6, D4

      (2150) 0x467ec0 B.GT	467ea0

      (2150) 0x467ec4 SUB	X10, X10, #1

      (2150) 0x467ec8 STR	X26, [X24, X19,LSL #3]

      (2150) 0x467ecc STUR	X10, [X29, #480]

      (2150) 0x467ed0 LDR	X11, [X1, X12,LSL #3]

      (2150) 0x467ed4 ADD	X19, X19, #1

      (2150) 0x467ed8 CMP	X19, X11

      (2150) 0x467edc B.LT	467eb8

    (2131) 0x467ee0 LDR	X14, [X2, X27,LSL #3]

    (2131) 0x467ee4 LDR	X11, [X2, X12,LSL #3]

    (2131) 0x467ee8 CMP	X14, X11

    (2131) 0x467eec B.GE	467674

    (2131) 0x467ef0 LDR	X5, [X25]

    (2131) 0x467ef4 LDR	X7, [X13]

    (2131) 0x467ef8 FMUL	D4, D1, D5

    (2131) 0x467efc B	467f18

      (2149) 0x467f00 LDR	X11, [X7, X14,LSL #3]

      (2149) 0x467f04 STR	X11, [X5, X14,LSL #3]

      (2149) 0x467f08 LDR	X11, [X2, X12,LSL #3]

      (2149) 0x467f0c ADD	X14, X14, #1

      (2149) 0x467f10 CMP	X14, X11

      (2149) 0x467f14 B.GE	467674

      (2149) 0x467f18 LDR	D5, [X3, X14,LSL #3]

      (2149) 0x467f1c FCMP	D5, D4

      (2149) 0x467f20 B.GT	467f00

      (2149) 0x467f24 SUB	X9, X9, #1

      (2149) 0x467f28 STR	X26, [X5, X14,LSL #3]

      (2149) 0x467f2c STUR	X9, [X29, #472]

      (2149) 0x467f30 LDR	X11, [X2, X12,LSL #3]

      (2149) 0x467f34 ADD	X14, X14, #1

      (2149) 0x467f38 CMP	X14, X11

      (2149) 0x467f3c B.LT	467f18

    (2131) 0x467f40 B	467674

    (2131) 0x467f44 CMP	X19, X11

    (2131) 0x467f48 B.GE	467fb0

    (2131) 0x467f4c LDR	X14, [X16]

    (2131) 0x467f50 LDR	X5, [X15]

    (2131) 0x467f54 FMUL	D4, D1, D5

    (2131) 0x467f58 B	467f7c

0x467f5c HINT	#0

      (2152) 0x467f60 SUB	X10, X10, #1

      (2152) 0x467f64 STR	X26, [X24, X19,LSL #3]

      (2152) 0x467f68 STUR	X10, [X29, #480]

      (2152) 0x467f6c LDR	X11, [X1, X12,LSL #3]

      (2152) 0x467f70 ADD	X19, X19, #1

      (2152) 0x467f74 CMP	X19, X11

      (2152) 0x467f78 B.GE	467fb0

      (2152) 0x467f7c LDR	D6, [X0, X19,LSL #3]

      (2152) 0x467f80 FCMP	D6, D4

      (2152) 0x467f84 B.GE	467f60

      (2152) 0x467f88 LDR	X11, [X5, X19,LSL #3]

      (2152) 0x467f8c LDR	X7, [X14, X27,LSL #3]

      (2152) 0x467f90 LDR	X20, [X14, X11,LSL #3]

      (2152) 0x467f94 CMP	X7, X20

      (2152) 0x467f98 B.NE	467f60

      (2152) 0x467f9c STR	X11, [X24, X19,LSL #3]

      (2152) 0x467fa0 LDR	X11, [X1, X12,LSL #3]

      (2152) 0x467fa4 ADD	X19, X19, #1

      (2152) 0x467fa8 CMP	X19, X11

      (2152) 0x467fac B.LT	467f7c

    (2131) 0x467fb0 LDR	X14, [X2, X27,LSL #3]

    (2131) 0x467fb4 LDR	X11, [X2, X12,LSL #3]

    (2131) 0x467fb8 CMP	X14, X11

    (2131) 0x467fbc B.GE	467674

    (2131) 0x467fc0 LDUR	X11, [X29, #448]

    (2131) 0x467fc4 LDR	X5, [X16]

    (2131) 0x467fc8 LDR	X19, [X13]

    (2131) 0x467fcc FMUL	D4, D1, D5

    (2131) 0x467fd0 LDR	X20, [X25]

    (2131) 0x467fd4 LDR	X7, [X11]

    (2131) 0x467fd8 B	467ffc

0x467fdc HINT	#0

      (2151) 0x467fe0 SUB	X9, X9, #1

      (2151) 0x467fe4 STR	X26, [X20, X14,LSL #3]

      (2151) 0x467fe8 STUR	X9, [X29, #472]

      (2151) 0x467fec LDR	X11, [X2, X12,LSL #3]

      (2151) 0x467ff0 ADD	X14, X14, #1

      (2151) 0x467ff4 CMP	X14, X11

      (2151) 0x467ff8 B.GE	467674

      (2151) 0x467ffc LDR	D5, [X3, X14,LSL #3]

      (2151) 0x468000 FCMP	D5, D4

      (2151) 0x468004 B.GE	467fe0

      (2151) 0x468008 LDR	X11, [X19, X14,LSL #3]

      (2151) 0x46800c LDR	X21, [X5, X27,LSL #3]

      (2151) 0x468010 LDR	X23, [X7, X11,LSL #3]

      (2151) 0x468014 CMP	X21, X23

      (2151) 0x468018 B.NE	467fe0

      (2151) 0x46801c STR	X11, [X20, X14,LSL #3]

      (2151) 0x468020 LDR	X11, [X2, X12,LSL #3]

      (2151) 0x468024 ADD	X14, X14, #1

      (2151) 0x468028 CMP	X14, X11

      (2151) 0x46802c B.LT	467ffc

    (2131) 0x468030 B	467674

    (2131) 0x468034 FMUL	D4, D1, D5

    (2131) 0x468038 CMP	X19, X11

    (2131) 0x46803c B.GE	468088

    (2131) 0x468040 LDR	X14, [X15]

    (2131) 0x468044 B	468060

      (2148) 0x468048 LDR	X11, [X14, X19,LSL #3]

      (2148) 0x46804c STR	X11, [X24, X19,LSL #3]

      (2148) 0x468050 LDR	X11, [X1, X12,LSL #3]

      (2148) 0x468054 ADD	X19, X19, #1

      (2148) 0x468058 CMP	X19, X11

      (2148) 0x46805c B.GE	468088

      (2148) 0x468060 LDR	D5, [X0, X19,LSL #3]

      (2148) 0x468064 FCMP	D5, D4

      (2148) 0x468068 B.LT	468048

      (2148) 0x46806c SUB	X10, X10, #1

      (2148) 0x468070 STR	X26, [X24, X19,LSL #3]

      (2148) 0x468074 STUR	X10, [X29, #480]

      (2148) 0x468078 LDR	X11, [X1, X12,LSL #3]

      (2148) 0x46807c ADD	X19, X19, #1

      (2148) 0x468080 CMP	X19, X11

      (2148) 0x468084 B.LT	468060

    (2131) 0x468088 LDR	X14, [X2, X27,LSL #3]

    (2131) 0x46808c LDR	X11, [X2, X12,LSL #3]

    (2131) 0x468090 CMP	X14, X11

    (2131) 0x468094 B.GE	467674

    (2131) 0x468098 LDR	X5, [X25]

    (2131) 0x46809c LDR	X7, [X13]

    (2131) 0x4680a0 B	4680bc

      (2147) 0x4680a4 LDR	X11, [X7, X14,LSL #3]

      (2147) 0x4680a8 STR	X11, [X5, X14,LSL #3]

      (2147) 0x4680ac LDR	X11, [X2, X12,LSL #3]

      (2147) 0x4680b0 ADD	X14, X14, #1

      (2147) 0x4680b4 CMP	X14, X11

      (2147) 0x4680b8 B.GE	467674

      (2147) 0x4680bc LDR	D5, [X3, X14,LSL #3]

      (2147) 0x4680c0 FCMP	D5, D4

      (2147) 0x4680c4 B.LT	4680a4

      (2147) 0x4680c8 SUB	X9, X9, #1

      (2147) 0x4680cc STR	X26, [X5, X14,LSL #3]

      (2147) 0x4680d0 STUR	X9, [X29, #472]

      (2147) 0x4680d4 LDR	X11, [X2, X12,LSL #3]

      (2147) 0x4680d8 ADD	X14, X14, #1

      (2147) 0x4680dc CMP	X14, X11

      (2147) 0x4680e0 B.LT	4680bc

    (2131) 0x4680e4 B	467674

  (2141) 0x4680e8 LDR	X7, [SP, #48]

  (2141) 0x4680ec ADD	X5, X5, X11,LSL #3

  (2141) 0x4680f0 SUB	X14, X20, X11

  (2141) 0x4680f4 ADD	X5, X5, #8

  (2141) 0x4680f8 ADD	X7, X7, X11,LSL #3

  (2141) 0x4680fc B	46810c

  (2141) 0x468100 SUBS	X14, X14, #2

  (2141) 0x468104 ADD	X5, X5, #16

  (2141) 0x468108 B.EQ	467cc0

  (2141) 0x46810c LDUR	X11, [X7, #504]

  (2141) 0x468110 LDR	X11, [X6, X11,LSL #3]

  (2141) 0x468114 CMP	X23, X11

  (2141) 0x468118 B.EQ	468140

  (2141) 0x46811c LDR	X11, [X7], #16

  (2141) 0x468120 LDR	X11, [X6, X11,LSL #3]

  (2141) 0x468124 CMP	X23, X11

  (2141) 0x468128 B.NE	468100

  (2141) 0x46812c B	46815c

0x468130 HINT	#0

0x468134 HINT	#0

0x468138 HINT	#0

0x46813c HINT	#0

(2140) 0x468140 LDUR	D7, [X5, #504]

(2140) 0x468144 FMINNM	D5, D5, D7

(2140) 0x468148 FADD	D6, D7, D6

(2140) 0x46814c LDR	X11, [X7], #16

(2140) 0x468150 LDR	X11, [X6, X11,LSL #3]

(2140) 0x468154 CMP	X23, X11

(2140) 0x468158 B.NE	468100

  (2141) 0x46815c LDR	D7, [X5]

  (2141) 0x468160 FMINNM	D5, D5, D7

  (2141) 0x468164 FADD	D6, D7, D6

  (2141) 0x468168 B	468100

0x46816c LDP	X9, X11, [SP, #8]

0x468170 LDUR	X19, [X29, #456]

0x468174 SUB	X0, X29, #32

0x468178 SUB	X2, X29, #40

0x46817c LDR	X9, [X9]

0x468180 LDR	X10, [X19]

0x468184 LDR	X4, [X11]

0x468188 ADD	X1, X8, X9,LSL #3

0x46818c ADD	X3, X10, X9,LSL #3

0x468190 BL	4aedd0

0x468194 LDP	X8, X10, [X29, #1000]

0x468198 CMP	X10, X8

0x46819c B.GE	468284

0x4681a0 LDR	X11, [SP]

0x4681a4 LDP	X15, X13, [SP, #32]

0x4681a8 LDR	X14, [SP, #24]

0x4681ac LDR	X12, [X19]

0x4681b0 LDR	X16, [X25]

0x4681b4 LDR	X11, [X11]

0x4681b8 LDR	X13, [X13]

0x4681bc LDP	X9, X8, [X29, #192]

0x4681c0 LDR	X14, [X14]

0x4681c4 LDR	X15, [X15]

0x4681c8 B	4681d8

  (2128) 0x4681cc LDUR	X17, [X29, #488]

  (2128) 0x4681d0 CMP	X10, X17

  (2128) 0x4681d4 B.GE	468284

  (2128) 0x4681d8 ORR	X17, XZR, X10

  (2128) 0x4681dc LDUR	X10, [X29, #480]

  (2128) 0x4681e0 LDR	X18, [X11, X17,LSL #3]

  (2128) 0x4681e4 ADD	X10, X18, X10

  (2128) 0x4681e8 STR	X10, [X11, X17,LSL #3]

  (2128) 0x4681ec LDUR	X10, [X29, #472]

  (2128) 0x4681f0 LDR	X18, [X12, X17,LSL #3]

  (2128) 0x4681f4 ADD	X10, X18, X10

  (2128) 0x4681f8 STR	X10, [X12, X17,LSL #3]

  (2128) 0x4681fc ADD	X10, X17, #1

  (2128) 0x468200 LDR	X18, [X13, X17,LSL #3]

  (2128) 0x468204 LDR	X0, [X13, X10,LSL #3]

  (2128) 0x468208 CMP	X18, X0

  (2128) 0x46820c B.GE	468244

(2129) 0x468210 LDR	X1, [X11, X17,LSL #3]

(2129) 0x468214 LDR	X2, [X9]

(2129) 0x468218 B	46822c

0x46821c HINT	#0

(2129) 0x468220 ADD	X18, X18, #1

(2129) 0x468224 CMP	X18, X0

(2129) 0x468228 B.GE	468244

(2129) 0x46822c LDR	X3, [X14, X18,LSL #3]

(2129) 0x468230 TBNZ	X3, #63, 468220

(2129) 0x468234 STR	X3, [X2, X1,LSL #3]

(2129) 0x468238 ADD	X1, X1, #1

(2129) 0x46823c LDR	X0, [X13, X10,LSL #3]

(2129) 0x468240 B	468220

  (2128) 0x468244 LDR	X18, [X15, X17,LSL #3]

  (2128) 0x468248 LDR	X0, [X15, X10,LSL #3]

  (2128) 0x46824c CMP	X18, X0

  (2128) 0x468250 B.GE	4681cc

  (2128) 0x468254 LDR	X17, [X12, X17,LSL #3]

  (2128) 0x468258 LDR	X1, [X8]

  (2128) 0x46825c B	46826c

    (2130) 0x468260 ADD	X18, X18, #1

    (2130) 0x468264 CMP	X18, X0

    (2130) 0x468268 B.GE	4681cc

    (2130) 0x46826c LDR	X2, [X16, X18,LSL #3]

    (2130) 0x468270 TBNZ	X2, #63, 468260

    (2130) 0x468274 STR	X2, [X1, X17,LSL #3]

    (2130) 0x468278 ADD	X17, X17, #1

    (2130) 0x46827c LDR	X0, [X15, X10,LSL #3]

    (2130) 0x468280 B	468260

0x468284 LDP	X20, X19, [SP, #224]

0x468288 LDP	X22, X21, [SP, #208]

0x46828c LDP	X24, X23, [SP, #192]

0x468290 LDP	X26, X25, [SP, #176]

0x468294 LDP	X28, X27, [SP, #160]

0x468298 LDP	X29, X30, [SP, #144]

0x46829c ADD	SP, SP, #240

0x4682a0 RET

0x4682a4 HINT	#0

0x4682a8 HINT	#0

0x4682ac HINT	#0

Coverage (%)	Name	Source Location	Module
►98.75+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.25+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGCreateS	par_strength.c:520	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:581	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	par_strength.c:246-513
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:246-283,289-302,309-386,392-415,422-445,451-472,480,492-513.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.50 to 0.67 cycles (35.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 30% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 23.50 to 6.79 cycles (3.46x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:250
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:480

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	132
nb uops	98
loop length	528
used w registers	0
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	4
used q registers	0
used v registers	0
used z registers	0
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.25 cycles
front end	12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	5.25	5.25	5.25	5.25	0.50	0.50	0.50	0.50	23.50	23.17	23.33	9.50	9.50
cycles	3.50	3.50	5.25	5.25	5.25	5.25	0.50	0.50	0.50	0.50	23.50	23.17	23.33	9.50	9.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Dispatch	23.50
Overall L1	23.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	31%
load	29%
store	35%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	30%
load	29%
store	35%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 467560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X1, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X25, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X5, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4ae1d0 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X12, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X19, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GE 46816c <hypre_BoomerAMGCreateS.omp_outlined.1+0xc0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D3, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVN X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X16, X15, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X13, X3, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X18, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X30, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X5, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X2, X1, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X5, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D0, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X11, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X19, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X3, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X24, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X19, X7, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X11, X19, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 467680 <hypre_BoomerAMGCreateS.omp_outlined.1+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X9, X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X19, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X2, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X1, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4aedd0 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 468284 <hypre_BoomerAMGCreateS.omp_outlined.1+0xd24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4681d8 <hypre_BoomerAMGCreateS.omp_outlined.1+0xc78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
LDP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	par_strength.c:246-513
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:250
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:480

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	132
nb uops	98
loop length	528
used w registers	0
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	4
used q registers	0
used v registers	0
used z registers	0
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.25 cycles
front end	12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	5.25	5.25	5.25	5.25	0.50	0.50	0.50	0.50	23.50	23.17	23.33	9.50	9.50
cycles	3.50	3.50	5.25	5.25	5.25	5.25	0.50	0.50	0.50	0.50	23.50	23.17	23.33	9.50	9.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Dispatch	23.50
Overall L1	23.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	31%
load	29%
store	35%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	30%
load	29%
store	35%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 467560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X1, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X25, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X5, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4ae1d0 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X12, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X19, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GE 46816c <hypre_BoomerAMGCreateS.omp_outlined.1+0xc0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D3, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVN X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X16, X15, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X13, X3, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X18, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X30, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X5, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X2, X1, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X5, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D0, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X11, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X19, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X3, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X24, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X19, X7, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X11, X19, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 467680 <hypre_BoomerAMGCreateS.omp_outlined.1+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X9, X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X19, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X2, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X1, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4aedd0 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 468284 <hypre_BoomerAMGCreateS.omp_outlined.1+0xd24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4681d8 <hypre_BoomerAMGCreateS.omp_outlined.1+0xc78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
LDP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreateS.omp_outlined.1–	0.20	0.10
▼Loop 2129 - par_strength.c:492-513 - exec–	0.07	0.03
▼Loop 2128 - par_strength.c:492-513 - exec–	0.00	0.01
○Loop 2130 - par_strength.c:508-513 - exec	0.00	0.00
▼Loop 2140 - par_strength.c:253-472 - exec–	0.00	0.00
▼Loop 2141 - par_strength.c:253-472 - exec–	0.00	0.00
▼Loop 2131 - par_strength.c:253-472 - exec–	0.04	0.01
○Loop 2148 - par_strength.c:451-460 - exec	0.06	0.02
○Loop 2135 - par_strength.c:324-327 - exec	0.02	0.01
○Loop 2134 - par_strength.c:324-327 - exec	0.00	0.00
○Loop 2153 - par_strength.c:376-386 - exec	0.00	0.00
○Loop 2151 - par_strength.c:405-415 - exec	0.00	0.00
○Loop 2144 - par_strength.c:270-275 - exec	0.00	0.00
○Loop 2133 - par_strength.c:329-332 - exec	0.00	0.00
○Loop 2138 - par_strength.c:311-314 - exec	0.00	0.00
○Loop 2152 - par_strength.c:392-402 - exec	0.00	0.00
○Loop 2147 - par_strength.c:463-472 - exec	0.00	0.00
○Loop 2146 - par_strength.c:345-347 - exec	0.00	0.00
○Loop 2142 - par_strength.c:289-294 - exec	0.00	0.00
○Loop 2143 - par_strength.c:278-283 - exec	0.00	0.00
○Loop 2137 - par_strength.c:316-319 - exec	0.00	0.00
○Loop 2132 - par_strength.c:329-332 - exec	0.00	0.00
○Loop 2154 - par_strength.c:363-373 - exec	0.00	0.00
○Loop 2150 - par_strength.c:424-433 - exec	0.00	0.00
○Loop 2139 - par_strength.c:311-314 - exec	0.00	0.00
○Loop 2149 - par_strength.c:436-445 - exec	0.00	0.00
○Loop 2136 - par_strength.c:316-319 - exec	0.00	0.00
○Loop 2145 - par_strength.c:351-353 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code