OV - exec - Function hypre_BoomerAMGCreate2ndS.omp

	Function: hypre_BoomerAMGCreate2ndS.omp_outlined.15	Module: exec	Source: par_strength.c:1668-2230 [...]	Coverage (incl. loops): 1.38% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1668 - 2230

--------------------------------------------------------------------------------

1668: #pragma omp parallel private(i1,i2,i3,jj1,jj2,index)

1669: #endif

1670:    {

1671:       HYPRE_Int my_thread_num = hypre_GetThreadNum();

1672:

1673:       HYPRE_Int i1_begin, i1_end;

1674:       hypre_GetSimpleThreadPartition(&i1_begin, &i1_end, num_cols_diag_S);

1675:

1676:       HYPRE_Int *C_temp_diag_j = NULL, *C_temp_offd_j = NULL;

1677:       HYPRE_Int *C_temp_diag_data = NULL, *C_temp_offd_data = NULL;

1678:

1679:       if (num_paths > 1)

1680:       {

1681:          C_temp_diag_j = C_temp_diag_j_array + num_coarse*my_thread_num;

1682:          C_temp_offd_j = C_temp_offd_j_array + num_cols_offd_C*my_thread_num;

1683:

1684:          C_temp_diag_data = C_temp_diag_data_array + num_coarse*my_thread_num;

1685:          C_temp_offd_data = C_temp_offd_data_array + num_cols_offd_C*my_thread_num;

1686:       }

1687:

1688:       HYPRE_Int *S_marker = NULL, *S_marker_offd = NULL;

1689:       if (num_coarse) S_marker = S_marker_array + num_coarse*my_thread_num;

1690:       if (num_cols_offd_C) S_marker_offd = S_marker_offd_array + num_cols_offd_C*my_thread_num;

1691:       for (i1 = 0; i1 < num_coarse; i1++)

1692:       {

1693:          S_marker[i1] = -1;

1694:       }

1695:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1696:       {

1697:          S_marker_offd[i1] = -1;

[...]

1705:       HYPRE_Int num_nonzeros_diag = 0;

1706:       HYPRE_Int num_nonzeros_offd = 0;

1707:

1708:       HYPRE_Int ic_begin = num_coarse_prefix_sum[my_thread_num];

1709:       HYPRE_Int ic_end = num_coarse_prefix_sum[my_thread_num + 1];

1710:       HYPRE_Int ic;

1711:

1712:       if (num_paths == 1)

1713:       {

1714:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1720:              HYPRE_Int i1 = coarse_to_fine[ic];

1721:

1722:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

1723:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

1724:

1725:              C_diag_i[ic] = num_nonzeros_diag;

1726:              if (num_cols_offd_C)

1727:              {

1728:                 C_offd_i[ic] = num_nonzeros_offd;

1729:              }

1730:

1731:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1732:              {

1733:                  i2 = S_diag_j[jj1];

1734:                  if (CF_marker[i2] > 0)

1735:                  {

1736:                     index = fine_to_coarse[i2];

1737:                     if (S_marker[index] < jj_row_begin_diag)

1738:                     {

1739:                        S_marker[index] = num_nonzeros_diag;

1740:                        num_nonzeros_diag++;

1741:                     }

1742:                  }

1743:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1744:                  {

1745:                     i3 = S_diag_j[jj2];

1746:                     if (CF_marker[i3] > 0)

1747:                     {

1748:                        index = fine_to_coarse[i3];

1749:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

1750:                        {

1751:                           S_marker[index] = num_nonzeros_diag;

1752:                           num_nonzeros_diag++;

1753:                        }

1754:                     }

1755:                  }

1756:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1757:                  {

1758:                     i3 = S_offd_j[jj2];

1759:                     if (CF_marker_offd[i3] > 0)

1760:                     {

1761:                        index = map_S_to_C[i3];

1762:                        if (S_marker_offd[index] < jj_row_begin_offd)

1763:                        {

1764:                           S_marker_offd[index] = num_nonzeros_offd;

1765:                           num_nonzeros_offd++;

1766:                        }

1767:                     }

1768:                  }

1769:              }

1770:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1771:              {

1772:                  i2 = S_offd_j[jj1];

1773:                  if (CF_marker_offd[i2] > 0)

1774:                  {

1775:                     index = map_S_to_C[i2];

1776:                     if (S_marker_offd[index] < jj_row_begin_offd)

1777:                     {

1778:                        S_marker_offd[index] = num_nonzeros_offd;

1779:                        num_nonzeros_offd++;

1780:                     }

1781:                  }

1782:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1783:                  {

1784:                     i3 = S_ext_diag_j[jj2];

1785:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

1786:                     {

1787:                        S_marker[i3] = num_nonzeros_diag;

1788:                        num_nonzeros_diag++;

1789:                     }

1790:                  }

1791:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1792:                  {

1793:                     i3 = S_ext_offd_j[jj2];

1794:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1795:                     {

1796:                        S_marker_offd[i3] = num_nonzeros_offd;

1797:                        num_nonzeros_offd++;

[...]

1806:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1812:              HYPRE_Int i1 = coarse_to_fine[ic];

1813:

1814:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

1815:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

1816:

1817:              C_diag_i[ic] = num_nonzeros_diag;

1818:              if (num_cols_offd_C)

1819:              {

1820:                 C_offd_i[ic] = num_nonzeros_offd;

1821:              }

1822:

1823:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1824:              {

1825:                  i2 = S_diag_j[jj1];

1826:                  if (CF_marker[i2] > 0)

1827:                  {

1828:                     index = fine_to_coarse[i2];

1829:                     if (S_marker[index] < jj_row_begin_diag)

1830:                     {

1831:                        S_marker[index] = jj_count_diag;

1832:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

1833:                        jj_count_diag++;

1834:                     }

1835:                     else

1836:                     {

1837:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

1838:                     }

1839:                  }

1840:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1841:                  {

1842:                     i3 = S_diag_j[jj2];

1843:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

1844:                     {

1845:                        index = fine_to_coarse[i3];

1846:                        if (S_marker[index] < jj_row_begin_diag)

1847:                        {

1848:                           S_marker[index] = jj_count_diag;

1849:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1850:                           jj_count_diag++;

1851:                        }

1852:                        else

1853:                        {

1854:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

1855:                        }

1856:                     }

1857:                  }

1858:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1859:                  {

1860:                     i3 = S_offd_j[jj2];

1861:                     if (CF_marker_offd[i3] > 0)

1862:                     {

1863:                        index = map_S_to_C[i3];

1864:                        if (S_marker_offd[index] < jj_row_begin_offd)

1865:                        {

1866:                           S_marker_offd[index] = jj_count_offd;

1867:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1868:                           jj_count_offd++;

1869:                        }

1870:                        else

1871:                        {

1872:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

1873:                        }

1874:                     }

1875:                  }

1876:              }

1877:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1878:              {

1879:                  i2 = S_offd_j[jj1];

1880:                  if (CF_marker_offd[i2] > 0)

1881:                  {

1882:                     index = map_S_to_C[i2];

1883:                     if (S_marker_offd[index] < jj_row_begin_offd)

1884:                     {

1885:                        S_marker_offd[index] = jj_count_offd;

1886:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

1887:                        jj_count_offd++;

1888:                     }

1889:                     else

1890:                     {

1891:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

1892:                     }

1893:                  }

1894:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1895:                  {

1896:                     i3 = S_ext_diag_j[jj2];

1897:                     if (i3 != ic)

1898:                     {

1899:                        if (S_marker[i3] < jj_row_begin_diag)

1900:                        {

1901:                           S_marker[i3] = jj_count_diag;

1902:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1903:                           jj_count_diag++;

1904:                        }

1905:                        else

1906:                        {

1907:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

1908:                        }

1909:                     }

1910:                  }

1911:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1912:                  {

1913:                     i3 = S_ext_offd_j[jj2];

1914:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1915:                     {

1916:                        S_marker_offd[i3] = jj_count_offd;

1917:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1918:                        jj_count_offd++;

1919:                     }

1920:                     else

1921:                     {

1922:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

1923:                     }

1924:                  }

1925:              }

1926:

1927:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

1928:              {

1929:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

1930:                  {

1931:                     ++num_nonzeros_diag;

1932:                  }

1933:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

1934:              }

1935:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

1936:              {

1937:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

1938:                  {

1939:                     ++num_nonzeros_offd;

1940:                  }

1941:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

1942:              }

1943:          } /* for each row */

1944:       } /* num_paths > 1 */

1945:

1946:       hypre_prefix_sum_pair(

1947:          &num_nonzeros_diag, &C_diag_i[num_coarse],

1948:          &num_nonzeros_offd, &C_offd_i[num_coarse],

1949:          prefix_sum_workspace);

1950:

1951:       for (i1 = 0; i1 < num_coarse; i1++)

1952:       {

1953:          S_marker[i1] = -1;

1954:       }

1955:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1956:       {

1957:          S_marker_offd[i1] = -1;

1958:       }

1959:

1960: #ifdef HYPRE_USING_OPENMP

1961: #pragma omp barrier

1962: #pragma omp master

1963: #endif

1964:       {

1965:          if (C_diag_i[num_coarse])

1966:          {

1967:             C_diag_j = hypre_TAlloc(HYPRE_Int, C_diag_i[num_coarse]);

1968:          }

1969:          if (C_offd_i[num_coarse])

1970:          {

1971:             C_offd_j = hypre_TAlloc(HYPRE_Int, C_offd_i[num_coarse]);

1972:          }

1973:       }

1974: #ifdef HYPRE_USING_OPENMP

1975: #pragma omp barrier

1976: #endif

1977:

1978:       for (ic = ic_begin; ic < ic_end - 1; ic++)

1979:       {

1980:          if (C_diag_i[ic+1] == C_diag_i[ic] && C_offd_i[ic+1] == C_offd_i[ic])

1981:             CF_marker[coarse_to_fine[ic]] = 2;

1982:

1983:          C_diag_i[ic] += num_nonzeros_diag;

1984:          C_offd_i[ic] += num_nonzeros_offd;

1985:       }

1986:       if (ic_begin < ic_end)

1987:       {

1988:          C_diag_i[ic] += num_nonzeros_diag;

1989:          C_offd_i[ic] += num_nonzeros_offd;

1990:

1991:          HYPRE_Int next_C_diag_i = prefix_sum_workspace[2*(my_thread_num + 1)];

1992:          HYPRE_Int next_C_offd_i = prefix_sum_workspace[2*(my_thread_num + 1) + 1];

1993:

1994:          if (next_C_diag_i == C_diag_i[ic] && next_C_offd_i == C_offd_i[ic])

1995:             CF_marker[coarse_to_fine[ic]] = 2;

1996:       }

1997:

1998:       if (num_paths == 1)

1999:       {

2000:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2006:              HYPRE_Int i1 = coarse_to_fine[ic];

2007:

2008:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

2009:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

2010:

2011:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2012:              {

2013:                  i2 = S_diag_j[jj1];

2014:                  if (CF_marker[i2] > 0)

2015:                  {

2016:                     index = fine_to_coarse[i2];

2017:                     if (S_marker[index] < jj_row_begin_diag)

2018:                     {

2019:                        S_marker[index] = num_nonzeros_diag;

2020:                        C_diag_j[num_nonzeros_diag] = index;

2021:                        num_nonzeros_diag++;

2022:                     }

2023:                  }

2024:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2025:                  {

2026:                     i3 = S_diag_j[jj2];

2027:                     if (CF_marker[i3] > 0)

2028:                     {

2029:                        index = fine_to_coarse[i3];

2030:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

2031:                        {

2032:                           S_marker[index] = num_nonzeros_diag;

2033:                           C_diag_j[num_nonzeros_diag] = index;

2034:                           num_nonzeros_diag++;

2035:                        }

2036:                     }

2037:                  }

2038:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2039:                  {

2040:                     i3 = S_offd_j[jj2];

2041:                     if (CF_marker_offd[i3] > 0)

2042:                     {

2043:                        index = map_S_to_C[i3];

2044:                        if (S_marker_offd[index] < jj_row_begin_offd)

2045:                        {

2046:                           S_marker_offd[index] = num_nonzeros_offd;

2047:                           C_offd_j[num_nonzeros_offd] = index;

2048:                           num_nonzeros_offd++;

2049:                        }

2050:                     }

2051:                  }

2052:              }

2053:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2054:              {

2055:                  i2 = S_offd_j[jj1];

2056:                  if (CF_marker_offd[i2] > 0)

2057:                  {

2058:                     index = map_S_to_C[i2];

2059:                     if (S_marker_offd[index] < jj_row_begin_offd)

2060:                     {

2061:                        S_marker_offd[index] = num_nonzeros_offd;

2062:                        C_offd_j[num_nonzeros_offd] = index;

2063:                        num_nonzeros_offd++;

2064:                     }

2065:                  }

2066:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2067:                  {

2068:                     i3 = S_ext_diag_j[jj2];

2069:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

2070:                     {

2071:                        S_marker[i3] = num_nonzeros_diag;

2072:                        C_diag_j[num_nonzeros_diag] = i3;

2073:                        num_nonzeros_diag++;

2074:                     }

2075:                  }

2076:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2077:                  {

2078:                     i3 = S_ext_offd_j[jj2];

2079:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2080:                     {

2081:                        S_marker_offd[i3] = num_nonzeros_offd;

2082:                        C_offd_j[num_nonzeros_offd] = i3;

2083:                        num_nonzeros_offd++;

[...]

2093:          jj_count_offd = num_nonzeros_offd;

2094:

2095:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2101:              HYPRE_Int i1 = coarse_to_fine[ic];

2102:

2103:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

2104:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

2105:

2106:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2107:              {

2108:                  i2 = S_diag_j[jj1];

2109:                  if (CF_marker[i2] > 0)

2110:                  {

2111:                     index = fine_to_coarse[i2];

2112:                     if (S_marker[index] < jj_row_begin_diag)

2113:                     {

2114:                        S_marker[index] = jj_count_diag;

2115:                        C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2116:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

2117:                        jj_count_diag++;

2118:                     }

2119:                     else

2120:                     {

2121:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

2122:                     }

2123:                  }

2124:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2125:                  {

2126:                     i3 = S_diag_j[jj2];

2127:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

2128:                     {

2129:                        index = fine_to_coarse[i3];

2130:                        if (S_marker[index] < jj_row_begin_diag)

2131:                        {

2132:                           S_marker[index] = jj_count_diag;

2133:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2134:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2135:                           jj_count_diag++;

2136:                        }

2137:                        else

2138:                        {

2139:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

2140:                        }

2141:                     }

2142:                  }

2143:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2144:                  {

2145:                     i3 = S_offd_j[jj2];

2146:                     if (CF_marker_offd[i3] > 0)

2147:                     {

2148:                        index = map_S_to_C[i3];

2149:                        if (S_marker_offd[index] < jj_row_begin_offd)

2150:                        {

2151:                           S_marker_offd[index] = jj_count_offd;

2152:                           C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2153:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2154:                           jj_count_offd++;

2155:                        }

2156:                        else

2157:                        {

2158:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

2159:                        }

2160:                     }

2161:                  }

2162:              }

2163:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2164:              {

2165:                  i2 = S_offd_j[jj1];

2166:                  if (CF_marker_offd[i2] > 0)

2167:                  {

2168:                     index = map_S_to_C[i2];

2169:                     if (S_marker_offd[index] < jj_row_begin_offd)

2170:                     {

2171:                        S_marker_offd[index] = jj_count_offd;

2172:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2173:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

2174:                        jj_count_offd++;

2175:                     }

2176:                     else

2177:                     {

2178:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

2179:                     }

2180:                  }

2181:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2182:                  {

2183:                     i3 = S_ext_diag_j[jj2];

2184:                     if (i3 != ic)

2185:                     {

2186:                        if (S_marker[i3] < jj_row_begin_diag)

2187:                        {

2188:                           S_marker[i3] = jj_count_diag;

2189:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = i3;

2190:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2191:                           jj_count_diag++;

2192:                        }

2193:                        else

2194:                        {

2195:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

2196:                        }

2197:                     }

2198:                  }

2199:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2200:                  {

2201:                     i3 = S_ext_offd_j[jj2];

2202:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2203:                     {

2204:                        S_marker_offd[i3] = jj_count_offd;

2205:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = i3;

2206:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2207:                        jj_count_offd++;

2208:                     }

2209:                     else

2210:                     {

2211:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

2212:                     }

2213:                  }

2214:              }

2215:

2216:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

2217:              {

2218:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

2219:                  {

2220:                     C_diag_j[num_nonzeros_diag++] = C_temp_diag_j[jj1 - jj_row_begin_diag];

2221:                  }

2222:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

2223:              }

2224:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

2225:              {

2226:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

2227:                  {

2228:                     C_offd_j[num_nonzeros_offd++] = C_temp_offd_j[jj1 - jj_row_begin_offd];

2229:                  }

2230:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

0x46b550 SUB	SP, SP, #384

0x46b554 STP	X29, X30, [SP, #288]

0x46b558 STP	X28, X27, [SP, #304]

0x46b55c STP	X26, X25, [SP, #320]

0x46b560 STP	X24, X23, [SP, #336]

0x46b564 STP	X22, X21, [SP, #352]

0x46b568 STP	X20, X19, [SP, #368]

0x46b56c ADD	X29, SP, #288

0x46b570 LDP	X27, X22, [X29, #112]

0x46b574 ORR	X21, XZR, X7

0x46b578 ORR	X24, XZR, X6

0x46b57c ORR	X20, XZR, X5

0x46b580 ORR	X25, XZR, X4

0x46b584 ORR	X19, XZR, X3

0x46b588 ORR	X26, XZR, X2

0x46b58c STR	X0, [SP, #32]

0x46b590 BL	4ae1b0

0x46b594 LDR	X2, [X26]

0x46b598 ORR	X28, XZR, X0

0x46b59c SUB	X0, X29, #16

0x46b5a0 SUB	X1, X29, #24

0x46b5a4 BL	4ae1d0

0x46b5a8 LDR	X10, [X20]

0x46b5ac LDR	X8, [X19]

0x46b5b0 LDR	X9, [X21]

0x46b5b4 ORR	X15, XZR, X20

0x46b5b8 MUL	X11, X10, X28

0x46b5bc CMP	X8, #1

0x46b5c0 STUR	X21, [X29, #400]

0x46b5c4 B.LE	46b5f4

0x46b5c8 LDP	X13, X8, [X29, #96]

0x46b5cc LDR	X12, [X25]

0x46b5d0 ADD	X26, X12, X11,LSL #3

0x46b5d4 LDR	X14, [X24]

0x46b5d8 LDR	X13, [X13]

0x46b5dc LDR	X8, [X8]

0x46b5e0 MUL	X12, X9, X28

0x46b5e4 ADD	X23, X14, X12,LSL #3

0x46b5e8 ADD	X20, X13, X11,LSL #3

0x46b5ec ADD	X21, X8, X12,LSL #3

0x46b5f0 B	46b608

0x46b5f4 ORR	X21, XZR, XZR

0x46b5f8 ORR	X20, XZR, XZR

0x46b5fc ORR	X23, XZR, XZR

0x46b600 ORR	X26, XZR, XZR

0x46b604 MUL	X12, X9, X28

0x46b608 LDR	X13, [X27]

0x46b60c LDR	X14, [X29, #144]

0x46b610 LDR	X8, [X29, #128]

0x46b614 ADD	X13, X13, X11,LSL #3

0x46b618 LDR	X11, [X22]

0x46b61c CMP	X10, #0

0x46b620 CSEL	X24, XZR, X13, #0

0x46b624 ADD	X12, X11, X12,LSL #3

0x46b628 CMP	X9, #0

0x46b62c CSEL	X25, XZR, X12, #0

0x46b630 CMP	X10, #1

0x46b634 B.LT	46b660

0x46b638 LDUR	X27, [X29, #400]

0x46b63c MOVN	X10, #0

0x46b640 ORR	X9, XZR, XZR

(2259) 0x46b644 STR	X10, [X13, X9,LSL #3]

(2259) 0x46b648 ADD	X9, X9, #1

(2259) 0x46b64c LDR	X11, [X15]

(2259) 0x46b650 CMP	X9, X11

(2259) 0x46b654 B.LT	46b644

0x46b658 LDR	X9, [X27]

0x46b65c B	46b664

0x46b660 LDUR	X27, [X29, #400]

0x46b664 LDR	X10, [X29, #256]

0x46b668 CMP	X9, #1

0x46b66c LDR	X9, [X29, #136]

0x46b670 STP	X10, X15, [SP, #80]

0x46b674 LDP	X10, X11, [X29, #240]

0x46b678 STR	X9, [SP, #96]

0x46b67c STUR	X11, [X29, #384]

0x46b680 STR	X10, [SP, #72]

0x46b684 LDP	X10, X11, [X29, #224]

0x46b688 STUR	X11, [X29, #376]

0x46b68c STR	X10, [SP, #64]

0x46b690 LDP	X9, X11, [X29, #208]

0x46b694 STUR	X11, [X29, #464]

0x46b698 LDP	X10, X11, [X29, #192]

0x46b69c STP	X11, X9, [X29, #920]

0x46b6a0 STR	X10, [SP, #56]

0x46b6a4 LDP	X10, X11, [X29, #176]

0x46b6a8 STR	X10, [SP, #112]

0x46b6ac LDR	X10, [X29, #168]

0x46b6b0 STUR	X11, [X29, #456]

0x46b6b4 STR	X10, [SP, #48]

0x46b6b8 LDR	X10, [X29, #160]

0x46b6bc STR	X10, [SP, #40]

0x46b6c0 LDR	X10, [X29, #152]

0x46b6c4 STR	X10, [SP, #120]

0x46b6c8 B.LT	46b6f4

0x46b6cc MOVN	X10, #0

0x46b6d0 ORR	X9, XZR, XZR

0x46b6d4 HINT	#0

0x46b6d8 HINT	#0

0x46b6dc HINT	#0

(2258) 0x46b6e0 STR	X10, [X12, X9,LSL #3]

(2258) 0x46b6e4 ADD	X9, X9, #1

(2258) 0x46b6e8 LDR	X11, [X27]

(2258) 0x46b6ec CMP	X9, X11

(2258) 0x46b6f0 B.LT	46b6e0

0x46b6f4 LDR	X8, [X8]

0x46b6f8 STP	XZR, XZR, [X29, #984]

0x46b6fc ADD	X9, X28, #1

0x46b700 LDR	X10, [X14]

0x46b704 STR	X14, [SP, #104]

0x46b708 LDR	X22, [X8, X28,LSL #3]

0x46b70c STR	X9, [SP, #8]

0x46b710 LDR	X9, [X8, X9,LSL #3]

0x46b714 LDR	X8, [X19]

0x46b718 STUR	X10, [X29, #392]

0x46b71c STP	X13, X12, [SP, #16]

0x46b720 CMP	X8, #1

0x46b724 STP	X9, X19, [X29, #936]

0x46b728 B.NE	46ba20

0x46b72c CMP	X22, X9

0x46b730 B.GE	46bf90

0x46b734 LDR	X8, [SP, #96]

0x46b738 ORR	X18, XZR, X22

0x46b73c LDR	X8, [X8]

0x46b740 STUR	X8, [X29, #440]

0x46b744 LDR	X8, [SP, #120]

0x46b748 LDR	X8, [X8]

0x46b74c STR	X8, [SP, #144]

0x46b750 LDP	X9, X8, [SP, #40]

0x46b754 LDR	X12, [X8]

0x46b758 LDR	X8, [SP, #112]

0x46b75c LDR	X11, [X9]

0x46b760 LDR	X13, [X8]

0x46b764 LDR	X8, [SP, #56]

0x46b768 LDR	X14, [X8]

0x46b76c LDP	X9, X8, [X29, #920]

0x46b770 LDR	X15, [X9]

0x46b774 LDR	X16, [X8]

0x46b778 LDP	X9, X8, [SP, #64]

0x46b77c LDR	X17, [X9]

0x46b780 LDR	X0, [X8]

0x46b784 B	46b79c

  (2251) 0x46b788 LDUR	X8, [X29, #424]

  (2251) 0x46b78c LDUR	X27, [X29, #400]

  (2251) 0x46b790 ADD	X18, X18, #1

  (2251) 0x46b794 CMP	X18, X8

  (2251) 0x46b798 B.EQ	46bf90

  (2251) 0x46b79c LDUR	X8, [X29, #440]

  (2251) 0x46b7a0 LDP	X2, X1, [X29, #984]

  (2251) 0x46b7a4 LDR	X10, [X8, X18,LSL #3]

  (2251) 0x46b7a8 LDUR	X8, [X29, #392]

  (2251) 0x46b7ac STR	X1, [X8, X18,LSL #3]

  (2251) 0x46b7b0 LDR	X8, [X27]

  (2251) 0x46b7b4 CBZ	X8, 46b7c4

  (2251) 0x46b7b8 LDUR	X8, [X29, #472]

  (2251) 0x46b7bc LDR	X9, [SP, #144]

  (2251) 0x46b7c0 STR	X8, [X9, X18,LSL #3]

  (2251) 0x46b7c4 ADD	X3, X10, #1

  (2251) 0x46b7c8 LDR	X4, [X11, X10,LSL #3]

  (2251) 0x46b7cc STUR	X10, [X29, #448]

  (2251) 0x46b7d0 LDR	X8, [X11, X3,LSL #3]

  (2251) 0x46b7d4 CMP	X4, X8

  (2251) 0x46b7d8 B.GE	46b90c

  (2251) 0x46b7dc LDUR	X8, [X29, #456]

  (2251) 0x46b7e0 LDR	X5, [X8]

  (2251) 0x46b7e4 LDP	X9, X8, [X29, #920]

  (2251) 0x46b7e8 LDR	X6, [X9]

  (2251) 0x46b7ec LDR	X7, [X8]

  (2251) 0x46b7f0 B	46b810

0x46b7f4 HINT	#0

0x46b7f8 HINT	#0

0x46b7fc HINT	#0

    (2254) 0x46b800 LDR	X8, [X11, X3,LSL #3]

    (2254) 0x46b804 ADD	X4, X4, #1

    (2254) 0x46b808 CMP	X4, X8

    (2254) 0x46b80c B.GE	46b90c

    (2254) 0x46b810 LDR	X27, [X12, X4,LSL #3]

    (2254) 0x46b814 LDR	X8, [X13, X27,LSL #3]

    (2254) 0x46b818 CMP	X8, #1

    (2254) 0x46b81c B.LT	46b840

    (2254) 0x46b820 LDR	X8, [X5, X27,LSL #3]

    (2254) 0x46b824 LDR	X9, [X24, X8,LSL #3]

    (2254) 0x46b828 CMP	X9, X1

    (2254) 0x46b82c B.GE	46b840

    (2254) 0x46b830 LDUR	X9, [X29, #480]

    (2254) 0x46b834 STR	X9, [X24, X8,LSL #3]

    (2254) 0x46b838 ADD	X8, X9, #1

    (2254) 0x46b83c STUR	X8, [X29, #480]

    (2254) 0x46b840 ADD	X28, X27, #1

    (2254) 0x46b844 LDR	X30, [X11, X27,LSL #3]

    (2254) 0x46b848 LDR	X10, [X11, X28,LSL #3]

    (2254) 0x46b84c CMP	X30, X10

    (2254) 0x46b850 B.GE	46b8ac

    (2254) 0x46b854 LDUR	X8, [X29, #456]

    (2254) 0x46b858 LDR	X9, [X8]

    (2254) 0x46b85c B	46b86c

      (2256) 0x46b860 ADD	X30, X30, #1

      (2256) 0x46b864 CMP	X30, X10

      (2256) 0x46b868 B.GE	46b8ac

      (2256) 0x46b86c LDR	X8, [X12, X30,LSL #3]

      (2256) 0x46b870 LDR	X19, [X13, X8,LSL #3]

      (2256) 0x46b874 CMP	X19, #1

      (2256) 0x46b878 B.LT	46b860

      (2256) 0x46b87c LDR	X8, [X9, X8,LSL #3]

      (2256) 0x46b880 CMP	X8, X18

      (2256) 0x46b884 B.EQ	46b860

      (2256) 0x46b888 LDR	X19, [X24, X8,LSL #3]

      (2256) 0x46b88c CMP	X19, X1

      (2256) 0x46b890 B.GE	46b860

      (2256) 0x46b894 LDUR	X10, [X29, #480]

      (2256) 0x46b898 STR	X10, [X24, X8,LSL #3]

      (2256) 0x46b89c ADD	X8, X10, #1

      (2256) 0x46b8a0 STUR	X8, [X29, #480]

      (2256) 0x46b8a4 LDR	X10, [X11, X28,LSL #3]

      (2256) 0x46b8a8 B	46b860

    (2254) 0x46b8ac LDR	X27, [X14, X27,LSL #3]

    (2254) 0x46b8b0 LDR	X9, [X14, X28,LSL #3]

    (2254) 0x46b8b4 CMP	X27, X9

    (2254) 0x46b8b8 B.GE	46b800

    (2254) 0x46b8bc LDUR	X8, [X29, #464]

    (2254) 0x46b8c0 LDR	X10, [X8]

    (2254) 0x46b8c4 B	46b8d4

      (2255) 0x46b8c8 ADD	X27, X27, #1

      (2255) 0x46b8cc CMP	X27, X9

      (2255) 0x46b8d0 B.GE	46b800

      (2255) 0x46b8d4 LDR	X8, [X6, X27,LSL #3]

      (2255) 0x46b8d8 LDR	X19, [X7, X8,LSL #3]

      (2255) 0x46b8dc CMP	X19, #1

      (2255) 0x46b8e0 B.LT	46b8c8

      (2255) 0x46b8e4 LDR	X8, [X10, X8,LSL #3]

      (2255) 0x46b8e8 LDR	X19, [X25, X8,LSL #3]

      (2255) 0x46b8ec CMP	X19, X2

      (2255) 0x46b8f0 B.GE	46b8c8

      (2255) 0x46b8f4 LDUR	X9, [X29, #472]

      (2255) 0x46b8f8 STR	X9, [X25, X8,LSL #3]

      (2255) 0x46b8fc ADD	X8, X9, #1

      (2255) 0x46b900 STUR	X8, [X29, #472]

      (2255) 0x46b904 LDR	X9, [X14, X28,LSL #3]

      (2255) 0x46b908 B	46b8c8

  (2251) 0x46b90c LDUR	X8, [X29, #448]

  (2251) 0x46b910 LDR	X9, [X14, X3,LSL #3]

  (2251) 0x46b914 LDR	X8, [X14, X8,LSL #3]

  (2251) 0x46b918 CMP	X8, X9

  (2251) 0x46b91c B.GE	46b788

(2252) 0x46b920 LDUR	X9, [X29, #464]

(2252) 0x46b924 LDR	X4, [X9]

(2252) 0x46b928 LDP	X10, X9, [X29, #888]

(2252) 0x46b92c LDR	X5, [X10]

(2252) 0x46b930 LDR	X6, [X9]

(2252) 0x46b934 B	46b950

0x46b938 HINT	#0

0x46b93c HINT	#0

(2252) 0x46b940 LDR	X9, [X14, X3,LSL #3]

(2252) 0x46b944 ADD	X8, X8, #1

(2252) 0x46b948 CMP	X8, X9

(2252) 0x46b94c B.GE	46b788

(2252) 0x46b950 LDR	X27, [X15, X8,LSL #3]

(2252) 0x46b954 LDR	X9, [X16, X27,LSL #3]

(2252) 0x46b958 CMP	X9, #1

(2252) 0x46b95c B.LT	46b980

(2252) 0x46b960 LDR	X9, [X4, X27,LSL #3]

(2252) 0x46b964 LDR	X10, [X25, X9,LSL #3]

(2252) 0x46b968 CMP	X10, X2

(2252) 0x46b96c B.GE	46b980

(2252) 0x46b970 LDUR	X10, [X29, #472]

(2252) 0x46b974 STR	X10, [X25, X9,LSL #3]

(2252) 0x46b978 ADD	X9, X10, #1

(2252) 0x46b97c STUR	X9, [X29, #472]

(2252) 0x46b980 ADD	X7, X27, #1

(2252) 0x46b984 LDR	X9, [X17, X27,LSL #3]

(2252) 0x46b988 LDR	X10, [X17, X7,LSL #3]

(2252) 0x46b98c B	46b9a4

0x46b990 HINT	#0

0x46b994 HINT	#0

0x46b998 HINT	#0

0x46b99c HINT	#0

  (2253) 0x46b9a0 ADD	X9, X9, #1

  (2253) 0x46b9a4 CMP	X9, X10

  (2253) 0x46b9a8 B.GE	46b9e0

  (2253) 0x46b9ac LDR	X28, [X5, X9,LSL #3]

  (2253) 0x46b9b0 CMP	X28, X18

  (2253) 0x46b9b4 B.EQ	46b9a0

  (2253) 0x46b9b8 LDR	X19, [X24, X28,LSL #3]

  (2253) 0x46b9bc CMP	X19, X1

  (2253) 0x46b9c0 B.GE	46b9a0

  (2253) 0x46b9c4 LDUR	X10, [X29, #480]

  (2253) 0x46b9c8 STR	X10, [X24, X28,LSL #3]

  (2253) 0x46b9cc ADD	X10, X10, #1

  (2253) 0x46b9d0 STUR	X10, [X29, #480]

  (2253) 0x46b9d4 LDR	X10, [X17, X7,LSL #3]

  (2253) 0x46b9d8 B	46b9a0

0x46b9dc HINT	#0

(2252) 0x46b9e0 LDR	X9, [X0, X27,LSL #3]

(2252) 0x46b9e4 LDR	X10, [X0, X7,LSL #3]

(2252) 0x46b9e8 B	46b9f0

  (2257) 0x46b9ec ADD	X9, X9, #1

  (2257) 0x46b9f0 CMP	X9, X10

  (2257) 0x46b9f4 B.GE	46b940

  (2257) 0x46b9f8 LDR	X27, [X6, X9,LSL #3]

  (2257) 0x46b9fc LDR	X19, [X25, X27,LSL #3]

  (2257) 0x46ba00 CMP	X19, X2

  (2257) 0x46ba04 B.GE	46b9ec

  (2257) 0x46ba08 LDUR	X10, [X29, #472]

  (2257) 0x46ba0c STR	X10, [X25, X27,LSL #3]

  (2257) 0x46ba10 ADD	X10, X10, #1

  (2257) 0x46ba14 STUR	X10, [X29, #472]

  (2257) 0x46ba18 LDR	X10, [X0, X7,LSL #3]

  (2257) 0x46ba1c B	46b9ec

0x46ba20 CMP	X22, X9

0x46ba24 B.GE	46bf90

0x46ba28 LDR	X8, [SP, #96]

0x46ba2c MOVZ	W4, #1

0x46ba30 ORR	X1, XZR, XZR

0x46ba34 ORR	X3, XZR, XZR

0x46ba38 ORR	X5, XZR, X22

0x46ba3c LDR	X9, [X8]

0x46ba40 LDR	X8, [SP, #120]

0x46ba44 LDR	X8, [X8]

0x46ba48 STP	X8, X9, [SP, #128]

0x46ba4c LDP	X9, X8, [SP, #40]

0x46ba50 LDR	X12, [X8]

0x46ba54 LDR	X8, [SP, #112]

0x46ba58 LDR	X11, [X9]

0x46ba5c LDR	X13, [X8]

0x46ba60 LDR	X8, [SP, #56]

0x46ba64 LDR	X14, [X8]

0x46ba68 LDP	X10, X8, [X29, #920]

0x46ba6c LDR	X9, [X10]

0x46ba70 LDR	X8, [X8]

0x46ba74 STP	X8, X9, [X29, #952]

0x46ba78 LDP	X9, X8, [SP, #64]

0x46ba7c LDR	X2, [X9]

0x46ba80 LDR	X6, [X8]

0x46ba84 B	46ba94

    (2241) 0x46ba88 ADD	X5, X5, #1

    (2241) 0x46ba8c CMP	X5, X16

    (2241) 0x46ba90 B.EQ	46bf90

    (2241) 0x46ba94 LDR	X8, [SP, #136]

    (2241) 0x46ba98 LDUR	X9, [X29, #392]

    (2241) 0x46ba9c ORR	X7, XZR, X3

    (2241) 0x46baa0 ORR	X30, XZR, X1

    (2241) 0x46baa4 LDR	X15, [X8, X5,LSL #3]

    (2241) 0x46baa8 LDUR	X8, [X29, #480]

    (2241) 0x46baac STR	X8, [X9, X5,LSL #3]

    (2241) 0x46bab0 LDR	X8, [X27]

    (2241) 0x46bab4 CBZ	X8, 46bac4

    (2241) 0x46bab8 LDUR	X8, [X29, #472]

    (2241) 0x46babc LDR	X9, [SP, #128]

    (2241) 0x46bac0 STR	X8, [X9, X5,LSL #3]

    (2241) 0x46bac4 ADD	X16, X15, #1

    (2241) 0x46bac8 LDR	X10, [X11, X15,LSL #3]

    (2241) 0x46bacc STR	X15, [SP, #144]

    (2241) 0x46bad0 ORR	X3, XZR, X7

    (2241) 0x46bad4 ORR	X1, XZR, X30

    (2241) 0x46bad8 LDR	X8, [X11, X16,LSL #3]

    (2241) 0x46badc CMP	X10, X8

    (2241) 0x46bae0 B.GE	46bc60

    (2241) 0x46bae4 LDUR	X8, [X29, #456]

    (2241) 0x46bae8 ORR	X1, XZR, X30

    (2241) 0x46baec ORR	X3, XZR, X7

    (2241) 0x46baf0 LDR	X9, [X8]

    (2241) 0x46baf4 LDP	X8, X15, [X29, #920]

    (2241) 0x46baf8 LDR	X8, [X8]

    (2241) 0x46bafc LDR	X0, [X15]

    (2241) 0x46bb00 B	46bb14

      (2247) 0x46bb04 LDR	X15, [X11, X16,LSL #3]

      (2247) 0x46bb08 ADD	X10, X10, #1

      (2247) 0x46bb0c CMP	X10, X15

      (2247) 0x46bb10 B.GE	46bc60

      (2247) 0x46bb14 LDR	X27, [X12, X10,LSL #3]

      (2247) 0x46bb18 LDR	X15, [X13, X27,LSL #3]

      (2247) 0x46bb1c CMP	X15, #1

      (2247) 0x46bb20 B.LT	46bb48

      (2247) 0x46bb24 LDR	X15, [X9, X27,LSL #3]

      (2247) 0x46bb28 LDR	X17, [X24, X15,LSL #3]

      (2247) 0x46bb2c SUBS	X17, X17, X30

      (2247) 0x46bb30 B.GE	46bb60

      (2247) 0x46bb34 STR	X1, [X24, X15,LSL #3]

      (2247) 0x46bb38 SUB	X15, X1, X30

      (2247) 0x46bb3c MOVZ	W17, #2

      (2247) 0x46bb40 ADD	X1, X1, #1

      (2247) 0x46bb44 STR	X17, [X20, X15,LSL #3]

      (2247) 0x46bb48 ADD	X28, X27, #1

      (2247) 0x46bb4c LDR	X17, [X11, X27,LSL #3]

      (2247) 0x46bb50 LDR	X15, [X11, X28,LSL #3]

      (2247) 0x46bb54 CMP	X17, X15

      (2247) 0x46bb58 B.LT	46bb80

      (2247) 0x46bb5c B	46bbec

      (2247) 0x46bb60 LDR	X15, [X20, X17,LSL #3]

      (2247) 0x46bb64 ADD	X15, X15, #2

      (2247) 0x46bb68 STR	X15, [X20, X17,LSL #3]

      (2247) 0x46bb6c ADD	X28, X27, #1

      (2247) 0x46bb70 LDR	X17, [X11, X27,LSL #3]

      (2247) 0x46bb74 LDR	X15, [X11, X28,LSL #3]

      (2247) 0x46bb78 CMP	X17, X15

      (2247) 0x46bb7c B.GE	46bbec

      (2247) 0x46bb80 LDUR	X15, [X29, #456]

      (2247) 0x46bb84 LDR	X15, [X15]

      (2247) 0x46bb88 B	46bbb0

        (2249) 0x46bb8c LDR	X18, [X20, X19,LSL #3]

        (2249) 0x46bb90 ADD	X18, X18, #1

        (2249) 0x46bb94 STR	X18, [X20, X19,LSL #3]

        (2249) 0x46bb98 HINT	#0

        (2249) 0x46bb9c HINT	#0

        (2249) 0x46bba0 LDR	X18, [X11, X28,LSL #3]

        (2249) 0x46bba4 ADD	X17, X17, #1

        (2249) 0x46bba8 CMP	X17, X18

        (2249) 0x46bbac B.GE	46bbec

        (2249) 0x46bbb0 LDR	X18, [X12, X17,LSL #3]

        (2249) 0x46bbb4 LDR	X19, [X13, X18,LSL #3]

        (2249) 0x46bbb8 CMP	X19, #1

        (2249) 0x46bbbc B.LT	46bba0

        (2249) 0x46bbc0 LDR	X18, [X15, X18,LSL #3]

        (2249) 0x46bbc4 CMP	X18, X5

        (2249) 0x46bbc8 B.EQ	46bba0

        (2249) 0x46bbcc LDR	X19, [X24, X18,LSL #3]

        (2249) 0x46bbd0 SUBS	X19, X19, X30

        (2249) 0x46bbd4 B.GE	46bb8c

        (2249) 0x46bbd8 STR	X1, [X24, X18,LSL #3]

        (2249) 0x46bbdc SUB	X18, X1, X30

        (2249) 0x46bbe0 ADD	X1, X1, #1

        (2249) 0x46bbe4 STR	X4, [X20, X18,LSL #3]

        (2249) 0x46bbe8 B	46bba0

      (2247) 0x46bbec LDR	X17, [X14, X27,LSL #3]

      (2247) 0x46bbf0 LDR	X15, [X14, X28,LSL #3]

      (2247) 0x46bbf4 CMP	X17, X15

      (2247) 0x46bbf8 B.GE	46bb04

      (2247) 0x46bbfc LDUR	X15, [X29, #464]

      (2247) 0x46bc00 LDR	X15, [X15]

      (2247) 0x46bc04 B	46bc24

        (2248) 0x46bc08 LDR	X18, [X21, X19,LSL #3]

        (2248) 0x46bc0c ADD	X18, X18, #1

        (2248) 0x46bc10 STR	X18, [X21, X19,LSL #3]

        (2248) 0x46bc14 LDR	X18, [X14, X28,LSL #3]

        (2248) 0x46bc18 ADD	X17, X17, #1

        (2248) 0x46bc1c CMP	X17, X18

        (2248) 0x46bc20 B.GE	46bb04

        (2248) 0x46bc24 LDR	X18, [X8, X17,LSL #3]

        (2248) 0x46bc28 LDR	X19, [X0, X18,LSL #3]

        (2248) 0x46bc2c CMP	X19, #1

        (2248) 0x46bc30 B.LT	46bc14

        (2248) 0x46bc34 LDR	X18, [X15, X18,LSL #3]

        (2248) 0x46bc38 LDR	X19, [X25, X18,LSL #3]

        (2248) 0x46bc3c SUBS	X19, X19, X7

        (2248) 0x46bc40 B.GE	46bc08

        (2248) 0x46bc44 STR	X3, [X25, X18,LSL #3]

        (2248) 0x46bc48 SUB	X18, X3, X7

        (2248) 0x46bc4c ADD	X3, X3, #1

        (2248) 0x46bc50 STR	X4, [X21, X18,LSL #3]

        (2248) 0x46bc54 B	46bc14

0x46bc58 HINT	#0

0x46bc5c HINT	#0

    (2241) 0x46bc60 LDR	X8, [SP, #144]

    (2241) 0x46bc64 LDR	X9, [X14, X16,LSL #3]

    (2241) 0x46bc68 LDR	X8, [X14, X8,LSL #3]

    (2241) 0x46bc6c CMP	X8, X9

    (2241) 0x46bc70 B.GE	46bde0

    (2241) 0x46bc74 LDUR	X9, [X29, #464]

    (2241) 0x46bc78 LDP	X10, X15, [X29, #888]

    (2241) 0x46bc7c LDR	X9, [X9]

    (2241) 0x46bc80 LDR	X10, [X10]

    (2241) 0x46bc84 LDR	X17, [X15]

    (2241) 0x46bc88 B	46bc9c

      (2244) 0x46bc8c LDR	X15, [X14, X16,LSL #3]

      (2244) 0x46bc90 ADD	X8, X8, #1

      (2244) 0x46bc94 CMP	X8, X15

      (2244) 0x46bc98 B.GE	46bde0

      (2244) 0x46bc9c LDUR	X15, [X29, #448]

      (2244) 0x46bca0 LDR	X27, [X15, X8,LSL #3]

      (2244) 0x46bca4 LDUR	X15, [X29, #440]

      (2244) 0x46bca8 LDR	X15, [X15, X27,LSL #3]

      (2244) 0x46bcac CMP	X15, #1

      (2244) 0x46bcb0 B.LT	46bcd8

      (2244) 0x46bcb4 LDR	X15, [X9, X27,LSL #3]

      (2244) 0x46bcb8 LDR	X18, [X25, X15,LSL #3]

      (2244) 0x46bcbc SUBS	X18, X18, X7

      (2244) 0x46bcc0 B.GE	46bd00

      (2244) 0x46bcc4 STR	X3, [X25, X15,LSL #3]

      (2244) 0x46bcc8 SUB	X15, X3, X7

      (2244) 0x46bccc MOVZ	W18, #2

      (2244) 0x46bcd0 ADD	X3, X3, #1

      (2244) 0x46bcd4 STR	X18, [X21, X15,LSL #3]

      (2244) 0x46bcd8 LDR	X15, [X2, X27,LSL #3]

      (2244) 0x46bcdc ADD	X0, X27, #1

      (2244) 0x46bce0 LDR	X18, [X2, X0,LSL #3]

      (2244) 0x46bce4 CMP	X15, X18

      (2244) 0x46bce8 B.LT	46bd40

      (2244) 0x46bcec B	46bd78

0x46bcf0 HINT	#0

0x46bcf4 HINT	#0

0x46bcf8 HINT	#0

0x46bcfc HINT	#0

      (2244) 0x46bd00 LDR	X15, [X21, X18,LSL #3]

      (2244) 0x46bd04 ADD	X15, X15, #2

      (2244) 0x46bd08 STR	X15, [X21, X18,LSL #3]

      (2244) 0x46bd0c LDR	X15, [X2, X27,LSL #3]

      (2244) 0x46bd10 ADD	X0, X27, #1

      (2244) 0x46bd14 LDR	X18, [X2, X0,LSL #3]

      (2244) 0x46bd18 CMP	X15, X18

      (2244) 0x46bd1c B.LT	46bd40

      (2244) 0x46bd20 B	46bd78

        (2246) 0x46bd24 LDR	X18, [X20, X19,LSL #3]

        (2246) 0x46bd28 ADD	X18, X18, #1

        (2246) 0x46bd2c STR	X18, [X20, X19,LSL #3]

        (2246) 0x46bd30 ADD	X15, X15, #1

        (2246) 0x46bd34 LDR	X18, [X2, X0,LSL #3]

        (2246) 0x46bd38 CMP	X15, X18

        (2246) 0x46bd3c B.GE	46bd78

        (2246) 0x46bd40 LDR	X18, [X10, X15,LSL #3]

        (2246) 0x46bd44 CMP	X18, X5

        (2246) 0x46bd48 B.EQ	46bd30

        (2246) 0x46bd4c LDR	X19, [X24, X18,LSL #3]

        (2246) 0x46bd50 SUBS	X19, X19, X30

        (2246) 0x46bd54 B.GE	46bd24

        (2246) 0x46bd58 STR	X1, [X24, X18,LSL #3]

        (2246) 0x46bd5c SUB	X18, X1, X30

        (2246) 0x46bd60 ADD	X1, X1, #1

        (2246) 0x46bd64 ADD	X15, X15, #1

        (2246) 0x46bd68 STR	X4, [X20, X18,LSL #3]

        (2246) 0x46bd6c LDR	X18, [X2, X0,LSL #3]

        (2246) 0x46bd70 CMP	X15, X18

        (2246) 0x46bd74 B.LT	46bd40

      (2244) 0x46bd78 LDR	X15, [X6, X27,LSL #3]

      (2244) 0x46bd7c LDR	X18, [X6, X0,LSL #3]

      (2244) 0x46bd80 CMP	X15, X18

      (2244) 0x46bd84 B.LT	46bdac

      (2244) 0x46bd88 B	46bc8c

        (2245) 0x46bd8c STR	X3, [X25, X18,LSL #3]

        (2245) 0x46bd90 SUB	X18, X3, X7

        (2245) 0x46bd94 ADD	X3, X3, #1

        (2245) 0x46bd98 ADD	X15, X15, #1

        (2245) 0x46bd9c STR	X4, [X21, X18,LSL #3]

        (2245) 0x46bda0 LDR	X18, [X6, X0,LSL #3]

        (2245) 0x46bda4 CMP	X15, X18

        (2245) 0x46bda8 B.GE	46bc8c

        (2245) 0x46bdac LDR	X18, [X17, X15,LSL #3]

        (2245) 0x46bdb0 LDR	X19, [X25, X18,LSL #3]

        (2245) 0x46bdb4 SUBS	X19, X19, X7

        (2245) 0x46bdb8 B.LT	46bd8c

        (2245) 0x46bdbc LDR	X18, [X21, X19,LSL #3]

        (2245) 0x46bdc0 ADD	X15, X15, #1

        (2245) 0x46bdc4 ADD	X18, X18, #1

        (2245) 0x46bdc8 STR	X18, [X21, X19,LSL #3]

        (2245) 0x46bdcc LDR	X18, [X6, X0,LSL #3]

        (2245) 0x46bdd0 CMP	X15, X18

        (2245) 0x46bdd4 B.LT	46bdac

      (2244) 0x46bdd8 B	46bc8c

0x46bddc HINT	#0

    (2241) 0x46bde0 LDUR	X16, [X29, #424]

    (2241) 0x46bde4 LDUR	X27, [X29, #400]

    (2241) 0x46bde8 CMP	X1, X30

    (2241) 0x46bdec B.LE	46be30

    (2241) 0x46bdf0 SUB	W8, W1, W30

    (2241) 0x46bdf4 ORR	X9, XZR, X30

    (2241) 0x46bdf8 TBZ	W8, #0, 46be24

    (2241) 0x46bdfc LDUR	X9, [X29, #432]

    (2241) 0x46be00 LDR	X8, [X20]

    (2241) 0x46be04 LDR	X9, [X9]

    (2241) 0x46be08 CMP	X8, X9

    (2241) 0x46be0c B.LT	46be1c

    (2241) 0x46be10 LDUR	X8, [X29, #480]

    (2241) 0x46be14 ADD	X8, X8, #1

    (2241) 0x46be18 STUR	X8, [X29, #480]

    (2241) 0x46be1c ADD	X9, X30, #1

    (2241) 0x46be20 STR	XZR, [X20]

    (2241) 0x46be24 ADD	X8, X30, #1

    (2241) 0x46be28 CMP	X1, X8

    (2241) 0x46be2c B.NE	46bf00

    (2241) 0x46be30 LDUR	X17, [X29, #432]

    (2241) 0x46be34 CMP	X3, X7

    (2241) 0x46be38 B.LE	46ba88

    (2241) 0x46be3c SUB	W8, W3, W7

    (2241) 0x46be40 ORR	X9, XZR, X7

    (2241) 0x46be44 TBZ	W8, #0, 46be6c

    (2241) 0x46be48 LDR	X8, [X21]

    (2241) 0x46be4c LDR	X9, [X17]

    (2241) 0x46be50 CMP	X8, X9

    (2241) 0x46be54 B.LT	46be64

    (2241) 0x46be58 LDUR	X8, [X29, #472]

    (2241) 0x46be5c ADD	X8, X8, #1

    (2241) 0x46be60 STUR	X8, [X29, #472]

    (2241) 0x46be64 ADD	X9, X7, #1

    (2241) 0x46be68 STR	XZR, [X21]

    (2241) 0x46be6c ADD	X8, X7, #1

    (2241) 0x46be70 CMP	X3, X8

    (2241) 0x46be74 B.EQ	46ba88

    (2241) 0x46be78 ADD	X10, X21, #8

    (2241) 0x46be7c SUB	X8, X3, X9

    (2241) 0x46be80 SUB	X10, X10, X7,LSL #3

    (2241) 0x46be84 ADD	X9, X10, X9,LSL #3

    (2241) 0x46be88 B	46be98

      (2250) 0x46be8c STR	XZR, [X9], #16

      (2250) 0x46be90 SUBS	X8, X8, #2

      (2250) 0x46be94 B.EQ	46ba88

      (2250) 0x46be98 LDUR	X10, [X9, #504]

      (2250) 0x46be9c LDR	X15, [X17]

      (2250) 0x46bea0 CMP	X10, X15

      (2250) 0x46bea4 B.GE	46bec0

      (2250) 0x46bea8 STUR	XZR, [X9, #504]

      (2250) 0x46beac LDR	X10, [X9]

      (2250) 0x46beb0 LDR	X15, [X17]

      (2250) 0x46beb4 CMP	X10, X15

      (2250) 0x46beb8 B.LT	46be8c

      (2250) 0x46bebc B	46bee0

      (2250) 0x46bec0 LDUR	X10, [X29, #472]

      (2250) 0x46bec4 ADD	X10, X10, #1

      (2250) 0x46bec8 STUR	X10, [X29, #472]

      (2250) 0x46becc STUR	XZR, [X9, #504]

      (2250) 0x46bed0 LDR	X10, [X9]

      (2250) 0x46bed4 LDR	X15, [X17]

      (2250) 0x46bed8 CMP	X10, X15

      (2250) 0x46bedc B.LT	46be8c

      (2250) 0x46bee0 LDUR	X10, [X29, #472]

      (2250) 0x46bee4 ADD	X10, X10, #1

      (2250) 0x46bee8 STUR	X10, [X29, #472]

      (2250) 0x46beec B	46be8c

0x46bef0 HINT	#0

0x46bef4 HINT	#0

0x46bef8 HINT	#0

0x46befc HINT	#0

  (2243) 0x46bf00 ADD	X10, X20, #8

  (2243) 0x46bf04 SUB	X8, X1, X9

  (2243) 0x46bf08 SUB	X10, X10, X30,LSL #3

  (2243) 0x46bf0c ADD	X9, X10, X9,LSL #3

  (2243) 0x46bf10 B	46bf2c

0x46bf14 HINT	#0

0x46bf18 HINT	#0

0x46bf1c HINT	#0

  (2243) 0x46bf20 STR	XZR, [X9], #16

  (2243) 0x46bf24 SUBS	X8, X8, #2

  (2243) 0x46bf28 B.EQ	46be30

  (2243) 0x46bf2c LDUR	X17, [X29, #432]

  (2243) 0x46bf30 LDUR	X10, [X9, #504]

  (2243) 0x46bf34 LDR	X15, [X17]

  (2243) 0x46bf38 CMP	X10, X15

  (2243) 0x46bf3c B.GE	46bf60

  (2243) 0x46bf40 STUR	XZR, [X9, #504]

  (2243) 0x46bf44 LDR	X10, [X9]

  (2243) 0x46bf48 LDR	X15, [X17]

  (2243) 0x46bf4c CMP	X10, X15

  (2243) 0x46bf50 B.LT	46bf20

  (2243) 0x46bf54 B	46bf80

0x46bf58 HINT	#0

0x46bf5c HINT	#0

(2242) 0x46bf60 LDUR	X10, [X29, #480]

(2242) 0x46bf64 ADD	X10, X10, #1

(2242) 0x46bf68 STUR	X10, [X29, #480]

(2242) 0x46bf6c STUR	XZR, [X9, #504]

(2242) 0x46bf70 LDR	X10, [X9]

(2242) 0x46bf74 LDR	X15, [X17]

(2242) 0x46bf78 CMP	X10, X15

(2242) 0x46bf7c B.LT	46bf20

  (2243) 0x46bf80 LDUR	X10, [X29, #480]

  (2243) 0x46bf84 ADD	X10, X10, #1

  (2243) 0x46bf88 STUR	X10, [X29, #480]

  (2243) 0x46bf8c B	46bf20

0x46bf90 LDP	X10, X19, [SP, #80]

0x46bf94 LDR	X9, [SP, #120]

0x46bf98 SUB	X0, X29, #32

0x46bf9c SUB	X2, X29, #40

0x46bfa0 LDR	X8, [X19]

0x46bfa4 LDR	X9, [X9]

0x46bfa8 LDR	X4, [X10]

0x46bfac LDUR	X10, [X29, #392]

0x46bfb0 ADD	X1, X10, X8,LSL #3

0x46bfb4 ADD	X3, X9, X8,LSL #3

0x46bfb8 BL	4aedd0

0x46bfbc LDR	X8, [X19]

0x46bfc0 LDR	X12, [SP, #16]

0x46bfc4 CMP	X8, #1

0x46bfc8 B.LT	46bff4

0x46bfcc MOVN	X9, #0

0x46bfd0 ORR	X11, XZR, X19

0x46bfd4 ORR	X8, XZR, XZR

0x46bfd8 HINT	#0

0x46bfdc HINT	#0

(2240) 0x46bfe0 STR	X9, [X12, X8,LSL #3]

(2240) 0x46bfe4 ADD	X8, X8, #1

(2240) 0x46bfe8 LDR	X10, [X11]

(2240) 0x46bfec CMP	X8, X10

(2240) 0x46bff0 B.LT	46bfe0

0x46bff4 LDP	X8, X9, [X29, #264]

0x46bff8 LDR	X11, [SP, #24]

0x46bffc STUR	X8, [X29, #448]

0x46c000 LDR	X8, [X27]

0x46c004 STUR	X9, [X29, #392]

0x46c008 CMP	X8, #1

0x46c00c B.LT	46c034

0x46c010 MOVN	X9, #0

0x46c014 ORR	X8, XZR, XZR

0x46c018 HINT	#0

0x46c01c HINT	#0

(2239) 0x46c020 STR	X9, [X11, X8,LSL #3]

(2239) 0x46c024 ADD	X8, X8, #1

(2239) 0x46c028 LDR	X10, [X27]

(2239) 0x46c02c CMP	X8, X10

(2239) 0x46c030 B.LT	46c020

0x46c034 LDR	X8, [SP, #32]

0x46c038 ADRP	X0,

0x46c03c ADD	X0, X0, #864

0x46c040 LDR	W27, [X8]

0x46c044 ORR	W1, WZR, W27

0x46c048 BL	410070

0x46c04c ADRP	X0,

0x46c050 ADD	X0, X0, #888

0x46c054 ORR	W1, WZR, W27

0x46c058 BL	4105a0

0x46c05c CBZ	W0, 46c0c0

0x46c060 LDR	X8, [SP, #104]

0x46c064 LDR	X10, [SP, #88]

0x46c068 LDR	X9, [X8]

0x46c06c LDR	X8, [X10]

0x46c070 LDR	X9, [X9, X8,LSL #3]

0x46c074 CBZ	X9, 46c090

0x46c078 UBFM	X0, X9, #61, #60

0x46c07c ORR	X19, XZR, X10

0x46c080 BL	4ac440

0x46c084 LDUR	X8, [X29, #448]

0x46c088 STR	X0, [X8]

0x46c08c LDR	X8, [X19]

0x46c090 LDR	X9, [SP, #120]

0x46c094 LDR	X9, [X9]

0x46c098 LDR	X8, [X9, X8,LSL #3]

0x46c09c CBZ	X8, 46c0b0

0x46c0a0 UBFM	X0, X8, #61, #60

0x46c0a4 BL	4ac440

0x46c0a8 LDUR	X8, [X29, #392]

0x46c0ac STR	X0, [X8]

0x46c0b0 ADRP	X0,

0x46c0b4 ADD	X0, X0, #888

0x46c0b8 ORR	W1, WZR, W27

0x46c0bc BL	4104d0

0x46c0c0 ADRP	X0,

0x46c0c4 ADD	X0, X0, #912

0x46c0c8 ORR	W1, WZR, W27

0x46c0cc BL	410070

0x46c0d0 LDP	X17, X18, [X29, #936]

0x46c0d4 LDR	X0, [SP, #104]

0x46c0d8 SUB	X8, X17, #1

0x46c0dc LDUR	X30, [X29, #392]

0x46c0e0 CMP	X22, X8

0x46c0e4 ORR	X8, XZR, X22

0x46c0e8 B.GE	46c178

0x46c0ec LDP	X8, X9, [SP, #112]

0x46c0f0 LDR	X10, [SP, #96]

0x46c0f4 MOVZ	W13, #2

0x46c0f8 LDR	X12, [X0]

0x46c0fc ADD	X12, X12, X22,LSL #3

0x46c100 LDR	X11, [X9]

0x46c104 LDR	X10, [X10]

0x46c108 LDR	X8, [X8]

0x46c10c ORN	X9, XZR, X22

0x46c110 ADD	X9, X9, X17

0x46c114 ADD	X10, X10, X22,LSL #3

0x46c118 ADD	X11, X11, X22,LSL #3

0x46c11c B	46c148

(2238) 0x46c120 LDUR	X15, [X29, #480]

(2238) 0x46c124 SUBS	X9, X9, #1

(2238) 0x46c128 ADD	X10, X10, #8

(2238) 0x46c12c ADD	X14, X14, X15

(2238) 0x46c130 STR	X14, [X12], #8

(2238) 0x46c134 LDUR	X14, [X29, #472]

(2238) 0x46c138 LDR	X15, [X11]

(2238) 0x46c13c ADD	X14, X15, X14

(2238) 0x46c140 STR	X14, [X11], #8

(2238) 0x46c144 B.EQ	46c174

(2238) 0x46c148 LDP	X14, X15, [X12]

(2238) 0x46c14c CMP	X15, X14

(2238) 0x46c150 B.NE	46c120

(2238) 0x46c154 LDP	X16, X14, [X11]

(2238) 0x46c158 CMP	X14, X16

(2238) 0x46c15c ORR	X14, XZR, X15

(2238) 0x46c160 B.NE	46c120

(2238) 0x46c164 LDR	X14, [X10]

(2238) 0x46c168 STR	X13, [X8, X14,LSL #3]

(2238) 0x46c16c LDR	X14, [X12]

(2238) 0x46c170 B	46c120

0x46c174 SUB	X8, X17, #1

0x46c178 CMP	X22, X17

0x46c17c B.GE	46cac0

0x46c180 LDR	X11, [X0]

0x46c184 LDUR	X9, [X29, #480]

0x46c188 LDR	X10, [X11, X8,LSL #3]

0x46c18c ADD	X9, X10, X9

0x46c190 LDR	X10, [SP, #120]

0x46c194 STR	X9, [X11, X8,LSL #3]

0x46c198 LDUR	X9, [X29, #472]

0x46c19c LDR	X10, [X10]

0x46c1a0 LDR	X12, [X10, X8,LSL #3]

0x46c1a4 ADD	X9, X12, X9

0x46c1a8 LDR	X12, [SP, #8]

0x46c1ac STR	X9, [X10, X8,LSL #3]

0x46c1b0 LDR	X10, [SP, #80]

0x46c1b4 LDR	X11, [X11, X8,LSL #3]

0x46c1b8 LDR	X10, [X10]

0x46c1bc ADD	X10, X10, X12,LSL #4

0x46c1c0 LDR	X12, [X10]

0x46c1c4 CMP	X12, X11

0x46c1c8 B.NE	46c1f4

0x46c1cc LDR	X10, [X10, #8]

0x46c1d0 CMP	X10, X9

0x46c1d4 B.NE	46c1f4

0x46c1d8 LDR	X10, [SP, #96]

0x46c1dc LDR	X9, [SP, #112]

0x46c1e0 LDR	X10, [X10]

0x46c1e4 LDR	X9, [X9]

0x46c1e8 LDR	X8, [X10, X8,LSL #3]

0x46c1ec MOVZ	W10, #2

0x46c1f0 STR	X10, [X9, X8,LSL #3]

0x46c1f4 LDR	X8, [X18]

0x46c1f8 CMP	X8, #1

0x46c1fc B.NE	46c500

0x46c200 LDR	X8, [SP, #96]

0x46c204 LDP	X9, X10, [SP, #40]

0x46c208 LDR	X11, [SP, #112]

0x46c20c LDR	X16, [SP, #72]

0x46c210 LDR	X8, [X8]

0x46c214 LDP	X12, X15, [SP, #56]

0x46c218 LDP	X13, X14, [X29, #920]

0x46c21c LDR	X9, [X9]

0x46c220 LDR	X10, [X10]

0x46c224 LDR	X11, [X11]

0x46c228 LDR	X12, [X12]

0x46c22c LDR	X13, [X13]

0x46c230 LDR	X14, [X14]

0x46c234 LDR	X15, [X15]

0x46c238 LDR	X16, [X16]

0x46c23c B	46c250

  (2231) 0x46c240 LDUR	X17, [X29, #424]

  (2231) 0x46c244 ADD	X22, X22, #1

  (2231) 0x46c248 CMP	X22, X17

  (2231) 0x46c24c B.EQ	46cac0

  (2231) 0x46c250 LDR	X1, [X8, X22,LSL #3]

  (2231) 0x46c254 LDP	X18, X17, [X29, #984]

  (2231) 0x46c258 ADD	X0, X1, #1

  (2231) 0x46c25c LDR	X2, [X9, X1,LSL #3]

  (2231) 0x46c260 LDR	X3, [X9, X0,LSL #3]

  (2231) 0x46c264 CMP	X2, X3

  (2231) 0x46c268 B.GE	46c3cc

  (2231) 0x46c26c LDP	X4, X3, [X29, #960]

  (2231) 0x46c270 LDP	X5, X6, [X29, #920]

  (2231) 0x46c274 LDR	X3, [X3]

  (2231) 0x46c278 LDR	X4, [X4]

  (2231) 0x46c27c LDR	X5, [X5]

  (2231) 0x46c280 LDR	X6, [X6]

  (2231) 0x46c284 B	46c298

    (2235) 0x46c288 LDR	X7, [X9, X0,LSL #3]

    (2235) 0x46c28c ADD	X2, X2, #1

    (2235) 0x46c290 CMP	X2, X7

    (2235) 0x46c294 B.GE	46c3cc

    (2235) 0x46c298 LDR	X19, [X10, X2,LSL #3]

    (2235) 0x46c29c LDR	X7, [X11, X19,LSL #3]

    (2235) 0x46c2a0 CMP	X7, #1

    (2235) 0x46c2a4 B.LT	46c2d0

    (2235) 0x46c2a8 LDR	X7, [X3, X19,LSL #3]

    (2235) 0x46c2ac LDR	X20, [X24, X7,LSL #3]

    (2235) 0x46c2b0 CMP	X20, X17

    (2235) 0x46c2b4 B.GE	46c2d0

    (2235) 0x46c2b8 LDUR	X20, [X29, #480]

    (2235) 0x46c2bc STR	X20, [X24, X7,LSL #3]

    (2235) 0x46c2c0 STR	X7, [X4, X20,LSL #3]

    (2235) 0x46c2c4 LDUR	X7, [X29, #480]

    (2235) 0x46c2c8 ADD	X7, X7, #1

    (2235) 0x46c2cc STUR	X7, [X29, #480]

    (2235) 0x46c2d0 ADD	X7, X19, #1

    (2235) 0x46c2d4 LDR	X20, [X9, X19,LSL #3]

    (2235) 0x46c2d8 LDR	X23, [X9, X7,LSL #3]

    (2235) 0x46c2dc CMP	X20, X23

    (2235) 0x46c2e0 B.GE	46c360

    (2235) 0x46c2e4 LDP	X26, X21, [X29, #960]

    (2235) 0x46c2e8 LDR	X21, [X21]

    (2235) 0x46c2ec LDR	X26, [X26]

    (2235) 0x46c2f0 B	46c30c

0x46c2f4 HINT	#0

0x46c2f8 HINT	#0

0x46c2fc HINT	#0

      (2237) 0x46c300 ADD	X20, X20, #1

      (2237) 0x46c304 CMP	X20, X23

      (2237) 0x46c308 B.GE	46c360

      (2237) 0x46c30c LDR	X27, [X10, X20,LSL #3]

      (2237) 0x46c310 LDR	X28, [X11, X27,LSL #3]

      (2237) 0x46c314 CMP	X28, #1

      (2237) 0x46c318 B.LT	46c300

      (2237) 0x46c31c LDR	X27, [X21, X27,LSL #3]

      (2237) 0x46c320 CMP	X27, X22

      (2237) 0x46c324 B.EQ	46c300

      (2237) 0x46c328 LDR	X28, [X24, X27,LSL #3]

      (2237) 0x46c32c CMP	X28, X17

      (2237) 0x46c330 B.GE	46c300

      (2237) 0x46c334 LDUR	X23, [X29, #480]

      (2237) 0x46c338 STR	X23, [X24, X27,LSL #3]

      (2237) 0x46c33c STR	X27, [X26, X23,LSL #3]

      (2237) 0x46c340 LDUR	X23, [X29, #480]

      (2237) 0x46c344 ADD	X23, X23, #1

      (2237) 0x46c348 STUR	X23, [X29, #480]

      (2237) 0x46c34c LDR	X23, [X9, X7,LSL #3]

      (2237) 0x46c350 B	46c300

0x46c354 HINT	#0

0x46c358 HINT	#0

0x46c35c HINT	#0

    (2235) 0x46c360 LDR	X19, [X12, X19,LSL #3]

    (2235) 0x46c364 LDR	X21, [X12, X7,LSL #3]

    (2235) 0x46c368 CMP	X19, X21

    (2235) 0x46c36c B.GE	46c288

    (2235) 0x46c370 LDUR	X20, [X29, #464]

    (2235) 0x46c374 LDR	X23, [X30]

    (2235) 0x46c378 LDR	X20, [X20]

    (2235) 0x46c37c B	46c38c

      (2236) 0x46c380 ADD	X19, X19, #1

      (2236) 0x46c384 CMP	X19, X21

      (2236) 0x46c388 B.GE	46c288

      (2236) 0x46c38c LDR	X26, [X5, X19,LSL #3]

      (2236) 0x46c390 LDR	X27, [X6, X26,LSL #3]

      (2236) 0x46c394 CMP	X27, #1

      (2236) 0x46c398 B.LT	46c380

      (2236) 0x46c39c LDR	X26, [X20, X26,LSL #3]

      (2236) 0x46c3a0 LDR	X27, [X25, X26,LSL #3]

      (2236) 0x46c3a4 CMP	X27, X18

      (2236) 0x46c3a8 B.GE	46c380

      (2236) 0x46c3ac LDUR	X21, [X29, #472]

      (2236) 0x46c3b0 STR	X21, [X25, X26,LSL #3]

      (2236) 0x46c3b4 STR	X26, [X23, X21,LSL #3]

      (2236) 0x46c3b8 LDUR	X21, [X29, #472]

      (2236) 0x46c3bc ADD	X21, X21, #1

      (2236) 0x46c3c0 STUR	X21, [X29, #472]

      (2236) 0x46c3c4 LDR	X21, [X12, X7,LSL #3]

      (2236) 0x46c3c8 B	46c380

  (2231) 0x46c3cc LDR	X1, [X12, X1,LSL #3]

  (2231) 0x46c3d0 LDR	X2, [X12, X0,LSL #3]

  (2231) 0x46c3d4 CMP	X1, X2

  (2231) 0x46c3d8 B.GE	46c240

(2232) 0x46c3dc LDUR	X2, [X29, #464]

(2232) 0x46c3e0 LDP	X4, X5, [X29, #888]

(2232) 0x46c3e4 LDR	X3, [X30]

(2232) 0x46c3e8 LDR	X2, [X2]

(2232) 0x46c3ec LDR	X4, [X4]

(2232) 0x46c3f0 LDR	X5, [X5]

(2232) 0x46c3f4 B	46c410

0x46c3f8 HINT	#0

0x46c3fc HINT	#0

(2232) 0x46c400 LDR	X6, [X12, X0,LSL #3]

(2232) 0x46c404 ADD	X1, X1, #1

(2232) 0x46c408 CMP	X1, X6

(2232) 0x46c40c B.GE	46c240

(2232) 0x46c410 LDR	X7, [X13, X1,LSL #3]

(2232) 0x46c414 LDR	X6, [X14, X7,LSL #3]

(2232) 0x46c418 CMP	X6, #1

(2232) 0x46c41c B.LT	46c448

(2232) 0x46c420 LDR	X6, [X2, X7,LSL #3]

(2232) 0x46c424 LDR	X19, [X25, X6,LSL #3]

(2232) 0x46c428 CMP	X19, X18

(2232) 0x46c42c B.GE	46c448

(2232) 0x46c430 LDUR	X19, [X29, #472]

(2232) 0x46c434 STR	X19, [X25, X6,LSL #3]

(2232) 0x46c438 STR	X6, [X3, X19,LSL #3]

(2232) 0x46c43c LDUR	X6, [X29, #472]

(2232) 0x46c440 ADD	X6, X6, #1

(2232) 0x46c444 STUR	X6, [X29, #472]

(2232) 0x46c448 ADD	X6, X7, #1

(2232) 0x46c44c LDR	X19, [X15, X7,LSL #3]

(2232) 0x46c450 LDR	X21, [X15, X6,LSL #3]

(2232) 0x46c454 CMP	X19, X21

(2232) 0x46c458 B.GE	46c4ac

(2232) 0x46c45c LDUR	X20, [X29, #448]

(2232) 0x46c460 LDR	X20, [X20]

(2232) 0x46c464 B	46c474

  (2234) 0x46c468 ADD	X19, X19, #1

  (2234) 0x46c46c CMP	X19, X21

  (2234) 0x46c470 B.GE	46c4ac

  (2234) 0x46c474 LDR	X23, [X4, X19,LSL #3]

  (2234) 0x46c478 CMP	X23, X22

  (2234) 0x46c47c B.EQ	46c468

  (2234) 0x46c480 LDR	X26, [X24, X23,LSL #3]

  (2234) 0x46c484 CMP	X26, X17

  (2234) 0x46c488 B.GE	46c468

  (2234) 0x46c48c LDUR	X21, [X29, #480]

  (2234) 0x46c490 STR	X21, [X24, X23,LSL #3]

  (2234) 0x46c494 STR	X23, [X20, X21,LSL #3]

  (2234) 0x46c498 LDUR	X21, [X29, #480]

  (2234) 0x46c49c ADD	X21, X21, #1

  (2234) 0x46c4a0 STUR	X21, [X29, #480]

  (2234) 0x46c4a4 LDR	X21, [X15, X6,LSL #3]

  (2234) 0x46c4a8 B	46c468

(2232) 0x46c4ac LDR	X7, [X16, X7,LSL #3]

(2232) 0x46c4b0 LDR	X20, [X16, X6,LSL #3]

(2232) 0x46c4b4 CMP	X7, X20

(2232) 0x46c4b8 B.GE	46c400

(2232) 0x46c4bc LDR	X19, [X30]

(2232) 0x46c4c0 B	46c4d0

  (2233) 0x46c4c4 ADD	X7, X7, #1

  (2233) 0x46c4c8 CMP	X7, X20

  (2233) 0x46c4cc B.GE	46c400

  (2233) 0x46c4d0 LDR	X21, [X5, X7,LSL #3]

  (2233) 0x46c4d4 LDR	X23, [X25, X21,LSL #3]

  (2233) 0x46c4d8 CMP	X23, X18

  (2233) 0x46c4dc B.GE	46c4c4

  (2233) 0x46c4e0 LDUR	X20, [X29, #472]

  (2233) 0x46c4e4 STR	X20, [X25, X21,LSL #3]

  (2233) 0x46c4e8 STR	X21, [X19, X20,LSL #3]

  (2233) 0x46c4ec LDUR	X20, [X29, #472]

  (2233) 0x46c4f0 ADD	X20, X20, #1

  (2233) 0x46c4f4 STUR	X20, [X29, #472]

  (2233) 0x46c4f8 LDR	X20, [X16, X6,LSL #3]

  (2233) 0x46c4fc B	46c4c4

0x46c500 LDR	X8, [SP, #96]

0x46c504 LDP	X12, X13, [X29, #984]

0x46c508 MOVZ	W4, #1

0x46c50c LDR	X8, [X8]

0x46c510 STR	X8, [SP, #144]

0x46c514 LDP	X10, X8, [SP, #40]

0x46c518 LDR	X9, [X10]

0x46c51c LDR	X10, [X8]

0x46c520 LDR	X8, [SP, #112]

0x46c524 LDR	X11, [X8]

0x46c528 LDR	X8, [SP, #56]

0x46c52c LDR	X14, [X8]

0x46c530 LDUR	X8, [X29, #408]

0x46c534 LDR	X8, [X8]

0x46c538 STUR	X8, [X29, #440]

0x46c53c LDUR	X8, [X29, #416]

0x46c540 LDR	X0, [X8]

0x46c544 LDR	X8, [SP, #64]

0x46c548 LDR	X2, [X8]

0x46c54c LDR	X8, [SP, #72]

0x46c550 LDR	X5, [X8]

0x46c554 B	46c570

0x46c558 HINT	#0

0x46c55c HINT	#0

    (2221) 0x46c560 LDUR	X8, [X29, #424]

    (2221) 0x46c564 ADD	X22, X22, #1

    (2221) 0x46c568 CMP	X22, X8

    (2221) 0x46c56c B.EQ	46cac0

    (2221) 0x46c570 LDR	X8, [SP, #144]

    (2221) 0x46c574 ORR	X6, XZR, X12

    (2221) 0x46c578 ORR	X7, XZR, X13

    (2221) 0x46c57c LDR	X8, [X8, X22,LSL #3]

    (2221) 0x46c580 ADD	X30, X8, #1

    (2221) 0x46c584 LDR	X17, [X9, X8,LSL #3]

    (2221) 0x46c588 STUR	X8, [X29, #400]

    (2221) 0x46c58c LDR	X8, [X9, X30,LSL #3]

    (2221) 0x46c590 CMP	X17, X8

    (2221) 0x46c594 B.GE	46c740

    (2221) 0x46c598 LDUR	X8, [X29, #456]

    (2221) 0x46c59c ORR	X13, XZR, X7

    (2221) 0x46c5a0 ORR	X12, XZR, X6

    (2221) 0x46c5a4 LDR	X18, [X8]

    (2221) 0x46c5a8 LDUR	X8, [X29, #408]

    (2221) 0x46c5ac LDR	X1, [X8]

    (2221) 0x46c5b0 LDUR	X8, [X29, #416]

    (2221) 0x46c5b4 LDR	X8, [X8]

    (2221) 0x46c5b8 B	46c5d0

0x46c5bc HINT	#0

      (2227) 0x46c5c0 LDR	X15, [X9, X30,LSL #3]

      (2227) 0x46c5c4 ADD	X17, X17, #1

      (2227) 0x46c5c8 CMP	X17, X15

      (2227) 0x46c5cc B.GE	46c740

      (2227) 0x46c5d0 LDR	X28, [X10, X17,LSL #3]

      (2227) 0x46c5d4 LDR	X15, [X11, X28,LSL #3]

      (2227) 0x46c5d8 CMP	X15, #1

      (2227) 0x46c5dc B.LT	46c608

      (2227) 0x46c5e0 LDR	X15, [X18, X28,LSL #3]

      (2227) 0x46c5e4 LDR	X16, [X24, X15,LSL #3]

      (2227) 0x46c5e8 SUBS	X16, X16, X7

      (2227) 0x46c5ec B.GE	46c620

      (2227) 0x46c5f0 SUB	X16, X13, X7

      (2227) 0x46c5f4 STR	X13, [X24, X15,LSL #3]

      (2227) 0x46c5f8 ADD	X13, X13, #1

      (2227) 0x46c5fc STR	X15, [X26, X16,LSL #3]

      (2227) 0x46c600 MOVZ	W15, #2

      (2227) 0x46c604 STR	X15, [X20, X16,LSL #3]

      (2227) 0x46c608 ADD	X3, X28, #1

      (2227) 0x46c60c LDR	X27, [X9, X28,LSL #3]

      (2227) 0x46c610 LDR	X15, [X9, X3,LSL #3]

      (2227) 0x46c614 CMP	X27, X15

      (2227) 0x46c618 B.LT	46c640

      (2227) 0x46c61c B	46c6c0

      (2227) 0x46c620 LDR	X15, [X20, X16,LSL #3]

      (2227) 0x46c624 ADD	X15, X15, #2

      (2227) 0x46c628 STR	X15, [X20, X16,LSL #3]

      (2227) 0x46c62c ADD	X3, X28, #1

      (2227) 0x46c630 LDR	X27, [X9, X28,LSL #3]

      (2227) 0x46c634 LDR	X15, [X9, X3,LSL #3]

      (2227) 0x46c638 CMP	X27, X15

      (2227) 0x46c63c B.GE	46c6c0

      (2227) 0x46c640 LDUR	X15, [X29, #456]

      (2227) 0x46c644 LDR	X15, [X15]

      (2227) 0x46c648 B	46c670

        (2229) 0x46c64c LDR	X16, [X20, X19,LSL #3]

        (2229) 0x46c650 ADD	X16, X16, #1

        (2229) 0x46c654 STR	X16, [X20, X19,LSL #3]

        (2229) 0x46c658 HINT	#0

        (2229) 0x46c65c HINT	#0

        (2229) 0x46c660 LDR	X16, [X9, X3,LSL #3]

        (2229) 0x46c664 ADD	X27, X27, #1

        (2229) 0x46c668 CMP	X27, X16

        (2229) 0x46c66c B.GE	46c6c0

        (2229) 0x46c670 LDR	X16, [X10, X27,LSL #3]

        (2229) 0x46c674 LDR	X19, [X11, X16,LSL #3]

        (2229) 0x46c678 CMP	X19, #1

        (2229) 0x46c67c B.LT	46c660

        (2229) 0x46c680 LDR	X16, [X15, X16,LSL #3]

        (2229) 0x46c684 CMP	X16, X22

        (2229) 0x46c688 B.EQ	46c660

        (2229) 0x46c68c LDR	X19, [X24, X16,LSL #3]

        (2229) 0x46c690 SUBS	X19, X19, X7

        (2229) 0x46c694 B.GE	46c64c

        (2229) 0x46c698 SUB	X19, X13, X7

        (2229) 0x46c69c STR	X13, [X24, X16,LSL #3]

        (2229) 0x46c6a0 ADD	X13, X13, #1

        (2229) 0x46c6a4 STR	X16, [X26, X19,LSL #3]

        (2229) 0x46c6a8 STR	X4, [X20, X19,LSL #3]

        (2229) 0x46c6ac B	46c660

0x46c6b0 HINT	#0

0x46c6b4 HINT	#0

0x46c6b8 HINT	#0

0x46c6bc HINT	#0

      (2227) 0x46c6c0 LDR	X27, [X14, X28,LSL #3]

      (2227) 0x46c6c4 LDR	X15, [X14, X3,LSL #3]

      (2227) 0x46c6c8 CMP	X27, X15

      (2227) 0x46c6cc B.GE	46c5c0

      (2227) 0x46c6d0 LDUR	X15, [X29, #464]

      (2227) 0x46c6d4 LDR	X15, [X15]

      (2227) 0x46c6d8 B	46c6fc

0x46c6dc HINT	#0

        (2228) 0x46c6e0 LDR	X16, [X21, X19,LSL #3]

        (2228) 0x46c6e4 ADD	X16, X16, #1

        (2228) 0x46c6e8 STR	X16, [X21, X19,LSL #3]

        (2228) 0x46c6ec LDR	X16, [X14, X3,LSL #3]

        (2228) 0x46c6f0 ADD	X27, X27, #1

        (2228) 0x46c6f4 CMP	X27, X16

        (2228) 0x46c6f8 B.GE	46c5c0

        (2228) 0x46c6fc LDR	X16, [X1, X27,LSL #3]

        (2228) 0x46c700 LDR	X19, [X8, X16,LSL #3]

        (2228) 0x46c704 CMP	X19, #1

        (2228) 0x46c708 B.LT	46c6ec

        (2228) 0x46c70c LDR	X16, [X15, X16,LSL #3]

        (2228) 0x46c710 LDR	X19, [X25, X16,LSL #3]

        (2228) 0x46c714 SUBS	X19, X19, X6

        (2228) 0x46c718 B.GE	46c6e0

        (2228) 0x46c71c SUB	X19, X12, X6

        (2228) 0x46c720 STR	X12, [X25, X16,LSL #3]

        (2228) 0x46c724 ADD	X12, X12, #1

        (2228) 0x46c728 STR	X16, [X23, X19,LSL #3]

        (2228) 0x46c72c STR	X4, [X21, X19,LSL #3]

        (2228) 0x46c730 B	46c6ec

0x46c734 HINT	#0

0x46c738 HINT	#0

0x46c73c HINT	#0

    (2221) 0x46c740 LDUR	X8, [X29, #400]

    (2221) 0x46c744 LDR	X15, [X14, X30,LSL #3]

    (2221) 0x46c748 LDR	X8, [X14, X8,LSL #3]

    (2221) 0x46c74c CMP	X8, X15

    (2221) 0x46c750 B.GE	46c8e0

    (2221) 0x46c754 LDUR	X16, [X29, #376]

    (2221) 0x46c758 LDUR	X15, [X29, #464]

    (2221) 0x46c75c LDR	X17, [X16]

    (2221) 0x46c760 LDUR	X16, [X29, #384]

    (2221) 0x46c764 LDR	X15, [X15]

    (2221) 0x46c768 LDR	X18, [X16]

    (2221) 0x46c76c B	46c790

0x46c770 HINT	#0

0x46c774 HINT	#0

0x46c778 HINT	#0

0x46c77c HINT	#0

      (2224) 0x46c780 LDR	X16, [X14, X30,LSL #3]

      (2224) 0x46c784 ADD	X8, X8, #1

      (2224) 0x46c788 CMP	X8, X16

      (2224) 0x46c78c B.GE	46c8e0

      (2224) 0x46c790 LDUR	X16, [X29, #440]

      (2224) 0x46c794 LDR	X3, [X16, X8,LSL #3]

      (2224) 0x46c798 LDR	X16, [X0, X3,LSL #3]

      (2224) 0x46c79c CMP	X16, #1

      (2224) 0x46c7a0 B.LT	46c7cc

      (2224) 0x46c7a4 LDR	X16, [X15, X3,LSL #3]

      (2224) 0x46c7a8 LDR	X1, [X25, X16,LSL #3]

      (2224) 0x46c7ac SUBS	X1, X1, X6

      (2224) 0x46c7b0 B.GE	46c7e4

      (2224) 0x46c7b4 SUB	X1, X12, X6

      (2224) 0x46c7b8 STR	X12, [X25, X16,LSL #3]

      (2224) 0x46c7bc ADD	X12, X12, #1

      (2224) 0x46c7c0 STR	X16, [X23, X1,LSL #3]

      (2224) 0x46c7c4 MOVZ	W16, #2

      (2224) 0x46c7c8 STR	X16, [X21, X1,LSL #3]

      (2224) 0x46c7cc LDR	X27, [X2, X3,LSL #3]

      (2224) 0x46c7d0 ADD	X1, X3, #1

      (2224) 0x46c7d4 LDR	X16, [X2, X1,LSL #3]

      (2224) 0x46c7d8 CMP	X27, X16

      (2224) 0x46c7dc B.LT	46c824

      (2224) 0x46c7e0 B	46c860

      (2224) 0x46c7e4 LDR	X16, [X21, X1,LSL #3]

      (2224) 0x46c7e8 ADD	X16, X16, #2

      (2224) 0x46c7ec STR	X16, [X21, X1,LSL #3]

      (2224) 0x46c7f0 LDR	X27, [X2, X3,LSL #3]

      (2224) 0x46c7f4 ADD	X1, X3, #1

      (2224) 0x46c7f8 LDR	X16, [X2, X1,LSL #3]

      (2224) 0x46c7fc CMP	X27, X16

      (2224) 0x46c800 B.LT	46c824

      (2224) 0x46c804 B	46c860

        (2226) 0x46c808 LDR	X16, [X20, X19,LSL #3]

        (2226) 0x46c80c ADD	X16, X16, #1

        (2226) 0x46c810 STR	X16, [X20, X19,LSL #3]

        (2226) 0x46c814 ADD	X27, X27, #1

        (2226) 0x46c818 LDR	X16, [X2, X1,LSL #3]

        (2226) 0x46c81c CMP	X27, X16

        (2226) 0x46c820 B.GE	46c860

        (2226) 0x46c824 LDR	X16, [X17, X27,LSL #3]

        (2226) 0x46c828 CMP	X16, X22

        (2226) 0x46c82c B.EQ	46c814

        (2226) 0x46c830 LDR	X19, [X24, X16,LSL #3]

        (2226) 0x46c834 SUBS	X19, X19, X7

        (2226) 0x46c838 B.GE	46c808

        (2226) 0x46c83c SUB	X19, X13, X7

        (2226) 0x46c840 STR	X13, [X24, X16,LSL #3]

        (2226) 0x46c844 ADD	X13, X13, #1

        (2226) 0x46c848 ADD	X27, X27, #1

        (2226) 0x46c84c STR	X16, [X26, X19,LSL #3]

        (2226) 0x46c850 STR	X4, [X20, X19,LSL #3]

        (2226) 0x46c854 LDR	X16, [X2, X1,LSL #3]

        (2226) 0x46c858 CMP	X27, X16

        (2226) 0x46c85c B.LT	46c824

      (2224) 0x46c860 LDR	X3, [X5, X3,LSL #3]

      (2224) 0x46c864 LDR	X16, [X5, X1,LSL #3]

      (2224) 0x46c868 CMP	X3, X16

      (2224) 0x46c86c B.LT	46c8a4

      (2224) 0x46c870 B	46c780

0x46c874 HINT	#0

0x46c878 HINT	#0

0x46c87c HINT	#0

        (2225) 0x46c880 SUB	X19, X12, X6

        (2225) 0x46c884 STR	X12, [X25, X16,LSL #3]

        (2225) 0x46c888 ADD	X12, X12, #1

        (2225) 0x46c88c ADD	X3, X3, #1

        (2225) 0x46c890 STR	X16, [X23, X19,LSL #3]

        (2225) 0x46c894 STR	X4, [X21, X19,LSL #3]

        (2225) 0x46c898 LDR	X16, [X5, X1,LSL #3]

        (2225) 0x46c89c CMP	X3, X16

        (2225) 0x46c8a0 B.GE	46c780

        (2225) 0x46c8a4 LDR	X16, [X18, X3,LSL #3]

        (2225) 0x46c8a8 LDR	X19, [X25, X16,LSL #3]

        (2225) 0x46c8ac SUBS	X19, X19, X6

        (2225) 0x46c8b0 B.LT	46c880

        (2225) 0x46c8b4 LDR	X16, [X21, X19,LSL #3]

        (2225) 0x46c8b8 ADD	X3, X3, #1

        (2225) 0x46c8bc ADD	X16, X16, #1

        (2225) 0x46c8c0 STR	X16, [X21, X19,LSL #3]

        (2225) 0x46c8c4 LDR	X16, [X5, X1,LSL #3]

        (2225) 0x46c8c8 CMP	X3, X16

        (2225) 0x46c8cc B.LT	46c8a4

      (2224) 0x46c8d0 B	46c780

0x46c8d4 HINT	#0

0x46c8d8 HINT	#0

0x46c8dc HINT	#0

    (2221) 0x46c8e0 LDUR	X19, [X29, #432]

    (2221) 0x46c8e4 LDUR	X27, [X29, #392]

    (2221) 0x46c8e8 CMP	X13, X7

    (2221) 0x46c8ec B.LE	46c93c

    (2221) 0x46c8f0 LDUR	X8, [X29, #448]

    (2221) 0x46c8f4 SUB	W15, W13, W7

    (2221) 0x46c8f8 ORR	X17, XZR, X7

    (2221) 0x46c8fc LDR	X8, [X8]

    (2221) 0x46c900 TBZ	W15, #0, 46c930

    (2221) 0x46c904 LDR	X15, [X20]

    (2221) 0x46c908 LDR	X16, [X19]

    (2221) 0x46c90c CMP	X15, X16

    (2221) 0x46c910 B.LT	46c928

    (2221) 0x46c914 LDUR	X16, [X29, #480]

    (2221) 0x46c918 LDR	X15, [X26]

    (2221) 0x46c91c ADD	X17, X16, #1

    (2221) 0x46c920 STUR	X17, [X29, #480]

    (2221) 0x46c924 STR	X15, [X8, X16,LSL #3]

    (2221) 0x46c928 ADD	X17, X7, #1

    (2221) 0x46c92c STR	XZR, [X20]

    (2221) 0x46c930 ADD	X15, X7, #1

    (2221) 0x46c934 CMP	X13, X15

    (2221) 0x46c938 B.NE	46ca24

    (2221) 0x46c93c CMP	X12, X6

    (2221) 0x46c940 B.LE	46c560

    (2221) 0x46c944 LDR	X8, [X27]

    (2221) 0x46c948 SUB	W15, W12, W6

    (2221) 0x46c94c ORR	X17, XZR, X6

    (2221) 0x46c950 TBZ	W15, #0, 46c980

    (2221) 0x46c954 LDR	X15, [X21]

    (2221) 0x46c958 LDR	X16, [X19]

    (2221) 0x46c95c CMP	X15, X16

    (2221) 0x46c960 B.LT	46c978

    (2221) 0x46c964 LDUR	X16, [X29, #472]

    (2221) 0x46c968 LDR	X15, [X23]

    (2221) 0x46c96c ADD	X17, X16, #1

    (2221) 0x46c970 STUR	X17, [X29, #472]

    (2221) 0x46c974 STR	X15, [X8, X16,LSL #3]

    (2221) 0x46c978 ADD	X17, X6, #1

    (2221) 0x46c97c STR	XZR, [X21]

    (2221) 0x46c980 ADD	X15, X6, #1

    (2221) 0x46c984 CMP	X12, X15

    (2221) 0x46c988 B.EQ	46c560

    (2221) 0x46c98c UBFM	X16, X17, #61, #60

    (2221) 0x46c990 SUB	X15, X12, X17

    (2221) 0x46c994 ADD	X17, X23, #8

    (2221) 0x46c998 ADD	X18, X21, #8

    (2221) 0x46c99c SUB	X16, X16, X6,LSL #3

    (2221) 0x46c9a0 ADD	X17, X17, X16

    (2221) 0x46c9a4 ADD	X18, X18, X16

    (2221) 0x46c9a8 B	46c9bc

      (2230) 0x46c9ac STR	XZR, [X18], #16

      (2230) 0x46c9b0 SUBS	X15, X15, #2

      (2230) 0x46c9b4 ADD	X17, X17, #16

      (2230) 0x46c9b8 B.EQ	46c560

      (2230) 0x46c9bc LDUR	X16, [X18, #504]

      (2230) 0x46c9c0 LDR	X1, [X19]

      (2230) 0x46c9c4 CMP	X16, X1

      (2230) 0x46c9c8 B.GE	46c9e4

      (2230) 0x46c9cc STUR	XZR, [X18, #504]

      (2230) 0x46c9d0 LDR	X16, [X18]

      (2230) 0x46c9d4 LDR	X1, [X19]

      (2230) 0x46c9d8 CMP	X16, X1

      (2230) 0x46c9dc B.LT	46c9ac

      (2230) 0x46c9e0 B	46ca0c

      (2230) 0x46c9e4 LDUR	X1, [X29, #472]

      (2230) 0x46c9e8 LDUR	X16, [X17, #504]

      (2230) 0x46c9ec ADD	X3, X1, #1

      (2230) 0x46c9f0 STUR	X3, [X29, #472]

      (2230) 0x46c9f4 STR	X16, [X8, X1,LSL #3]

      (2230) 0x46c9f8 STUR	XZR, [X18, #504]

      (2230) 0x46c9fc LDR	X16, [X18]

      (2230) 0x46ca00 LDR	X1, [X19]

      (2230) 0x46ca04 CMP	X16, X1

      (2230) 0x46ca08 B.LT	46c9ac

      (2230) 0x46ca0c LDUR	X1, [X29, #472]

      (2230) 0x46ca10 LDR	X16, [X17]

      (2230) 0x46ca14 ADD	X3, X1, #1

      (2230) 0x46ca18 STUR	X3, [X29, #472]

      (2230) 0x46ca1c STR	X16, [X8, X1,LSL #3]

      (2230) 0x46ca20 B	46c9ac

  (2223) 0x46ca24 UBFM	X16, X17, #61, #60

  (2223) 0x46ca28 SUB	X15, X13, X17

  (2223) 0x46ca2c ADD	X17, X26, #8

  (2223) 0x46ca30 ADD	X18, X20, #8

  (2223) 0x46ca34 SUB	X16, X16, X7,LSL #3

  (2223) 0x46ca38 ADD	X17, X17, X16

  (2223) 0x46ca3c ADD	X18, X18, X16

  (2223) 0x46ca40 B	46ca54

  (2223) 0x46ca44 STR	XZR, [X18], #16

  (2223) 0x46ca48 SUBS	X15, X15, #2

  (2223) 0x46ca4c ADD	X17, X17, #16

  (2223) 0x46ca50 B.EQ	46c93c

  (2223) 0x46ca54 LDUR	X16, [X18, #504]

  (2223) 0x46ca58 LDR	X1, [X19]

  (2223) 0x46ca5c CMP	X16, X1

  (2223) 0x46ca60 B.GE	46ca80

  (2223) 0x46ca64 STUR	XZR, [X18, #504]

  (2223) 0x46ca68 LDR	X16, [X18]

  (2223) 0x46ca6c LDR	X1, [X19]

  (2223) 0x46ca70 CMP	X16, X1

  (2223) 0x46ca74 B.LT	46ca44

  (2223) 0x46ca78 B	46caa8

0x46ca7c HINT	#0

(2222) 0x46ca80 LDUR	X1, [X29, #480]

(2222) 0x46ca84 LDUR	X16, [X17, #504]

(2222) 0x46ca88 ADD	X3, X1, #1

(2222) 0x46ca8c STUR	X3, [X29, #480]

(2222) 0x46ca90 STR	X16, [X8, X1,LSL #3]

(2222) 0x46ca94 STUR	XZR, [X18, #504]

(2222) 0x46ca98 LDR	X16, [X18]

(2222) 0x46ca9c LDR	X1, [X19]

(2222) 0x46caa0 CMP	X16, X1

(2222) 0x46caa4 B.LT	46ca44

  (2223) 0x46caa8 LDUR	X1, [X29, #480]

  (2223) 0x46caac LDR	X16, [X17]

  (2223) 0x46cab0 ADD	X3, X1, #1

  (2223) 0x46cab4 STUR	X3, [X29, #480]

  (2223) 0x46cab8 STR	X16, [X8, X1,LSL #3]

  (2223) 0x46cabc B	46ca44

0x46cac0 LDP	X20, X19, [SP, #368]

0x46cac4 LDP	X22, X21, [SP, #352]

0x46cac8 LDP	X24, X23, [SP, #336]

0x46cacc LDP	X26, X25, [SP, #320]

0x46cad0 LDP	X28, X27, [SP, #304]

0x46cad4 LDP	X29, X30, [SP, #288]

0x46cad8 ADD	SP, SP, #384

0x46cadc RET

Coverage (%)	Name	Source Location	Module
►98.54+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.46+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGCreate2ndS	par_strength.c:2238	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:617	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	par_strength.c:1668-2230
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1668-1697,1705-1714,1720-1797,1806,1812-2000,2006-2083,2093-2095,2101-2230.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 66.17 to 11.37 cycles (5.82x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1674
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1671
hypre_MAlloc: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1967
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1971
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1946
unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1961
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1962
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1973
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1975

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	385
nb uops	322
loop length	1540
used w registers	7
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	40.25 cycles
front end	40.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	16.50	16.50	25.00	25.00	25.00	25.00	0.00	0.00	0.00	0.00	66.17	65.83	66.00	20.50	20.50
cycles	16.50	16.50	25.00	25.00	25.00	25.00	0.00	0.00	0.00	0.00	66.17	65.83	66.00	20.50	20.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	40.25
Dispatch	66.17
Overall L1	66.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	25%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 66.17 cycles. At this rate:

0% of peak load performance is reached (0.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 46b550

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X27, X22, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X21, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4ae1b0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X0, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ae1d0 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X15, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X11, X10, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X21, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 46b5f4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X26, X12, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X12, X9, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X23, X14, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X13, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X8, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 46b608 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X12, X9, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X13, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X13, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X24, XZR, X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X25, XZR, X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 46b660 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46b664 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X15, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X9, X11, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X11, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 46b6f4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X22, [X8, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X13, X12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STP X9, X19, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.NE 46ba20 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46bf90 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xa40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46b79c <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
CMP X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46bf90 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xa40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X1, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X5, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X2, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 46ba94 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X10, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X9, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aedd0 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 46bff4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xaa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X8, X9, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 46c034 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xae4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4fe038>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #864	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410070 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4fe04c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #888	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4105a0 <@plt_start@+0x580>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 46c0c0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X9, 46c090 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ac440 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 46c0b0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ac440 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X0, <4fe0b0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #888	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104d0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4fe0c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #912	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410070 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X17, X18, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X30, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR X8, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.GE 46c178 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xc28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X12, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X9, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 46c148 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xbf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X22, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46cac0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x1570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X10, X12,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46c1f4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46c1f4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X10, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46c500 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xfb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X15, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X13, X14, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46c250 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xd00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 46c570 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	par_strength.c:1668-2230
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1674
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1671
hypre_MAlloc: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1967
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1971
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1946
unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1961
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1962
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1973
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1975

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	385
nb uops	322
loop length	1540
used w registers	7
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	40.25 cycles
front end	40.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	16.50	16.50	25.00	25.00	25.00	25.00	0.00	0.00	0.00	0.00	66.17	65.83	66.00	20.50	20.50
cycles	16.50	16.50	25.00	25.00	25.00	25.00	0.00	0.00	0.00	0.00	66.17	65.83	66.00	20.50	20.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	40.25
Dispatch	66.17
Overall L1	66.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	25%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 66.17 cycles. At this rate:

0% of peak load performance is reached (0.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 46b550

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X27, X22, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X21, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4ae1b0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X0, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ae1d0 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X15, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X11, X10, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X21, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 46b5f4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X26, X12, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X12, X9, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X23, X14, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X13, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X8, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 46b608 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X12, X9, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X13, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X13, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X24, XZR, X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X25, XZR, X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 46b660 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46b664 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X15, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X9, X11, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X11, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 46b6f4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X22, [X8, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X13, X12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STP X9, X19, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.NE 46ba20 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46bf90 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xa40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46b79c <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
CMP X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46bf90 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xa40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X1, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X5, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X2, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 46ba94 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X10, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X9, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aedd0 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 46bff4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xaa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X8, X9, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 46c034 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xae4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4fe038>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #864	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410070 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4fe04c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #888	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4105a0 <@plt_start@+0x580>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 46c0c0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X9, 46c090 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ac440 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 46c0b0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ac440 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X0, <4fe0b0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #888	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104d0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4fe0c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #912	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410070 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X17, X18, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X30, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR X8, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.GE 46c178 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xc28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X12, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X9, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 46c148 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xbf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X22, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46cac0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x1570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X10, X12,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46c1f4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46c1f4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X10, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46c500 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xfb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X15, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X13, X14, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46c250 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xd00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 46c570 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreate2ndS.omp_outlined.15–	1.38	0.66
○Loop 2240 - par_strength.c:1951-1953 - exec	0.03	0.01
○Loop 2259 - par_strength.c:1691-1693 - exec	0.01	0.01
○Loop 2258 - par_strength.c:1695-1697 - exec	0.00	0.00
○Loop 2238 - par_strength.c:1978-1984 - exec	0.00	0.00
▼Loop 2222 - par_strength.c:2093-2230 - exec–	0.00	0.00
▼Loop 2223 - par_strength.c:2093-2230 - exec–	0.00	0.00
▼Loop 2221 - par_strength.c:2093-2230 - exec–	0.00	0.00
▼Loop 2227 - par_strength.c:2106-2158 - exec–	0.00	0.00
○Loop 2229 - par_strength.c:2124-2139 - exec	0.00	0.00
○Loop 2228 - par_strength.c:2143-2158 - exec	0.00	0.00
▼Loop 2224 - par_strength.c:2163-2211 - exec–	0.00	0.00
○Loop 2225 - par_strength.c:2199-2211 - exec	0.00	0.00
○Loop 2226 - par_strength.c:2181-2195 - exec	0.00	0.00
○Loop 2230 - par_strength.c:2224-2230 - exec	0.00	0.00
○Loop 2239 - par_strength.c:1955-1957 - exec	0.00	0.00
▼Loop 2242 - par_strength.c:1806-1941 - exec–	0.00	0.00
▼Loop 2243 - par_strength.c:1806-1941 - exec–	0.00	0.00
▼Loop 2241 - par_strength.c:1806-1941 - exec–	0.00	0.00
○Loop 2250 - par_strength.c:1935-1941 - exec	0.00	0.00
▼Loop 2247 - par_strength.c:1823-1872 - exec–	0.00	0.00
○Loop 2249 - par_strength.c:1840-1854 - exec	0.00	0.00
○Loop 2248 - par_strength.c:1858-1872 - exec	0.00	0.00
▼Loop 2244 - par_strength.c:1877-1922 - exec–	0.00	0.00
○Loop 2245 - par_strength.c:1911-1922 - exec	0.00	0.00
○Loop 2246 - par_strength.c:1894-1907 - exec	0.00	0.00
▼Loop 2252 - par_strength.c:1714-1797 - exec–	0.00	0.00
▼Loop 2251 - par_strength.c:1714-1770 - exec–	0.00	0.01
▼Loop 2254 - par_strength.c:1731-1765 - exec–	0.08	0.03
○Loop 2256 - par_strength.c:1743-1752 - exec	0.58	0.20
○Loop 2255 - par_strength.c:1756-1765 - exec	0.00	0.00
○Loop 2253 - par_strength.c:1782-1788 - exec	0.00	0.00
○Loop 2257 - par_strength.c:1791-1797 - exec	0.00	0.00
▼Loop 2232 - par_strength.c:1998-2083 - exec–	0.00	0.00
▼Loop 2231 - par_strength.c:1998-2053 - exec–	0.00	0.01
▼Loop 2235 - par_strength.c:2011-2048 - exec–	0.09	0.03
○Loop 2237 - par_strength.c:2024-2034 - exec	0.58	0.20
○Loop 2236 - par_strength.c:2038-2048 - exec	0.00	0.00
○Loop 2234 - par_strength.c:2066-2073 - exec	0.00	0.00
○Loop 2233 - par_strength.c:2076-2083 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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Cycles and memory resources usage

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ASM code

Vectorization

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CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code