OV - exec - Function hypre_ParCSRRelaxThreads.omp

	Function: hypre_ParCSRRelaxThreads.omp_outlined.27	Module: exec	Source: ams.c:3662-3682	Coverage (incl. loops): 32.33% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

3663: #endif

3664:       for (i = 0; i < n; i++)

3665:       {

3666:          /*-----------------------------------------------------------

3667:           * If diagonal is nonzero, relax point i; otherwise, skip it.

3668:           *-----------------------------------------------------------*/

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

0x47d440 SUB	SP, SP, #144

0x47d444 STP	X29, X30, [SP, #48]

0x47d448 STP	X28, X27, [SP, #64]

0x47d44c STP	X26, X25, [SP, #80]

0x47d450 STP	X24, X23, [SP, #96]

0x47d454 STP	X22, X21, [SP, #112]

0x47d458 STP	X20, X19, [SP, #128]

0x47d45c ADD	X29, SP, #48

0x47d460 LDR	X8, [X2]

0x47d464 SUBS	X25, X8, #1

0x47d468 B.LT	47d4e8

0x47d46c LDR	W20, [X0]

0x47d470 ORR	X21, XZR, X7

0x47d474 ORR	X22, XZR, X6

0x47d478 ORR	X19, XZR, X5

0x47d47c ORR	X23, XZR, X4

0x47d480 ORR	X24, XZR, X3

0x47d484 MOVZ	W8, #1

0x47d488 ADRP	X0,

0x47d48c ADD	X0, X0, #1200

0x47d490 ADD	X3, SP, #20

0x47d494 SUB	X4, X29, #8

0x47d498 SUB	X5, X29, #16

0x47d49c ADD	X6, SP, #24

0x47d4a0 MOVZ	W2, #34

0x47d4a4 STP	X25, XZR, [X29, #1008]

0x47d4a8 MOVZ	W7, #1

0x47d4ac STR	X8, [SP, #24]

0x47d4b0 STR	WZR, [SP, #20]

0x47d4b4 STR	X8, [SP]

0x47d4b8 ORR	W1, WZR, W20

0x47d4bc BL	410630

0x47d4c0 LDP	X8, X9, [X29, #1008]

0x47d4c4 CMP	X8, X25

0x47d4c8 CSEL	X1, X8, X25, #11

0x47d4cc CMP	X9, X1

0x47d4d0 STUR	X1, [X29, #496]

0x47d4d4 B.LE	47d508

0x47d4d8 ADRP	X0,

0x47d4dc ADD	X0, X0, #1224

0x47d4e0 ORR	W1, WZR, W20

0x47d4e4 BL	410540

0x47d4e8 LDP	X20, X19, [SP, #128]

0x47d4ec LDP	X22, X21, [SP, #112]

0x47d4f0 LDP	X24, X23, [SP, #96]

0x47d4f4 LDP	X26, X25, [SP, #80]

0x47d4f8 LDP	X28, X27, [SP, #64]

0x47d4fc LDP	X29, X30, [SP, #48]

0x47d500 ADD	SP, SP, #144

0x47d504 RET

0x47d508 LDP	X16, X17, [X29, #112]

0x47d50c LDP	X8, X0, [X29, #144]

0x47d510 ADD	X1, X1, #1

0x47d514 LDR	X10, [X24]

0x47d518 ADD	X2, X10, #8

0x47d51c LDR	X13, [X21]

0x47d520 LDP	X18, X4, [X29, #128]

0x47d524 LDP	X14, X15, [X29, #96]

0x47d528 LDR	X16, [X16]

0x47d52c LDR	X17, [X17]

0x47d530 LDR	X11, [X23]

0x47d534 LDR	X12, [X22]

0x47d538 LDR	X14, [X14]

0x47d53c ADD	X3, X13, #8

0x47d540 ADD	X7, X17, #8

0x47d544 LDR	X15, [X15]

0x47d548 LDR	X18, [X18]

0x47d54c LDR	X0, [X0]

0x47d550 LDR	X6, [X4]

0x47d554 ADD	X21, X16, #8

0x47d558 B	47d588

0x47d55c HINT	#0

(2740) 0x47d560 LDR	D1, [X8]

(2740) 0x47d564 FMUL	D0, D1, D0

(2740) 0x47d568 LDR	D1, [X0, X9,LSL #3]

(2740) 0x47d56c FDIV	D0, D0, D1

(2740) 0x47d570 LDR	D1, [X6, X9,LSL #3]

(2740) 0x47d574 FADD	D0, D1, D0

(2740) 0x47d578 STR	D0, [X6, X9,LSL #3]

(2740) 0x47d57c CMP	X24, X1

(2740) 0x47d580 ORR	X9, XZR, X24

(2740) 0x47d584 B.EQ	47d4d8

  (2739) 0x47d588 LDR	X4, [X11, X9,LSL #3]

  (2739) 0x47d58c LDR	D1, [X19]

  (2739) 0x47d590 LDR	D0, [X10, X4,LSL #3]

  (2739) 0x47d594 FCMP	D0, D1

  (2739) 0x47d598 B.EQ	47d5c0

(2740) 0x47d59c LDR	D0, [X12, X9,LSL #3]

(2740) 0x47d5a0 ADD	X24, X9, #1

(2740) 0x47d5a4 LDR	X25, [X11, X24,LSL #3]

(2740) 0x47d5a8 SUBS	X27, X25, X4

(2740) 0x47d5ac B.LE	47d6c0

(2740) 0x47d5b0 CMP	X27, #2

(2740) 0x47d5b4 B.CS	47d5d4

(2740) 0x47d5b8 ORR	X26, XZR, X4

(2740) 0x47d5bc B	47d620

  (2739) 0x47d5c0 ADD	X24, X9, #1

  (2739) 0x47d5c4 CMP	X24, X1

  (2739) 0x47d5c8 ORR	X9, XZR, X24

  (2739) 0x47d5cc B.NE	47d588

0x47d5d0 B	47d4d8

(2740) 0x47d5d4 AND	X28, X27, #0xfffffffe

(2740) 0x47d5d8 MOVI	D1, #0

(2740) 0x47d5dc ADD	X30, X2, X4,LSL #3

(2740) 0x47d5e0 AND	X5, X27, #0xfffffffe

(2740) 0x47d5e4 ADD	X26, X4, X28

(2740) 0x47d5e8 ADD	X4, X3, X4,LSL #3

  (2744) 0x47d5ec LDP	X22, X23, [X4, #1016]

  (2744) 0x47d5f0 LDP	D2, D3, [X30, #1016]

  (2744) 0x47d5f4 SUBS	X5, X5, #2

  (2744) 0x47d5f8 ADD	X30, X30, #16

  (2744) 0x47d5fc ADD	X4, X4, #16

  (2744) 0x47d600 LDR	D4, [X14, X22,LSL #3]

  (2744) 0x47d604 LDR	D5, [X14, X23,LSL #3]

  (2744) 0x47d608 FMSUB	D0, D4, D2, D0

  (2744) 0x47d60c FMSUB	D1, D5, D3, D1

  (2744) 0x47d610 B.NE	47d5ec

(2740) 0x47d614 FADD	D0, D1, D0

(2740) 0x47d618 CMP	X27, X28

(2740) 0x47d61c B.EQ	47d6c0

(2740) 0x47d620 SUB	W4, W25, W26

(2740) 0x47d624 ORR	X27, XZR, X26

(2740) 0x47d628 ANDS	X4, X4, #0x3

(2740) 0x47d62c B.EQ	47d65c

(2740) 0x47d630 HINT	#0

(2740) 0x47d634 HINT	#0

(2740) 0x47d638 HINT	#0

(2740) 0x47d63c HINT	#0

  (2746) 0x47d640 LDR	X5, [X13, X27,LSL #3]

  (2746) 0x47d644 LDR	D1, [X10, X27,LSL #3]

  (2746) 0x47d648 ADD	X27, X27, #1

  (2746) 0x47d64c SUBS	X4, X4, #1

  (2746) 0x47d650 LDR	D2, [X14, X5,LSL #3]

  (2746) 0x47d654 FMSUB	D0, D2, D1, D0

  (2746) 0x47d658 B.NE	47d640

(2740) 0x47d65c SUB	X4, X26, X25

(2740) 0x47d660 CMN	X4, #4

(2740) 0x47d664 B.HI	47d6c0

(2740) 0x47d668 ADD	X4, X10, #16

(2740) 0x47d66c SUB	X25, X25, X27

(2740) 0x47d670 ADD	X26, X4, X27,LSL #3

(2740) 0x47d674 ADD	X4, X13, #16

(2740) 0x47d678 ADD	X27, X4, X27,LSL #3

(2740) 0x47d67c HINT	#0

  (2745) 0x47d680 LDP	X4, X5, [X27, #1008]

  (2745) 0x47d684 LDP	D2, D3, [X26, #1008]

  (2745) 0x47d688 SUBS	X25, X25, #4

  (2745) 0x47d68c LDR	D4, [X14, X5,LSL #3]

  (2745) 0x47d690 LDR	D1, [X14, X4,LSL #3]

  (2745) 0x47d694 FMUL	D3, D4, D3

  (2745) 0x47d698 FMADD	D1, D1, D2, D3

  (2745) 0x47d69c LDP	X4, X5, [X27], #32

  (2745) 0x47d6a0 LDR	D4, [X14, X4,LSL #3]

  (2745) 0x47d6a4 LDP	D2, D3, [X26], #32

  (2745) 0x47d6a8 FMADD	D1, D4, D2, D1

  (2745) 0x47d6ac LDR	D2, [X14, X5,LSL #3]

  (2745) 0x47d6b0 FMADD	D1, D2, D3, D1

  (2745) 0x47d6b4 FSUB	D0, D0, S1

  (2745) 0x47d6b8 B.NE	47d680

(2740) 0x47d6bc HINT	#0

(2740) 0x47d6c0 LDR	X4, [X15, X9,LSL #3]

(2740) 0x47d6c4 LDR	X25, [X15, X24,LSL #3]

(2740) 0x47d6c8 SUBS	X27, X25, X4

(2740) 0x47d6cc B.LE	47d560

(2740) 0x47d6d0 CMP	X27, #2

(2740) 0x47d6d4 B.CS	47d6e0

(2740) 0x47d6d8 ORR	X26, XZR, X4

(2740) 0x47d6dc B	47d734

(2740) 0x47d6e0 AND	X28, X27, #0xfffffffe

(2740) 0x47d6e4 MOVI	D1, #0

(2740) 0x47d6e8 ADD	X30, X7, X4,LSL #3

(2740) 0x47d6ec AND	X5, X27, #0xfffffffe

(2740) 0x47d6f0 ADD	X26, X4, X28

(2740) 0x47d6f4 ADD	X4, X21, X4,LSL #3

(2740) 0x47d6f8 HINT	#0

(2740) 0x47d6fc HINT	#0

  (2741) 0x47d700 LDP	X22, X23, [X4, #1016]

  (2741) 0x47d704 LDP	D2, D3, [X30, #1016]

  (2741) 0x47d708 SUBS	X5, X5, #2

  (2741) 0x47d70c ADD	X30, X30, #16

  (2741) 0x47d710 ADD	X4, X4, #16

  (2741) 0x47d714 LDR	D4, [X18, X22,LSL #3]

  (2741) 0x47d718 LDR	D5, [X18, X23,LSL #3]

  (2741) 0x47d71c FMSUB	D0, D4, D2, D0

  (2741) 0x47d720 FMSUB	D1, D5, D3, D1

  (2741) 0x47d724 B.NE	47d700

(2740) 0x47d728 FADD	D0, D1, D0

(2740) 0x47d72c CMP	X27, X28

(2740) 0x47d730 B.EQ	47d560

(2740) 0x47d734 SUB	W4, W25, W26

(2740) 0x47d738 ORR	X27, XZR, X26

(2740) 0x47d73c ANDS	X4, X4, #0x3

(2740) 0x47d740 B.EQ	47d760

  (2743) 0x47d744 LDR	X5, [X16, X27,LSL #3]

  (2743) 0x47d748 LDR	D1, [X17, X27,LSL #3]

  (2743) 0x47d74c ADD	X27, X27, #1

  (2743) 0x47d750 SUBS	X4, X4, #1

  (2743) 0x47d754 LDR	D2, [X18, X5,LSL #3]

  (2743) 0x47d758 FMSUB	D0, D2, D1, D0

  (2743) 0x47d75c B.NE	47d744

(2740) 0x47d760 SUB	X4, X26, X25

(2740) 0x47d764 CMN	X4, #4

(2740) 0x47d768 B.HI	47d560

(2740) 0x47d76c ADD	X4, X17, #16

(2740) 0x47d770 SUB	X25, X25, X27

(2740) 0x47d774 ADD	X26, X4, X27,LSL #3

(2740) 0x47d778 ADD	X4, X16, #16

(2740) 0x47d77c ADD	X27, X4, X27,LSL #3

  (2742) 0x47d780 LDP	X4, X5, [X27, #1008]

  (2742) 0x47d784 LDP	D2, D3, [X26, #1008]

  (2742) 0x47d788 SUBS	X25, X25, #4

  (2742) 0x47d78c LDR	D4, [X18, X5,LSL #3]

  (2742) 0x47d790 LDR	D1, [X18, X4,LSL #3]

  (2742) 0x47d794 FMUL	D3, D4, D3

  (2742) 0x47d798 FMADD	D1, D1, D2, D3

  (2742) 0x47d79c LDP	X4, X5, [X27], #32

  (2742) 0x47d7a0 LDR	D4, [X18, X4,LSL #3]

  (2742) 0x47d7a4 LDP	D2, D3, [X26], #32

  (2742) 0x47d7a8 FMADD	D1, D4, D2, D1

  (2742) 0x47d7ac LDR	D2, [X18, X5,LSL #3]

  (2742) 0x47d7b0 FMADD	D1, D2, D3, D1

  (2742) 0x47d7b4 FSUB	D0, D0, S1

  (2742) 0x47d7b8 B.NE	47d780

(2740) 0x47d7bc B	47d560

Coverage (%)	Name	Source Location	Module
►98.50+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.44+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_ParCSRRelaxThreads	ams.c:3685	exec
○	hypre_BoomerAMGCycle	par_cycle.c:334	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:274	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 30% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 11.83 to 3.23 cycles (3.66x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	73
nb uops	72
loop length	292
used w registers	6
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	11.83	11.50	11.67	5.50	5.50
cycles	3.50	3.50	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	11.83	11.50	11.67	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.00
Dispatch	11.83
Overall L1	11.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	32%
store	39%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.83 cycles. At this rate:

0% of peak load performance is reached (0.25 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.25 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 47d440

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUBS X25, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 47d4e8 <hypre_ParCSRRelaxThreads.omp_outlined.27+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X21, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X23, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <4fe488>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X25, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410630 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X1, X8, X25, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X1, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 47d508 <hypre_ParCSRRelaxThreads.omp_outlined.27+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4fe4d8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410540 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X16, X17, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X8, X0, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X2, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X4, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X14, X15, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X21, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 47d588 <hypre_ParCSRRelaxThreads.omp_outlined.27+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
B 47d4d8 <hypre_ParCSRRelaxThreads.omp_outlined.27+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	73
nb uops	72
loop length	292
used w registers	6
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	11.83	11.50	11.67	5.50	5.50
cycles	3.50	3.50	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	11.83	11.50	11.67	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.00
Dispatch	11.83
Overall L1	11.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	32%
store	39%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.83 cycles. At this rate:

0% of peak load performance is reached (0.25 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.25 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 47d440

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUBS X25, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 47d4e8 <hypre_ParCSRRelaxThreads.omp_outlined.27+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X21, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X23, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <4fe488>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X25, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410630 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X1, X8, X25, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X1, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 47d508 <hypre_ParCSRRelaxThreads.omp_outlined.27+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4fe4d8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410540 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X16, X17, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X8, X0, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X2, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X4, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X14, X15, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X21, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 47d588 <hypre_ParCSRRelaxThreads.omp_outlined.27+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
B 47d4d8 <hypre_ParCSRRelaxThreads.omp_outlined.27+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads.omp_outlined.27–	32.33	15.50
▼Loop 2740 - ams.c:3664-3682 - exec–	1.21	0.42
○Loop 2744 - ams.c:3672-3675 - exec	28.84	9.95
○Loop 2746 - ams.c:3672-3675 - exec	1.34	0.46
○Loop 2739 - ams.c:3664-3669 - exec	0.94	0.32
○Loop 2742 - ams.c:3677-3680 - exec	0.00	0.00
○Loop 2741 - ams.c:3677-3680 - exec	0.00	0.00
○Loop 2745 - ams.c:3672-3675 - exec	0.00	0.00
○Loop 2743 - ams.c:3677-3680 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code