OV - exec - Function hypre_ParMatmul.omp

	Function: hypre_ParMatmul.omp_outlined.6	Module: exec	Source: par_csr_matop.c:829-995 [...]	Coverage (incl. loops): 0.76% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 829 - 995

--------------------------------------------------------------------------------

829: #pragma omp parallel

[...]

840:     ii = hypre_GetThreadNum();

841:     num_threads = hypre_NumActiveThreads();

842:     size = num_rows_diag_A/num_threads;

843:     rest = num_rows_diag_A - size*num_threads;

844:     if (ii < rest)

845:     {

846:        ns = ii*size+ii;

847:        ne = (ii+1)*size+ii+1;

848:     }

849:     else

850:     {

851:        ns = ii*size+rest;

852:        ne = (ii+1)*size+rest;

853:     }

854:     jj_count_diag = C_diag_i[ns];

855:     jj_count_offd = C_offd_i[ns];

856:     if (num_cols_diag_B || num_cols_offd_C)

857:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

858:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

859:       B_marker[i1] = -1;

[...]

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

[...]

995:     hypre_TFree(B_marker);

0x488030 SUB	SP, SP, #320

0x488034 STP	X29, X30, [SP, #224]

0x488038 STP	X28, X27, [SP, #240]

0x48803c STP	X26, X25, [SP, #256]

0x488040 STP	X24, X23, [SP, #272]

0x488044 STP	X22, X21, [SP, #288]

0x488048 STP	X20, X19, [SP, #304]

0x48804c ADD	X29, SP, #224

0x488050 LDP	X8, X9, [X29, #288]

0x488054 STUR	X7, [X29, #424]

0x488058 ORR	X19, XZR, X6

0x48805c ORR	X20, XZR, X5

0x488060 ORR	X22, XZR, X3

0x488064 ORR	X26, XZR, X2

0x488068 STUR	X4, [X29, #480]

0x48806c STUR	X9, [X29, #456]

0x488070 STR	X8, [SP, #88]

0x488074 LDR	X8, [X29, #280]

0x488078 STR	X8, [SP, #80]

0x48807c LDR	X8, [X29, #272]

0x488080 STR	X8, [SP, #72]

0x488084 LDP	X8, X28, [X29, #256]

0x488088 STUR	X8, [X29, #464]

0x48808c LDR	X8, [X29, #248]

0x488090 STR	X8, [SP, #64]

0x488094 LDP	X27, X8, [X29, #232]

0x488098 STUR	X8, [X29, #472]

0x48809c LDP	X8, X24, [X29, #216]

0x4880a0 STR	X8, [SP, #40]

0x4880a4 LDP	X8, X9, [X29, #200]

0x4880a8 STUR	X9, [X29, #448]

0x4880ac STR	X8, [SP, #56]

0x4880b0 LDR	X8, [X29, #192]

0x4880b4 STR	X8, [SP, #32]

0x4880b8 LDP	X8, X9, [X29, #176]

0x4880bc STUR	X8, [X29, #440]

0x4880c0 LDP	X8, X10, [X29, #160]

0x4880c4 STP	X10, X9, [X29, #1000]

0x4880c8 STR	X8, [SP, #48]

0x4880cc LDR	X8, [X29, #152]

0x4880d0 STR	X8, [SP, #24]

0x4880d4 LDR	X8, [X29, #144]

0x4880d8 STR	X8, [SP, #16]

0x4880dc LDR	X8, [X29, #136]

0x4880e0 STR	X8, [SP, #8]

0x4880e4 LDR	X8, [X29, #128]

0x4880e8 STR	X8, [SP, #96]

0x4880ec LDP	X21, X9, [X29, #112]

0x4880f0 LDP	X25, X8, [X29, #96]

0x4880f4 STP	X8, X9, [X29, #920]

0x4880f8 BL	4ae1b0

0x4880fc ORR	X23, XZR, X0

0x488100 BL	4ae190

0x488104 LDR	X8, [X26]

0x488108 ADD	X10, X23, #1

0x48810c ORR	X13, XZR, X19

0x488110 SDIV	X9, X8, X0

0x488114 MSUB	X8, X9, X0, X8

0x488118 MADD	X11, X9, X23, X8

0x48811c MADD	X12, X9, X10, X8

0x488120 ADD	X9, X9, #1

0x488124 MUL	X10, X10, X9

0x488128 CMP	X23, X8

0x48812c CSEL	X8, X12, X10, #10

0x488130 MUL	X9, X9, X23

0x488134 CSEL	X26, X11, X9, #10

0x488138 LDR	X9, [X19]

0x48813c STUR	X8, [X29, #432]

0x488140 LDR	X8, [X22]

0x488144 LDR	X22, [X8, X26,LSL #3]

0x488148 LDUR	X8, [X29, #480]

0x48814c LDR	X8, [X8]

0x488150 LDR	X19, [X8, X26,LSL #3]

0x488154 LDR	X8, [X20]

0x488158 ORR	X10, X8, X9

0x48815c CBNZ	X10, 488178

0x488160 LDUR	X9, [X29, #472]

0x488164 ORR	X0, XZR, XZR

0x488168 LDUR	X8, [X29, #432]

0x48816c CMP	X26, X8

0x488170 B.LT	4881dc

0x488174 B	488590

0x488178 STUR	X24, [X29, #480]

0x48817c LDUR	X24, [X29, #472]

0x488180 ADD	X0, X9, X8

0x488184 MOVZ	W1, #8

0x488188 ORR	X23, XZR, X13

0x48818c BL	4ac4b0

0x488190 LDR	X8, [X20]

0x488194 LDR	X9, [X23]

0x488198 ADD	X8, X9, X8

0x48819c CMP	X8, #1

0x4881a0 B.LT	4881c8

0x4881a4 MOVN	X9, #0

0x4881a8 ORR	X8, XZR, XZR

(2949) 0x4881ac STR	X9, [X0, X8,LSL #3]

(2949) 0x4881b0 ADD	X8, X8, #1

(2949) 0x4881b4 LDR	X10, [X20]

(2949) 0x4881b8 LDR	X11, [X23]

(2949) 0x4881bc ADD	X10, X11, X10

(2949) 0x4881c0 CMP	X8, X10

(2949) 0x4881c4 B.LT	4881ac

0x4881c8 ORR	X9, XZR, X24

0x4881cc LDUR	X24, [X29, #480]

0x4881d0 LDUR	X8, [X29, #432]

0x4881d4 CMP	X26, X8

0x4881d8 B.GE	488590

0x4881dc LDR	X10, [X25]

0x4881e0 LDR	X8, [X21]

0x4881e4 LDR	X16, [X24]

0x4881e8 ORR	X1, XZR, X22

0x4881ec LDR	X17, [X27]

0x4881f0 LDR	X18, [X9]

0x4881f4 STP	X8, X10, [SP, #104]

0x4881f8 LDR	X8, [SP, #96]

0x4881fc LDR	X8, [X8]

0x488200 STR	X8, [SP, #96]

0x488204 LDR	X8, [SP, #8]

0x488208 LDR	X8, [X8]

0x48820c STUR	X8, [X29, #480]

0x488210 LDR	X8, [SP, #16]

0x488214 LDR	X8, [X8]

0x488218 STUR	X8, [X29, #472]

0x48821c LDP	X10, X8, [SP, #24]

0x488220 LDR	X14, [X8]

0x488224 LDR	X8, [SP, #40]

0x488228 LDR	X13, [X10]

0x48822c LDR	X15, [X8]

0x488230 B	488254

0x488234 HINT	#0

0x488238 HINT	#0

0x48823c HINT	#0

  (2942) 0x488240 LDUR	X8, [X29, #432]

  (2942) 0x488244 ORR	X19, XZR, X2

  (2942) 0x488248 ORR	X22, XZR, X1

  (2942) 0x48824c CMP	X26, X8

  (2942) 0x488250 B.GE	488590

  (2942) 0x488254 LDUR	X8, [X29, #424]

  (2942) 0x488258 LDR	X8, [X8]

  (2942) 0x48825c CBZ	X8, 48827c

  (2942) 0x488260 LDUR	X8, [X29, #408]

  (2942) 0x488264 ADD	X1, X22, #1

  (2942) 0x488268 STR	X22, [X0, X26,LSL #3]

  (2942) 0x48826c LDR	D0, [X8]

  (2942) 0x488270 LDP	X8, X9, [SP, #104]

  (2942) 0x488274 STR	X26, [X8, X22,LSL #3]

  (2942) 0x488278 STR	D0, [X9, X22,LSL #3]

  (2942) 0x48827c LDUR	X8, [X29, #416]

  (2942) 0x488280 LDR	X8, [X8]

  (2942) 0x488284 CBZ	X8, 488400

  (2942) 0x488288 LDR	X8, [SP, #96]

  (2942) 0x48828c ADD	X3, X8, X26,LSL #3

  (2942) 0x488290 LDP	X4, X8, [X3]

  (2942) 0x488294 CMP	X4, X8

  (2942) 0x488298 B.GE	488420

  (2942) 0x48829c LDP	X9, X8, [SP, #48]

  (2942) 0x4882a0 ORR	X2, XZR, X19

  (2942) 0x4882a4 LDR	X5, [X9]

  (2942) 0x4882a8 LDR	X6, [X8]

  (2942) 0x4882ac B	4882d0

0x4882b0 HINT	#0

0x4882b4 HINT	#0

0x4882b8 HINT	#0

0x4882bc HINT	#0

    (2946) 0x4882c0 LDR	X8, [X3, #8]

    (2946) 0x4882c4 ADD	X4, X4, #1

    (2946) 0x4882c8 CMP	X4, X8

    (2946) 0x4882cc B.GE	488404

    (2946) 0x4882d0 LDP	X8, X9, [X29, #984]

    (2946) 0x4882d4 LDR	X30, [X9, X4,LSL #3]

    (2946) 0x4882d8 LDR	D0, [X8, X4,LSL #3]

    (2946) 0x4882dc ADD	X7, X30, #1

    (2946) 0x4882e0 LDR	X8, [X13, X30,LSL #3]

    (2946) 0x4882e4 LDR	X23, [X13, X7,LSL #3]

    (2946) 0x4882e8 CMP	X8, X23

    (2946) 0x4882ec B.GE	48836c

    (2946) 0x4882f0 LDUR	X9, [X29, #440]

    (2946) 0x4882f4 LDP	X10, X11, [X29, #1000]

    (2946) 0x4882f8 LDR	X9, [X9]

    (2946) 0x4882fc LDR	X10, [X10]

    (2946) 0x488300 LDR	X27, [X11]

    (2946) 0x488304 B	488324

      (2948) 0x488308 LDR	D1, [X9, X8,LSL #3]

      (2948) 0x48830c LDR	D2, [X10, X11,LSL #3]

      (2948) 0x488310 FMADD	D1, D1, D0, D2

      (2948) 0x488314 STR	D1, [X10, X11,LSL #3]

      (2948) 0x488318 ADD	X8, X8, #1

      (2948) 0x48831c CMP	X8, X23

      (2948) 0x488320 B.GE	48836c

      (2948) 0x488324 LDR	X11, [X20]

      (2948) 0x488328 LDR	X12, [X5, X8,LSL #3]

      (2948) 0x48832c ADD	X24, X12, X11

      (2948) 0x488330 LDR	X11, [X0, X24,LSL #3]

      (2948) 0x488334 CMP	X11, X19

      (2948) 0x488338 B.GE	488308

      (2948) 0x48833c STR	X2, [X0, X24,LSL #3]

      (2948) 0x488340 LDR	D1, [X9, X8,LSL #3]

      (2948) 0x488344 LDR	X11, [X20]

      (2948) 0x488348 SUB	X11, X24, X11

      (2948) 0x48834c STR	X11, [X27, X2,LSL #3]

      (2948) 0x488350 FMUL	D1, D1, D0

      (2948) 0x488354 LDR	X23, [X13, X7,LSL #3]

      (2948) 0x488358 STR	D1, [X10, X2,LSL #3]

      (2948) 0x48835c ADD	X2, X2, #1

      (2948) 0x488360 ADD	X8, X8, #1

      (2948) 0x488364 CMP	X8, X23

      (2948) 0x488368 B.LT	488324

    (2946) 0x48836c LDR	X8, [X14, X30,LSL #3]

    (2946) 0x488370 LDR	X23, [X14, X7,LSL #3]

    (2946) 0x488374 CMP	X8, X23

    (2946) 0x488378 B.GE	4882c0

    (2946) 0x48837c LDUR	X9, [X29, #448]

    (2946) 0x488380 LDR	X10, [X25]

    (2946) 0x488384 LDR	X27, [X21]

    (2946) 0x488388 LDR	X9, [X9]

    (2946) 0x48838c B	4883bc

0x488390 HINT	#0

0x488394 HINT	#0

0x488398 HINT	#0

0x48839c HINT	#0

      (2947) 0x4883a0 LDR	D1, [X9, X8,LSL #3]

      (2947) 0x4883a4 LDR	D2, [X10, X11,LSL #3]

      (2947) 0x4883a8 FMADD	D1, D1, D0, D2

      (2947) 0x4883ac STR	D1, [X10, X11,LSL #3]

      (2947) 0x4883b0 ADD	X8, X8, #1

      (2947) 0x4883b4 CMP	X8, X23

      (2947) 0x4883b8 B.GE	4882c0

      (2947) 0x4883bc LDR	X24, [X6, X8,LSL #3]

      (2947) 0x4883c0 LDR	X11, [X0, X24,LSL #3]

      (2947) 0x4883c4 CMP	X11, X22

      (2947) 0x4883c8 B.GE	4883a0

      (2947) 0x4883cc LDR	D1, [X9, X8,LSL #3]

      (2947) 0x4883d0 STR	X1, [X0, X24,LSL #3]

      (2947) 0x4883d4 STR	X24, [X27, X1,LSL #3]

      (2947) 0x4883d8 LDR	X23, [X14, X7,LSL #3]

      (2947) 0x4883dc FMUL	D1, D1, D0

      (2947) 0x4883e0 STR	D1, [X10, X1,LSL #3]

      (2947) 0x4883e4 ADD	X1, X1, #1

      (2947) 0x4883e8 ADD	X8, X8, #1

      (2947) 0x4883ec CMP	X8, X23

      (2947) 0x4883f0 B.LT	4883bc

    (2946) 0x4883f4 B	4882c0

0x4883f8 HINT	#0

0x4883fc HINT	#0

  (2942) 0x488400 ORR	X2, XZR, X19

  (2942) 0x488404 LDR	X3, [X15, X26,LSL #3]

  (2942) 0x488408 ADD	X26, X26, #1

  (2942) 0x48840c LDR	X8, [X15, X26,LSL #3]

  (2942) 0x488410 CMP	X3, X8

  (2942) 0x488414 B.GE	488240

(2943) 0x488418 B	488438

0x48841c HINT	#0

  (2942) 0x488420 ORR	X2, XZR, X19

  (2942) 0x488424 LDR	X3, [X15, X26,LSL #3]

  (2942) 0x488428 ADD	X26, X26, #1

  (2942) 0x48842c LDR	X8, [X15, X26,LSL #3]

  (2942) 0x488430 CMP	X3, X8

  (2942) 0x488434 B.GE	488240

(2943) 0x488438 LDP	X9, X8, [SP, #64]

(2943) 0x48843c LDR	X4, [X9]

(2943) 0x488440 LDR	X5, [X8]

(2943) 0x488444 LDP	X9, X8, [SP, #80]

(2943) 0x488448 LDR	X6, [X9]

(2943) 0x48844c LDR	X7, [X8]

(2943) 0x488450 B	488470

0x488454 HINT	#0

0x488458 HINT	#0

0x48845c HINT	#0

(2943) 0x488460 LDR	X8, [X15, X26,LSL #3]

(2943) 0x488464 ADD	X3, X3, #1

(2943) 0x488468 CMP	X3, X8

(2943) 0x48846c B.GE	488240

(2943) 0x488470 LDR	X8, [X16, X3,LSL #3]

(2943) 0x488474 LDR	D0, [X17, X3,LSL #3]

(2943) 0x488478 ADD	X30, X8, #1

(2943) 0x48847c LDR	X9, [X18, X8,LSL #3]

(2943) 0x488480 LDR	X27, [X18, X30,LSL #3]

(2943) 0x488484 CMP	X9, X27

(2943) 0x488488 B.GE	4884f4

(2943) 0x48848c LDUR	X10, [X29, #464]

(2943) 0x488490 LDR	X23, [X25]

(2943) 0x488494 LDR	X24, [X21]

(2943) 0x488498 LDR	X10, [X10]

(2943) 0x48849c B	4884bc

  (2945) 0x4884a0 LDR	D1, [X10, X9,LSL #3]

  (2945) 0x4884a4 LDR	D2, [X23, X12,LSL #3]

  (2945) 0x4884a8 FMADD	D1, D1, D0, D2

  (2945) 0x4884ac STR	D1, [X23, X12,LSL #3]

  (2945) 0x4884b0 ADD	X9, X9, #1

  (2945) 0x4884b4 CMP	X9, X27

  (2945) 0x4884b8 B.GE	4884f4

  (2945) 0x4884bc LDR	X11, [X4, X9,LSL #3]

  (2945) 0x4884c0 LDR	X12, [X0, X11,LSL #3]

  (2945) 0x4884c4 CMP	X12, X22

  (2945) 0x4884c8 B.GE	4884a0

  (2945) 0x4884cc LDR	D1, [X10, X9,LSL #3]

  (2945) 0x4884d0 STR	X1, [X0, X11,LSL #3]

  (2945) 0x4884d4 STR	X11, [X24, X1,LSL #3]

  (2945) 0x4884d8 LDR	X27, [X18, X30,LSL #3]

  (2945) 0x4884dc FMUL	D1, D1, D0

  (2945) 0x4884e0 STR	D1, [X23, X1,LSL #3]

  (2945) 0x4884e4 ADD	X1, X1, #1

  (2945) 0x4884e8 ADD	X9, X9, #1

  (2945) 0x4884ec CMP	X9, X27

  (2945) 0x4884f0 B.LT	4884bc

(2943) 0x4884f4 LDR	X9, [X28]

(2943) 0x4884f8 CBZ	X9, 488460

(2943) 0x4884fc LDR	X8, [X5, X8,LSL #3]

(2943) 0x488500 LDR	X23, [X5, X30,LSL #3]

(2943) 0x488504 CMP	X8, X23

(2943) 0x488508 B.GE	488460

(2943) 0x48850c LDUR	X9, [X29, #456]

(2943) 0x488510 LDP	X10, X11, [X29, #1000]

(2943) 0x488514 LDR	X9, [X9]

(2943) 0x488518 LDR	X10, [X10]

(2943) 0x48851c LDR	X27, [X11]

(2943) 0x488520 B	488540

  (2944) 0x488524 LDR	D1, [X9, X8,LSL #3]

  (2944) 0x488528 LDR	D2, [X10, X11,LSL #3]

  (2944) 0x48852c FMADD	D1, D1, D0, D2

  (2944) 0x488530 STR	D1, [X10, X11,LSL #3]

  (2944) 0x488534 ADD	X8, X8, #1

  (2944) 0x488538 CMP	X8, X23

  (2944) 0x48853c B.GE	488460

  (2944) 0x488540 LDR	X12, [X7, X8,LSL #3]

  (2944) 0x488544 LDR	X11, [X20]

  (2944) 0x488548 LDR	X12, [X6, X12,LSL #3]

  (2944) 0x48854c ADD	X24, X12, X11

  (2944) 0x488550 LDR	X11, [X0, X24,LSL #3]

  (2944) 0x488554 CMP	X11, X19

  (2944) 0x488558 B.GE	488524

  (2944) 0x48855c STR	X2, [X0, X24,LSL #3]

  (2944) 0x488560 LDR	D1, [X9, X8,LSL #3]

  (2944) 0x488564 LDR	X11, [X20]

  (2944) 0x488568 SUB	X11, X24, X11

  (2944) 0x48856c STR	X11, [X27, X2,LSL #3]

  (2944) 0x488570 FMUL	D1, D1, D0

  (2944) 0x488574 LDR	X23, [X5, X30,LSL #3]

  (2944) 0x488578 STR	D1, [X10, X2,LSL #3]

  (2944) 0x48857c ADD	X2, X2, #1

  (2944) 0x488580 ADD	X8, X8, #1

  (2944) 0x488584 CMP	X8, X23

  (2944) 0x488588 B.LT	488540

(2943) 0x48858c B	488460

0x488590 LDP	X20, X19, [SP, #304]

0x488594 LDP	X22, X21, [SP, #288]

0x488598 LDP	X24, X23, [SP, #272]

0x48859c LDP	X26, X25, [SP, #256]

0x4885a0 LDP	X28, X27, [SP, #240]

0x4885a4 LDP	X29, X30, [SP, #224]

0x4885a8 ADD	SP, SP, #320

0x4885ac B	4ac5b0

Coverage (%)	Name	Source Location	Module
►98.56+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.44+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_ParMatmul	par_csr_matop.c:999	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1226	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	par_csr_matop.c:829-995
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:829,840-859,865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989,995.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 29.17 to 10.00 cycles (2.92x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:857
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:840
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:841

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	147
nb uops	130
loop length	588
used w registers	1
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	31

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.25 cycles
front end	16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	29.17	28.83	29.00	16.50	16.50
cycles	5.00	5.00	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	29.17	28.83	29.00	16.50	16.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	16.25
Dispatch	29.17
DIV/SQRT	5.00-20.00
Overall L1	29.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	29%
load	25%
store	31%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.17 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 488030

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X4, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X28, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X27, X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X24, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X10, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X21, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4ae1b0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ae190 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X13, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SDIV X9, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X8, X9, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X11, X9, X23, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD X12, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X10, X10, X9	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
CMP X23, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X12, X10, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X9, X9, X23	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
CSEL X26, X11, X9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBNZ X10, 488178 <hypre_ParMatmul.omp_outlined.6+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4881dc <hypre_ParMatmul.omp_outlined.6+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 488590 <hypre_ParMatmul.omp_outlined.6+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X24, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X23, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4881c8 <hypre_ParMatmul.omp_outlined.6+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 488590 <hypre_ParMatmul.omp_outlined.6+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X17, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X8, X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 488254 <hypre_ParMatmul.omp_outlined.6+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ac5b0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	par_csr_matop.c:829-995
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:857
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:840
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:841

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	147
nb uops	130
loop length	588
used w registers	1
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	31

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.25 cycles
front end	16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	29.17	28.83	29.00	16.50	16.50
cycles	5.00	5.00	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	29.17	28.83	29.00	16.50	16.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	16.25
Dispatch	29.17
DIV/SQRT	5.00-20.00
Overall L1	29.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	29%
load	25%
store	31%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.17 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 488030

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X4, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X28, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X27, X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X24, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X10, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X21, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4ae1b0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ae190 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X13, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SDIV X9, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X8, X9, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X11, X9, X23, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD X12, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X10, X10, X9	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
CMP X23, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X12, X10, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X9, X9, X23	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
CSEL X26, X11, X9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBNZ X10, 488178 <hypre_ParMatmul.omp_outlined.6+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4881dc <hypre_ParMatmul.omp_outlined.6+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 488590 <hypre_ParMatmul.omp_outlined.6+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X24, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X23, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ac4b0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4881c8 <hypre_ParMatmul.omp_outlined.6+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 488590 <hypre_ParMatmul.omp_outlined.6+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X17, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X8, X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 488254 <hypre_ParMatmul.omp_outlined.6+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ac5b0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul.omp_outlined.6–	0.76	0.36
▼Loop 2943 - par_csr_matop.c:865-989 - exec–	0.21	0.07
○Loop 2945 - par_csr_matop.c:946-965 - exec	0.53	0.18
▼Loop 2942 - par_csr_matop.c:865-937 - exec–	0.01	0.01
▼Loop 2946 - par_csr_matop.c:888-928 - exec–	0.00	0.00
○Loop 2947 - par_csr_matop.c:917-928 - exec	0.00	0.00
○Loop 2948 - par_csr_matop.c:897-915 - exec	0.00	0.00
○Loop 2944 - par_csr_matop.c:970-989 - exec	0.00	0.00
○Loop 2949 - par_csr_matop.c:858-859 - exec	0.01	0.01

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Matching between your function (in the source code) and the binary function

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Vector efficiency ratios

Cycles and memory resources usage

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ASM code

Vectorization

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CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code