OV - exec - Function hypre_IJMatrixSetValuesOMPParCSR.omp

	Function: hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14	Module: exec	Source: IJMatrix_parcsr.c:3240-3484 [...]	Coverage (incl. loops): 0.18% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3484

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

3284:          }

3285: #ifdef HYPRE_USING_OPENMP

3286: #pragma omp barrier

3287: #endif

3288:          indx = 0;

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

3323:       		           not_found = 0;

3324:       		           break;

3325:       	                }

3326:       	             }

3327:       	             if (not_found)

3328:       	             {

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

[...]

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

[...]

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

3411: 	    	              if (print_level)

[...]

3417: 	                }

3418: 	                not_found = 1;

3419: 	             }

3420: 	             else  /* insert into diag */

3421: 	             {

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

[...]

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

3445: 	    	              if (print_level)

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

0x49bc30 SUB	SP, SP, #352

0x49bc34 STP	X29, X30, [SP, #256]

0x49bc38 STP	X28, X27, [SP, #272]

0x49bc3c STP	X26, X25, [SP, #288]

0x49bc40 STP	X24, X23, [SP, #304]

0x49bc44 STP	X22, X21, [SP, #320]

0x49bc48 STP	X20, X19, [SP, #336]

0x49bc4c ADD	X29, SP, #256

0x49bc50 ORR	X28, XZR, X7

0x49bc54 ORR	X21, XZR, X6

0x49bc58 ORR	X24, XZR, X5

0x49bc5c STUR	X4, [X29, #440]

0x49bc60 ORR	X23, XZR, X3

0x49bc64 ORR	X26, XZR, X2

0x49bc68 ORR	X25, XZR, X0

0x49bc6c BL	4ae190

0x49bc70 ORR	X27, XZR, X0

0x49bc74 BL	4ae1b0

0x49bc78 LDR	X8, [X26]

0x49bc7c ORR	X22, XZR, X0

0x49bc80 SDIV	X10, X8, X27

0x49bc84 ADD	X13, X10, #1

0x49bc88 MSUB	X11, X10, X27, X8

0x49bc8c ADD	X8, X0, #1

0x49bc90 MADD	X12, X10, X8, X11

0x49bc94 MUL	X8, X13, X8

0x49bc98 MADD	X9, X10, X0, X11

0x49bc9c MUL	X14, X13, X0

0x49bca0 CMP	X0, X11

0x49bca4 CSEL	X15, X12, X8, #10

0x49bca8 LDR	X12, [X23]

0x49bcac CSEL	X16, X9, X14, #10

0x49bcb0 CMP	X16, X15

0x49bcb4 ADD	X8, X12, X0,LSL #3

0x49bcb8 STR	XZR, [X8]

0x49bcbc B.GE	49bd78

0x49bcc0 LDUR	X9, [X29, #440]

0x49bcc4 CMP	X22, X11

0x49bcc8 CSEL	X11, X22, X11, #11

0x49bccc MADD	X10, X22, X10, X11

0x49bcd0 SUB	X11, X15, X10

0x49bcd4 LDR	X9, [X9]

0x49bcd8 CMP	X11, #14

0x49bcdc B.CC	49bd54

0x49bce0 ADD	X10, X12, X22,LSL #3

0x49bce4 ADD	X12, X9, X15,LSL #3

0x49bce8 ADD	X13, X9, X16,LSL #3

0x49bcec ADD	X10, X10, #8

0x49bcf0 CMP	X8, X12

0x49bcf4 CCMP	X13, X10, #2, #3

0x49bcf8 B.CC	49bd54

0x49bcfc AND	X12, X11, #0x0

0x49bd00 MOVI	V0.2D, #0

0x49bd04 MOVI	V1.2D, #0

0x49bd08 ADD	X13, X13, #16

0x49bd0c AND	X14, X11, #0x0

0x49bd10 ADD	X10, X16, X12

0x49bd14 HINT	#0

0x49bd18 HINT	#0

0x49bd1c HINT	#0

(3450) 0x49bd20 LDP	Q2, Q3, [X13, #2032]

(3450) 0x49bd24 ADD	X13, X13, #32

(3450) 0x49bd28 SUBS	X14, X14, #4

(3450) 0x49bd2c ADD	V1.2D, V1.2D, V3.2D

(3450) 0x49bd30 ADD	V0.2D, V0.2D, V2.2D

(3450) 0x49bd34 B.NE	49bd20

0x49bd38 ADD	V0.2D, V1.2D, V0.2D

0x49bd3c CMP	X11, X12

0x49bd40 ADDP	D0, V0.2D

0x49bd44 FMOV	X13, D0

0x49bd48 STR	D0, [X8]

0x49bd4c B.NE	49bd60

0x49bd50 B	49bd78

0x49bd54 ORR	X13, XZR, XZR

0x49bd58 ORR	X10, XZR, X16

0x49bd5c HINT	#0

(3449) 0x49bd60 LDR	X11, [X9, X10,LSL #3]

(3449) 0x49bd64 ADD	X10, X10, #1

(3449) 0x49bd68 CMP	X10, X15

(3449) 0x49bd6c ADD	X13, X13, X11

(3449) 0x49bd70 STR	X13, [X8]

(3449) 0x49bd74 B.LT	49bd60

0x49bd78 LDR	W25, [X25]

0x49bd7c ADRP	X0,

0x49bd80 ADD	X0, X0, #3768

0x49bd84 ORR	X19, XZR, X16

0x49bd88 STUR	X15, [X29, #424]

0x49bd8c ORR	W1, WZR, W25

0x49bd90 BL	410070

0x49bd94 CBNZ	X22, 49bddc

0x49bd98 LDR	X8, [X24]

0x49bd9c CMP	X8, #1

0x49bda0 B.LT	49bddc

0x49bda4 LDR	X8, [X23]

0x49bda8 ORR	X10, XZR, XZR

0x49bdac LDR	X9, [X8], #8

0x49bdb0 HINT	#0

0x49bdb4 HINT	#0

0x49bdb8 HINT	#0

0x49bdbc HINT	#0

(3448) 0x49bdc0 LDR	X11, [X8, X10,LSL #3]

(3448) 0x49bdc4 ADD	X9, X11, X9

(3448) 0x49bdc8 STR	X9, [X8, X10,LSL #3]

(3448) 0x49bdcc ADD	X10, X10, #1

(3448) 0x49bdd0 LDR	X11, [X24]

(3448) 0x49bdd4 CMP	X10, X11

(3448) 0x49bdd8 B.LT	49bdc0

0x49bddc ADRP	X0,

0x49bde0 ADD	X0, X0, #3792

0x49bde4 ORR	W1, WZR, W25

0x49bde8 BL	410070

0x49bdec CBZ	X22, 49be14

0x49bdf0 LDR	X8, [X23]

0x49bdf4 ADD	X8, X8, X22,LSL #3

0x49bdf8 LDUR	X24, [X8, #504]

0x49bdfc LDUR	X7, [X29, #424]

0x49be00 LDUR	X23, [X29, #440]

0x49be04 ORR	X30, XZR, X19

0x49be08 CMP	X19, X7

0x49be0c B.LT	49be2c

0x49be10 B	49c65c

0x49be14 ORR	X24, XZR, XZR

0x49be18 LDUR	X7, [X29, #424]

0x49be1c LDUR	X23, [X29, #440]

0x49be20 ORR	X30, XZR, X19

0x49be24 CMP	X19, X7

0x49be28 B.GE	49c65c

0x49be2c LDR	X8, [X29, #256]

0x49be30 LDP	X26, X19, [X29, #264]

0x49be34 MOVN	X27, #0

0x49be38 LDR	X10, [X29, #96]

0x49be3c STUR	XZR, [X29, #464]

0x49be40 STR	X28, [SP, #88]

0x49be44 STR	X8, [SP, #120]

0x49be48 LDP	X8, X3, [X29, #240]

0x49be4c STP	X26, X21, [X29, #920]

0x49be50 STUR	X10, [X29, #456]

0x49be54 STR	X8, [SP, #64]

0x49be58 LDR	X8, [X29, #232]

0x49be5c STR	X8, [SP, #56]

0x49be60 LDR	X8, [X29, #224]

0x49be64 STR	X8, [SP, #16]

0x49be68 LDR	X8, [X29, #216]

0x49be6c STR	X8, [SP, #8]

0x49be70 LDR	X8, [X29, #208]

0x49be74 STR	X8, [SP, #48]

0x49be78 LDR	X8, [X29, #200]

0x49be7c STR	X8, [SP, #40]

0x49be80 LDP	X8, X9, [X29, #184]

0x49be84 STP	X8, X9, [X29, #984]

0x49be88 LDR	X8, [X29, #176]

0x49be8c STR	X8, [SP, #32]

0x49be90 LDR	X8, [X29, #168]

0x49be94 STR	X8, [SP, #24]

0x49be98 LDP	X8, X4, [X29, #152]

0x49be9c STR	X8, [SP, #80]

0x49bea0 LDP	X8, X9, [X29, #136]

0x49bea4 STP	X4, X3, [X29, #904]

0x49bea8 STUR	X8, [X29, #448]

0x49beac LDR	X8, [X29, #128]

0x49beb0 STUR	X9, [X29, #496]

0x49beb4 STR	X8, [SP, #104]

0x49beb8 LDR	X8, [X29, #120]

0x49bebc STR	X8, [SP, #96]

0x49bec0 LDR	X8, [X29, #112]

0x49bec4 STR	X8, [SP, #112]

0x49bec8 LDR	X8, [X29, #104]

0x49becc STR	X8, [SP, #128]

0x49bed0 B	49bf10

      (3433) 0x49bed4 ORR	X26, XZR, X9

      (3433) 0x49bed8 ORR	X21, XZR, X8

      (3433) 0x49bedc LDP	X4, X3, [X29, #904]

      (3433) 0x49bee0 LDR	X8, [X4]

      (3433) 0x49bee4 LDP	X9, X8, [X8, #56]

      (3433) 0x49bee8 STR	X26, [X9, X5,LSL #3]

      (3433) 0x49beec STR	X21, [X8, X5,LSL #3]

      (3433) 0x49bef0 LDP	X26, X21, [X29, #920]

      (3433) 0x49bef4 HINT	#0

      (3433) 0x49bef8 HINT	#0

      (3433) 0x49befc HINT	#0

      (3433) 0x49bf00 LDUR	X10, [X29, #456]

        (3432) 0x49bf04 ADD	X30, X30, #1

        (3432) 0x49bf08 CMP	X30, X7

        (3432) 0x49bf0c B.GE	49c65c

        (3432) 0x49bf10 LDR	X8, [X21]

        (3432) 0x49bf14 LDR	X9, [X10]

        (3432) 0x49bf18 LDR	X25, [X8, X30,LSL #3]

        (3432) 0x49bf1c LDR	X8, [X23]

        (3432) 0x49bf20 LDR	X20, [X8, X30,LSL #3]

        (3432) 0x49bf24 LDR	X8, [X28]

        (3432) 0x49bf28 ADD	X8, X8, X9,LSL #3

        (3432) 0x49bf2c LDR	X9, [X8]

        (3432) 0x49bf30 SUBS	X5, X25, X9

        (3432) 0x49bf34 B.LT	49c000

        (3432) 0x49bf38 LDR	X8, [X8, #8]

        (3432) 0x49bf3c CMP	X25, X8

        (3432) 0x49bf40 B.GE	49c000

      (3433) 0x49bf44 LDR	X8, [SP, #128]

      (3433) 0x49bf48 STUR	X5, [X29, #488]

      (3433) 0x49bf4c LDR	X8, [X8]

      (3433) 0x49bf50 CBZ	X8, 49c16c

    (3441) 0x49bf54 LDR	X16, [SP, #112]

    (3441) 0x49bf58 STUR	X30, [X29, #432]

    (3441) 0x49bf5c LDR	X8, [X16]

    (3441) 0x49bf60 LDR	X23, [X8, X5,LSL #3]

    (3441) 0x49bf64 LDR	X8, [SP, #96]

    (3441) 0x49bf68 LDR	X8, [X8]

    (3441) 0x49bf6c LDR	X28, [X8, X5,LSL #3]

    (3441) 0x49bf70 LDR	X8, [SP, #104]

    (3441) 0x49bf74 LDR	X8, [X8]

    (3441) 0x49bf78 LDR	X17, [X8, X5,LSL #3]

    (3441) 0x49bf7c LDUR	X8, [X29, #448]

    (3441) 0x49bf80 LDR	X8, [X8]

    (3441) 0x49bf84 LDR	X25, [X8, X5,LSL #3]

    (3441) 0x49bf88 SUB	X8, X17, X25

    (3441) 0x49bf8c SUBS	X26, X20, X8

    (3441) 0x49bf90 B.LE	49c2b4

    (3441) 0x49bf94 MOVZ	W1, #8

    (3441) 0x49bf98 ORR	X0, XZR, X26

    (3441) 0x49bf9c STUR	X17, [X29, #464]

    (3441) 0x49bfa0 BL	4ac4b0

    (3441) 0x49bfa4 MOVZ	W1, #8

    (3441) 0x49bfa8 ORR	X21, XZR, X0

    (3441) 0x49bfac ORR	X0, XZR, X26

    (3441) 0x49bfb0 BL	4ac4b0

    (3441) 0x49bfb4 LDUR	X17, [X29, #464]

    (3441) 0x49bfb8 ORR	X18, XZR, X21

    (3441) 0x49bfbc LDUR	X21, [X29, #416]

    (3441) 0x49bfc0 LDUR	X5, [X29, #488]

    (3441) 0x49bfc4 LDR	X16, [SP, #112]

    (3441) 0x49bfc8 CMP	X20, #0

    (3441) 0x49bfcc STUR	X0, [X29, #464]

    (3441) 0x49bfd0 B.GT	49c2c8

    (3441) 0x49bfd4 LDP	X23, X8, [X29, #952]

    (3441) 0x49bfd8 LDR	X28, [SP, #88]

    (3441) 0x49bfdc LDR	X8, [X8]

    (3441) 0x49bfe0 STR	X25, [X8, X5,LSL #3]

    (3441) 0x49bfe4 LDUR	X26, [X29, #408]

    (3441) 0x49bfe8 CBNZ	X18, 49c63c

    (3441) 0x49bfec B	49c650

0x49bff0 HINT	#0

0x49bff4 HINT	#0

0x49bff8 HINT	#0

0x49bffc HINT	#0

        (3432) 0x49c000 LDR	X8, [X4]

        (3432) 0x49c004 LDR	X12, [X3]

        (3432) 0x49c008 ADD	X24, X20, X24

        (3432) 0x49c00c CMP	X8, #0

        (3432) 0x49c010 CCMP	X12, #1, #8, #1

        (3432) 0x49c014 B.LT	49bf04

        (3432) 0x49c018 CMP	X20, #1

        (3432) 0x49c01c B.LT	49bf04

      (3433) 0x49c020 LDR	X10, [SP, #120]

      (3433) 0x49c024 ORR	X8, XZR, XZR

      (3433) 0x49c028 ORR	X9, XZR, XZR

      (3433) 0x49c02c LDR	X10, [X10]

      (3433) 0x49c030 B	49c054

0x49c034 HINT	#0

0x49c038 HINT	#0

0x49c03c HINT	#0

        (3434) 0x49c040 LDR	X12, [X3]

        (3434) 0x49c044 ADD	X9, X9, #2

        (3434) 0x49c048 ADD	X8, X11, X8

        (3434) 0x49c04c CMP	X9, X12

        (3434) 0x49c050 B.GE	49bf00

        (3434) 0x49c054 ADD	X13, X10, X9,LSL #3

        (3434) 0x49c058 LDP	X13, X11, [X13]

        (3434) 0x49c05c CMP	X13, X25

        (3434) 0x49c060 B.NE	49c044

        (3434) 0x49c064 CMP	X11, #1

        (3434) 0x49c068 B.LT	49c044

        (3434) 0x49c06c LDUR	X14, [X29, #496]

        (3434) 0x49c070 LDR	X13, [X26]

        (3434) 0x49c074 AND	X15, X11, #0x0

        (3434) 0x49c078 ORR	X12, XZR, XZR

        (3434) 0x49c07c LDR	X14, [X14]

        (3434) 0x49c080 ADD	X16, X13, X8,LSL #3

        (3434) 0x49c084 ADD	X16, X16, #8

        (3434) 0x49c088 B	49c098

          (3435) 0x49c08c ADD	X12, X12, #1

          (3435) 0x49c090 CMP	X12, X20

          (3435) 0x49c094 B.EQ	49c040

          (3435) 0x49c098 LDR	X17, [X19]

          (3435) 0x49c09c CMP	X11, #1

          (3435) 0x49c0a0 ORR	X18, XZR, X8

          (3435) 0x49c0a4 B.EQ	49c148

          (3435) 0x49c0a8 AND	X18, X11, #0x0

          (3435) 0x49c0ac ORR	X0, XZR, X16

          (3435) 0x49c0b0 B	49c0cc

0x49c0b4 HINT	#0

0x49c0b8 HINT	#0

0x49c0bc HINT	#0

            (3436) 0x49c0c0 ADD	X0, X0, #16

            (3436) 0x49c0c4 SUBS	X18, X18, #2

            (3436) 0x49c0c8 B.EQ	49c140

            (3436) 0x49c0cc LDUR	X1, [X0, #504]

            (3436) 0x49c0d0 LDR	X2, [X14, X12,LSL #3]

            (3436) 0x49c0d4 CMP	X1, X2

            (3436) 0x49c0d8 B.EQ	49c100

            (3436) 0x49c0dc LDR	X1, [X0]

            (3436) 0x49c0e0 LDR	X2, [X14, X12,LSL #3]

            (3436) 0x49c0e4 CMP	X1, X2

            (3436) 0x49c0e8 B.NE	49c0c0

            (3436) 0x49c0ec B	49c120

0x49c0f0 HINT	#0

0x49c0f4 HINT	#0

0x49c0f8 HINT	#0

0x49c0fc HINT	#0

            (3436) 0x49c100 STUR	X27, [X0, #504]

            (3436) 0x49c104 LDR	X1, [X17, X22,LSL #3]

            (3436) 0x49c108 ADD	X1, X1, #1

            (3436) 0x49c10c STR	X1, [X17, X22,LSL #3]

            (3436) 0x49c110 LDR	X1, [X0]

            (3436) 0x49c114 LDR	X2, [X14, X12,LSL #3]

            (3436) 0x49c118 CMP	X1, X2

            (3436) 0x49c11c B.NE	49c0c0

            (3436) 0x49c120 STR	X27, [X0]

            (3436) 0x49c124 LDR	X1, [X17, X22,LSL #3]

            (3436) 0x49c128 ADD	X1, X1, #1

            (3436) 0x49c12c STR	X1, [X17, X22,LSL #3]

            (3436) 0x49c130 B	49c0c0

0x49c134 HINT	#0

0x49c138 HINT	#0

0x49c13c HINT	#0

          (3435) 0x49c140 ADD	X18, X8, X15

          (3435) 0x49c144 TBZ	W11, #0, 49c08c

          (3435) 0x49c148 LDR	X0, [X13, X18,LSL #3]

          (3435) 0x49c14c LDR	X1, [X14, X12,LSL #3]

          (3435) 0x49c150 CMP	X0, X1

          (3435) 0x49c154 B.NE	49c08c

          (3435) 0x49c158 STR	X27, [X13, X18,LSL #3]

          (3435) 0x49c15c LDR	X18, [X17, X22,LSL #3]

          (3435) 0x49c160 ADD	X18, X18, #1

          (3435) 0x49c164 STR	X18, [X17, X22,LSL #3]

          (3435) 0x49c168 B	49c08c

      (3433) 0x49c16c LDR	X8, [X4]

      (3433) 0x49c170 UBFM	X12, X5, #61, #60

      (3433) 0x49c174 CMP	X20, #1

      (3433) 0x49c178 LDP	X10, X9, [X8, #56]

      (3433) 0x49c17c LDR	X8, [X9, X12]

      (3433) 0x49c180 LDR	X9, [X10, X12]

      (3433) 0x49c184 B.LT	49bed4

      (3433) 0x49c188 LDP	X11, X13, [SP, #24]

      (3433) 0x49c18c LDUR	X15, [X29, #496]

      (3433) 0x49c190 ADD	X14, X12, #8

      (3433) 0x49c194 ORR	X10, XZR, XZR

      (3433) 0x49c198 ORR	X21, XZR, X8

      (3433) 0x49c19c ORR	X26, XZR, X9

      (3433) 0x49c1a0 LDR	X17, [SP, #80]

      (3433) 0x49c1a4 LDP	X16, X18, [SP, #56]

      (3433) 0x49c1a8 LDR	X11, [X11]

      (3433) 0x49c1ac LDR	X13, [X13]

      (3433) 0x49c1b0 LDP	X0, X1, [SP, #40]

      (3433) 0x49c1b4 LDR	X15, [X15]

      (3433) 0x49c1b8 LDR	X16, [X16]

      (3433) 0x49c1bc LDR	X17, [X17]

      (3433) 0x49c1c0 LDR	X18, [X18]

      (3433) 0x49c1c4 LDR	X0, [X0]

      (3433) 0x49c1c8 LDR	X1, [X1]

      (3433) 0x49c1cc LDR	X12, [X11, X14]

      (3433) 0x49c1d0 LDR	X14, [X13, X14]

      (3433) 0x49c1d4 B	49c1fc

0x49c1d8 HINT	#0

0x49c1dc HINT	#0

        (3437) 0x49c1e0 LDR	D0, [X17, X24,LSL #3]

        (3437) 0x49c1e4 STR	D0, [X4]

        (3437) 0x49c1e8 LDUR	X5, [X29, #488]

        (3437) 0x49c1ec ADD	X10, X10, #1

        (3437) 0x49c1f0 ADD	X24, X24, #1

        (3437) 0x49c1f4 CMP	X10, X20

        (3437) 0x49c1f8 B.EQ	49bedc

        (3437) 0x49c1fc LDP	X3, X4, [X29, #984]

        (3437) 0x49c200 LDR	X2, [X15, X24,LSL #3]

        (3437) 0x49c204 LDR	X3, [X3]

        (3437) 0x49c208 LDR	X4, [X4]

        (3437) 0x49c20c CMP	X2, X3

        (3437) 0x49c210 CCMP	X2, X4, #0, #10

        (3437) 0x49c214 B.LE	49c260

        (3437) 0x49c218 LDR	X5, [X13, X5,LSL #3]

        (3437) 0x49c21c SUBS	X3, X8, X5

        (3437) 0x49c220 B.LE	49c244

        (3437) 0x49c224 ADD	X4, X1, X5,LSL #3

        (3437) 0x49c228 ADD	X5, X0, X5,LSL #3

          (3439) 0x49c22c LDR	X6, [X5], #8

          (3439) 0x49c230 CMP	X6, X2

          (3439) 0x49c234 B.EQ	49c1e0

          (3439) 0x49c238 ADD	X4, X4, #8

          (3439) 0x49c23c SUBS	X3, X3, #1

          (3439) 0x49c240 B.NE	49c22c

        (3437) 0x49c244 CMP	X21, X14

        (3437) 0x49c248 B.GE	49c514

        (3437) 0x49c24c LDR	D0, [X17, X24,LSL #3]

        (3437) 0x49c250 STR	X2, [X0, X21,LSL #3]

        (3437) 0x49c254 STR	D0, [X1, X21,LSL #3]

        (3437) 0x49c258 ADD	X21, X21, #1

        (3437) 0x49c25c B	49c1e8

        (3437) 0x49c260 LDR	X5, [X11, X5,LSL #3]

        (3437) 0x49c264 SUBS	X3, X9, X5

        (3437) 0x49c268 B.LE	49c298

        (3437) 0x49c26c ADD	X4, X18, X5,LSL #3

        (3437) 0x49c270 ADD	X5, X16, X5,LSL #3

        (3437) 0x49c274 HINT	#0

        (3437) 0x49c278 HINT	#0

        (3437) 0x49c27c HINT	#0

          (3438) 0x49c280 LDR	X6, [X5], #8

          (3438) 0x49c284 CMP	X6, X2

          (3438) 0x49c288 B.EQ	49c1e0

          (3438) 0x49c28c ADD	X4, X4, #8

          (3438) 0x49c290 SUBS	X3, X3, #1

          (3438) 0x49c294 B.NE	49c280

        (3437) 0x49c298 CMP	X26, X12

        (3437) 0x49c29c B.GE	49c568

        (3437) 0x49c2a0 LDR	D0, [X17, X24,LSL #3]

        (3437) 0x49c2a4 STR	X2, [X16, X26,LSL #3]

        (3437) 0x49c2a8 STR	D0, [X18, X26,LSL #3]

        (3437) 0x49c2ac ADD	X26, X26, #1

        (3437) 0x49c2b0 B	49c1e8

    (3441) 0x49c2b4 LDUR	X0, [X29, #464]

    (3441) 0x49c2b8 ORR	X18, XZR, XZR

    (3441) 0x49c2bc CMP	X20, #0

    (3441) 0x49c2c0 STUR	X0, [X29, #464]

    (3441) 0x49c2c4 B.LE	49bfd4

  (3442) 0x49c2c8 LDUR	X9, [X29, #496]

  (3442) 0x49c2cc LDR	X10, [SP, #80]

  (3442) 0x49c2d0 ORR	X21, XZR, XZR

  (3442) 0x49c2d4 ORR	X8, XZR, XZR

  (3442) 0x49c2d8 ORR	X26, XZR, X25

  (3442) 0x49c2dc LDR	X9, [X9]

  (3442) 0x49c2e0 LDR	X10, [X10]

  (3442) 0x49c2e4 B	49c308

  (3442) 0x49c2e8 LDR	D0, [X10, X24,LSL #3]

  (3442) 0x49c2ec STR	X11, [X18, X21,LSL #3]

  (3442) 0x49c2f0 STR	D0, [X0, X21,LSL #3]

  (3442) 0x49c2f4 ADD	X21, X21, #1

  (3442) 0x49c2f8 ADD	X8, X8, #1

  (3442) 0x49c2fc ADD	X24, X24, #1

  (3442) 0x49c300 CMP	X8, X20

  (3442) 0x49c304 B.EQ	49c36c

  (3442) 0x49c308 CMP	X25, #1

  (3442) 0x49c30c B.LT	49c338

(3443) 0x49c310 LDR	X11, [X9, X24,LSL #3]

(3443) 0x49c314 ORR	X13, XZR, X25

(3443) 0x49c318 ORR	X14, XZR, X23

(3443) 0x49c31c ORR	X12, XZR, X28

  (3444) 0x49c320 LDR	X15, [X14], #8

  (3444) 0x49c324 CMP	X15, X11

  (3444) 0x49c328 B.EQ	49c360

  (3444) 0x49c32c ADD	X12, X12, #8

  (3444) 0x49c330 SUBS	X13, X13, #1

  (3444) 0x49c334 B.NE	49c320

  (3442) 0x49c338 LDR	X11, [X9, X24,LSL #3]

  (3442) 0x49c33c CMP	X26, X17

  (3442) 0x49c340 B.GE	49c2e8

  (3442) 0x49c344 LDR	D0, [X10, X24,LSL #3]

  (3442) 0x49c348 STR	X11, [X23, X26,LSL #3]

  (3442) 0x49c34c STR	D0, [X28, X26,LSL #3]

  (3442) 0x49c350 ADD	X26, X26, #1

  (3442) 0x49c354 B	49c2f8

0x49c358 HINT	#0

0x49c35c HINT	#0

(3443) 0x49c360 LDR	D0, [X10, X24,LSL #3]

(3443) 0x49c364 STR	D0, [X12]

(3443) 0x49c368 B	49c2f8

  (3442) 0x49c36c LDUR	X8, [X29, #448]

  (3442) 0x49c370 ADD	X23, X26, X21

  (3442) 0x49c374 LDR	X8, [X8]

  (3442) 0x49c378 STR	X23, [X8, X5,LSL #3]

  (3442) 0x49c37c CBZ	X21, 49c458

  (3442) 0x49c380 LDR	X8, [X16]

  (3442) 0x49c384 UBFM	X20, X23, #61, #60

  (3442) 0x49c388 STR	X18, [SP, #72]

  (3442) 0x49c38c ORR	X28, XZR, X16

  (3442) 0x49c390 ORR	X1, XZR, X20

  (3442) 0x49c394 LDR	X0, [X8, X5,LSL #3]

  (3442) 0x49c398 BL	4ac520

  (3442) 0x49c39c LDR	X8, [X28]

  (3442) 0x49c3a0 LDUR	X9, [X29, #488]

  (3442) 0x49c3a4 LDR	X25, [SP, #96]

  (3442) 0x49c3a8 ORR	X1, XZR, X20

  (3442) 0x49c3ac STR	X0, [X8, X9,LSL #3]

  (3442) 0x49c3b0 LDR	X8, [X25]

  (3442) 0x49c3b4 LDUR	X9, [X29, #488]

  (3442) 0x49c3b8 LDR	X0, [X8, X9,LSL #3]

  (3442) 0x49c3bc BL	4ac520

  (3442) 0x49c3c0 LDUR	X9, [X29, #488]

  (3442) 0x49c3c4 LDR	X8, [X25]

  (3442) 0x49c3c8 LDR	X11, [SP, #88]

  (3442) 0x49c3cc CMP	X21, #1

  (3442) 0x49c3d0 STR	X0, [X8, X9,LSL #3]

  (3442) 0x49c3d4 LDR	X8, [SP, #104]

  (3442) 0x49c3d8 LDR	X8, [X8]

  (3442) 0x49c3dc STR	X23, [X8, X9,LSL #3]

  (3442) 0x49c3e0 B.LT	49c46c

  (3442) 0x49c3e4 LDR	X8, [X28]

  (3442) 0x49c3e8 LDUR	X23, [X29, #440]

  (3442) 0x49c3ec LDUR	X17, [X29, #464]

  (3442) 0x49c3f0 CMP	X21, #4

  (3442) 0x49c3f4 LDR	X18, [SP, #72]

  (3442) 0x49c3f8 LDR	X8, [X8, X9,LSL #3]

  (3442) 0x49c3fc ORR	X9, XZR, XZR

  (3442) 0x49c400 B.CS	49c484

  (3442) 0x49c404 ORR	X28, XZR, X11

  (3442) 0x49c408 ANDS	X11, X21, #0x3

  (3442) 0x49c40c B.EQ	49c5a8

  (3442) 0x49c410 ADD	X12, X0, X26,LSL #3

  (3442) 0x49c414 ADD	X13, X8, X26,LSL #3

  (3442) 0x49c418 ADD	X14, X17, X9,LSL #3

  (3442) 0x49c41c ADD	X15, X18, X9,LSL #3

  (3442) 0x49c420 ORR	X10, XZR, XZR

    (3446) 0x49c424 LDR	D0, [X14, X10,LSL #3]

    (3446) 0x49c428 LDR	X16, [X15, X10,LSL #3]

    (3446) 0x49c42c STR	X16, [X13, X10,LSL #3]

    (3446) 0x49c430 STR	D0, [X12, X10,LSL #3]

    (3446) 0x49c434 ADD	X10, X10, #1

    (3446) 0x49c438 CMP	X11, X10

    (3446) 0x49c43c B.NE	49c424

  (3442) 0x49c440 ADD	X26, X26, X10

  (3442) 0x49c444 ADD	X11, X9, X10

  (3442) 0x49c448 SUB	X9, X9, X21

  (3442) 0x49c44c CMN	X9, #4

  (3442) 0x49c450 B.LS	49c5b8

  (3442) 0x49c454 B	49c638

  (3442) 0x49c458 LDR	X28, [SP, #88]

  (3442) 0x49c45c LDP	X26, X21, [X29, #920]

  (3442) 0x49c460 LDUR	X23, [X29, #440]

  (3442) 0x49c464 CBNZ	X18, 49c63c

  (3442) 0x49c468 B	49c650

  (3442) 0x49c46c LDP	X26, X21, [X29, #920]

  (3442) 0x49c470 LDUR	X23, [X29, #440]

  (3442) 0x49c474 LDR	X18, [SP, #72]

  (3442) 0x49c478 ORR	X28, XZR, X11

  (3442) 0x49c47c CBNZ	X18, 49c63c

  (3442) 0x49c480 B	49c650

  (3442) 0x49c484 SUB	X10, X8, X18

  (3442) 0x49c488 ORR	X28, XZR, X11

  (3442) 0x49c48c ADD	X10, X10, X26,LSL #3

  (3442) 0x49c490 CMP	X10, #32

  (3442) 0x49c494 B.CC	49c408

  (3442) 0x49c498 SUB	X10, X0, X17

  (3442) 0x49c49c ADD	X10, X10, X26,LSL #3

  (3442) 0x49c4a0 CMP	X10, #32

  (3442) 0x49c4a4 B.CC	49c408

  (3442) 0x49c4a8 UBFM	X13, X26, #61, #60

  (3442) 0x49c4ac AND	X9, X21, #0x0

  (3442) 0x49c4b0 ADD	X10, X17, #16

  (3442) 0x49c4b4 ADD	X12, X18, #16

  (3442) 0x49c4b8 AND	X14, X21, #0x0

  (3442) 0x49c4bc ADD	X11, X8, X13

  (3442) 0x49c4c0 ADD	X13, X0, X13

  (3442) 0x49c4c4 ADD	X26, X26, X9

  (3442) 0x49c4c8 ADD	X11, X11, #16

  (3442) 0x49c4cc ADD	X13, X13, #16

  (3442) 0x49c4d0 HINT	#0

  (3442) 0x49c4d4 HINT	#0

  (3442) 0x49c4d8 HINT	#0

  (3442) 0x49c4dc HINT	#0

    (3447) 0x49c4e0 LDP	Q0, Q1, [X12, #2032]

    (3447) 0x49c4e4 LDP	Q2, Q3, [X10, #2032]

    (3447) 0x49c4e8 SUBS	X14, X14, #4

    (3447) 0x49c4ec ADD	X10, X10, #32

    (3447) 0x49c4f0 ADD	X12, X12, #32

    (3447) 0x49c4f4 STP	Q0, Q1, [X11, #2032]

    (3447) 0x49c4f8 STP	Q2, Q3, [X13, #2032]

    (3447) 0x49c4fc ADD	X11, X11, #32

    (3447) 0x49c500 ADD	X13, X13, #32

    (3447) 0x49c504 B.NE	49c4e0

  (3442) 0x49c508 CMP	X21, X9

  (3442) 0x49c50c B.NE	49c408

  (3442) 0x49c510 B	49c638

      (3433) 0x49c514 ADRP	X0,

      (3433) 0x49c518 ADD	X0, X0, #1344

      (3433) 0x49c51c MOVZ	W1, #3406

      (3433) 0x49c520 MOVZ	W2, #1

      (3433) 0x49c524 ORR	X20, XZR, X30

      (3433) 0x49c528 ORR	X3, XZR, XZR

      (3433) 0x49c52c BL	4aeb20

      (3433) 0x49c530 LDR	X8, [SP, #8]

      (3433) 0x49c534 MOVZ	W9, #1

      (3433) 0x49c538 ADRP	X0,

      (3433) 0x49c53c ADD	X0, X0, #1684

      (3433) 0x49c540 LDADD	X9, X8, [X8]

      (3433) 0x49c544 LDR	X8, [SP, #16]

      (3433) 0x49c548 LDR	X8, [X8]

      (3433) 0x49c54c CBZ	X8, 49c558

      (3433) 0x49c550 ORR	X1, XZR, X25

      (3433) 0x49c554 BL	4ac6c0

      (3433) 0x49c558 LDUR	X7, [X29, #424]

      (3433) 0x49c55c LDUR	X5, [X29, #488]

      (3433) 0x49c560 ORR	X30, XZR, X20

      (3433) 0x49c564 B	49bedc

      (3433) 0x49c568 ADRP	X0,

      (3433) 0x49c56c ADD	X0, X0, #1344

      (3433) 0x49c570 MOVZ	W1, #3440

      (3433) 0x49c574 MOVZ	W2, #1

      (3433) 0x49c578 ORR	X20, XZR, X30

      (3433) 0x49c57c ORR	X3, XZR, XZR

      (3433) 0x49c580 BL	4aeb20

      (3433) 0x49c584 LDR	X8, [SP, #8]

      (3433) 0x49c588 MOVZ	W9, #1

      (3433) 0x49c58c ADRP	X0,

      (3433) 0x49c590 ADD	X0, X0, #1722

      (3433) 0x49c594 LDADD	X9, X8, [X8]

      (3433) 0x49c598 LDR	X8, [SP, #16]

      (3433) 0x49c59c LDR	X8, [X8]

      (3433) 0x49c5a0 CBNZ	X8, 49c550

      (3433) 0x49c5a4 B	49c558

  (3442) 0x49c5a8 ORR	X11, XZR, X9

  (3442) 0x49c5ac SUB	X9, X9, X21

  (3442) 0x49c5b0 CMN	X9, #4

  (3442) 0x49c5b4 B.HI	49c638

  (3442) 0x49c5b8 ADD	X9, X18, X11,LSL #3

  (3442) 0x49c5bc ADD	X10, X17, X11,LSL #3

  (3442) 0x49c5c0 ADD	X12, X0, X26,LSL #3

  (3442) 0x49c5c4 ADD	X8, X8, X26,LSL #3

  (3442) 0x49c5c8 SUB	X11, X21, X11

  (3442) 0x49c5cc ADD	X9, X9, #16

  (3442) 0x49c5d0 ADD	X10, X10, #16

  (3442) 0x49c5d4 ADD	X12, X12, #16

  (3442) 0x49c5d8 ADD	X8, X8, #16

  (3442) 0x49c5dc HINT	#0

    (3445) 0x49c5e0 LDUR	D0, [X10, #496]

    (3445) 0x49c5e4 LDUR	X13, [X9, #496]

    (3445) 0x49c5e8 SUBS	X11, X11, #4

    (3445) 0x49c5ec STUR	X13, [X8, #496]

    (3445) 0x49c5f0 LDUR	X13, [X9, #504]

    (3445) 0x49c5f4 STUR	D0, [X12, #496]

    (3445) 0x49c5f8 LDUR	D0, [X10, #504]

    (3445) 0x49c5fc STUR	X13, [X8, #504]

    (3445) 0x49c600 LDR	X13, [X9]

    (3445) 0x49c604 STUR	D0, [X12, #504]

    (3445) 0x49c608 LDR	D0, [X10]

    (3445) 0x49c60c STR	X13, [X8]

    (3445) 0x49c610 LDR	X13, [X9, #8]

    (3445) 0x49c614 ADD	X9, X9, #32

    (3445) 0x49c618 STR	X13, [X8, #8]

    (3445) 0x49c61c ADD	X8, X8, #32

    (3445) 0x49c620 STR	D0, [X12]

    (3445) 0x49c624 LDR	D0, [X10, #8]

    (3445) 0x49c628 ADD	X10, X10, #32

    (3445) 0x49c62c STR	D0, [X12, #8]

    (3445) 0x49c630 ADD	X12, X12, #32

    (3445) 0x49c634 B.NE	49c5e0

  (3442) 0x49c638 LDP	X26, X21, [X29, #920]

    (3440) 0x49c63c ORR	X0, XZR, X18

    (3440) 0x49c640 BL	4ac5b0

  (3442) 0x49c644 LDUR	X0, [X29, #464]

  (3442) 0x49c648 BL	4ac5b0

  (3442) 0x49c64c STUR	XZR, [X29, #464]

    (3441) 0x49c650 LDP	X7, X30, [X29, #936]

    (3441) 0x49c654 LDP	X4, X3, [X29, #904]

    (3441) 0x49c658 B	49bf00

0x49c65c LDP	X20, X19, [SP, #336]

0x49c660 LDP	X22, X21, [SP, #320]

0x49c664 LDP	X24, X23, [SP, #304]

0x49c668 LDP	X26, X25, [SP, #288]

0x49c66c LDP	X28, X27, [SP, #272]

0x49c670 LDP	X29, X30, [SP, #256]

0x49c674 ADD	SP, SP, #352

0x49c678 RET

0x49c67c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.45+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.55+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_IJMatrixSetValuesOMPParC[...]	IJMatrix_parcsr.c:3509	exec
○	BuildIJLaplacian27pt	amg.c:2267	exec
○	main	amg.c:274	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3352,3359-3368,3376-3377,3383-3390,3399-3411,3417-3424,3433-3445,3454-3458,3466-3484.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.33 to 1.00 cycles (23.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 23.33 to 10.00 cycles (2.33x speedup).

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
7% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256
unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3278
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3286

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	180
nb uops	150
loop length	720
used w registers	3
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	2
used z registers	0
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.75 cycles
front end	18.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	15.75	15.75	15.75	15.75	1.50	1.50	1.50	1.50	23.33	23.33	23.33	15.50	15.50
cycles	8.50	8.50	15.75	15.75	15.75	15.75	1.50	1.50	1.50	1.50	23.33	23.33	23.33	15.50	15.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	18.75
Dispatch	23.33
DIV/SQRT	5.00-20.00
Overall L1	23.33

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	7%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	7%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	28%
load	35%
store	32%
mul	25%
add-sub	28%
fma	25%
other	24%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	28%
load	35%
store	32%
mul	25%
add-sub	28%
fma	25%
div/sqrt	25%
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.33 cycles. At this rate:

0% of peak load performance is reached (0.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 49bc30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X4, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ae190 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ae1b0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SDIV X10, X8, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
ADD X13, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MSUB X11, X10, X27, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X8, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X12, X10, X8, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MUL X8, X13, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MADD X9, X10, X0, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MUL X14, X13, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X15, X12, X8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X12, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CSEL X16, X9, X14, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X8, X12, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GE 49bd78 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X22, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X11, X22, X11, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X10, X22, X10, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X11, X15, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, #14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 49bd54 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X12, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X9, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X9, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X13, X10, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.CC 49bd54 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X12, X11, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVI V0.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X13, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X14, X11, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD V0.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
CMP X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADDP D0, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV X13, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B.NE 49bd60 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49bd78 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
LDR W25, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4fed7c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X19, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X15, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410070 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X22, 49bddc <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 49bddc <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X8], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <4feddc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3792	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410070 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X22, 49be14 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x1e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X24, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X23, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X30, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 49be2c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49c65c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0xa2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X23, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X30, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 49c65c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0xa2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X26, X19, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVN X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR XZR, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X28, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X3, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X26, X21, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X4, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X4, X3, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 49bf10 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
7% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256
unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3278
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3286

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	180
nb uops	150
loop length	720
used w registers	3
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	2
used z registers	0
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.75 cycles
front end	18.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	15.75	15.75	15.75	15.75	1.50	1.50	1.50	1.50	23.33	23.33	23.33	15.50	15.50
cycles	8.50	8.50	15.75	15.75	15.75	15.75	1.50	1.50	1.50	1.50	23.33	23.33	23.33	15.50	15.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	18.75
Dispatch	23.33
DIV/SQRT	5.00-20.00
Overall L1	23.33

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	7%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	7%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	28%
load	35%
store	32%
mul	25%
add-sub	28%
fma	25%
other	24%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	28%
load	35%
store	32%
mul	25%
add-sub	28%
fma	25%
div/sqrt	25%
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.33 cycles. At this rate:

0% of peak load performance is reached (0.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 49bc30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X4, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ae190 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ae1b0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SDIV X10, X8, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
ADD X13, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MSUB X11, X10, X27, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X8, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X12, X10, X8, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MUL X8, X13, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MADD X9, X10, X0, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MUL X14, X13, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X15, X12, X8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X12, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CSEL X16, X9, X14, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X8, X12, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GE 49bd78 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X22, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X11, X22, X11, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X10, X22, X10, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X11, X15, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, #14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 49bd54 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X12, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X9, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X9, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X13, X10, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.CC 49bd54 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X12, X11, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVI V0.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X13, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X14, X11, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD V0.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
CMP X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADDP D0, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV X13, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B.NE 49bd60 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49bd78 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
LDR W25, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4fed7c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X19, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X15, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410070 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X22, 49bddc <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 49bddc <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X8], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <4feddc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3792	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410070 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X22, 49be14 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x1e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X24, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X23, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X30, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 49be2c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49c65c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0xa2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X23, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X30, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 49c65c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0xa2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X26, X19, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVN X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR XZR, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X28, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X3, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X26, X21, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X4, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X4, X3, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 49bf10 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14–	0.18	0.08
○Loop 3450 - IJMatrix_parcsr.c:3274-3275 - exec	0.00	0.00
▼Loop 3443 - IJMatrix_parcsr.c:3291-3484 - exec–	0.00	0.00
▼Loop 3442 - IJMatrix_parcsr.c:3291-3484 - exec–	0.00	0.00
○Loop 3440 - IJMatrix_parcsr.c:3367-3367 - exec	0.00	0.00
○Loop 3446 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
▼Loop 3441 - IJMatrix_parcsr.c:3291-3484 - exec–	0.00	0.00
▼Loop 3433 - IJMatrix_parcsr.c:3291-3484 - exec–	0.03	0.01
▼Loop 3437 - IJMatrix_parcsr.c:3383-3454 - exec–	0.13	0.05
○Loop 3439 - IJMatrix_parcsr.c:3388-3390 - exec	0.00	0.00
○Loop 3438 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 3432 - IJMatrix_parcsr.c:3291-3467 - exec	0.01	0.01
▼Loop 3434 - IJMatrix_parcsr.c:3470-3484 - exec–	0.00	0.00
▼Loop 3435 - IJMatrix_parcsr.c:3475-3484 - exec–	0.00	0.00
○Loop 3436 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
○Loop 3445 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3447 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3444 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
○Loop 3449 - IJMatrix_parcsr.c:3274-3275 - exec	0.00	0.00
○Loop 3448 - IJMatrix_parcsr.c:3282-3283 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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Front-end bottlenecks

ASM code