OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace.omp

	Function: hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14	Module: exec	Source: csr_matvec.c:243-404 [...]	Coverage (incl. loops): 16.13% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 243 - 404

--------------------------------------------------------------------------------

243: #pragma omp parallel private(i,jj,tempx)

244: #endif

245:       {

246:       HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

247:       HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

248:       hypre_assert(iBegin <= iEnd);

249:       hypre_assert(iBegin >= 0 && iBegin <= num_rows);

250:       hypre_assert(iEnd >= 0 && iEnd <= num_rows);

251:

252:       if (0 == temp)

253:       {

254:          if (1 == alpha) // JSP: a common path

255:          {

256:             for (i = iBegin; i < iEnd; i++)

257:             {

258:                tempx = 0.0;

259:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

260:                {

261:                   tempx += A_data[jj] * x_data[A_j[jj]];

262:                }

263:                y_data[i] = tempx;

264:             }

265:          } // y = A*x

266:          else if (-1 == alpha)

267:          {

268:             for (i = iBegin; i < iEnd; i++)

269:             {

270:                tempx = 0.0;

271:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

272:                {

273:                   tempx -= A_data[jj] * x_data[A_j[jj]];

274:                }

275:                y_data[i] = tempx;

276:             }

277:          } // y = -A*x

278:          else

279:          {

280:             for (i = iBegin; i < iEnd; i++)

281:             {

282:                tempx = 0.0;

283:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

284:                {

285:                   tempx += A_data[jj] * x_data[A_j[jj]];

286:                }

287:                y_data[i] = alpha*tempx;

288:             }

289:          } // y = alpha*A*x

290:       } // temp == 0

291:       else if (-1 == temp) // beta == -alpha

292:       {

293:          if (1 == alpha) // JSP: a common path

294:          {

295:             for (i = iBegin; i < iEnd; i++)

296:             {

297:                tempx = -b_data[i];

298:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

299:                {

300:                   tempx += A_data[jj] * x_data[A_j[jj]];

301:                }

302:                y_data[i] = tempx;

303:             }

304:          } // y = A*x - y

305:          else if (-1 == alpha) // JSP: a common path

306:          {

307:             for (i = iBegin; i < iEnd; i++)

308:             {

309:                tempx = b_data[i];

310:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

311:                {

312:                   tempx -= A_data[jj] * x_data[A_j[jj]];

313:                }

314:                y_data[i] = tempx;

315:             }

316:          } // y = -A*x + y

317:          else

318:          {

319:             for (i = iBegin; i < iEnd; i++)

320:             {

321:                tempx = -b_data[i];

322:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

323:                {

324:                   tempx += A_data[jj] * x_data[A_j[jj]];

325:                }

326:                y_data[i] = alpha*tempx;

327:             }

328:          } // y = alpha*(A*x - y)

329:       } // temp == -1

330:       else if (1 == temp)

331:       {

332:          if (1 == alpha) // JSP: a common path

333:          {

334:             for (i = iBegin; i < iEnd; i++)

335:             {

336:                tempx = b_data[i];

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

340:                }

341:                y_data[i] = tempx;

342:             }

343:          } // y = A*x + y

344:          else if (-1 == alpha)

345:          {

346:             for (i = iBegin; i < iEnd; i++)

347:             {

348:                tempx = -b_data[i];

349:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

350:                {

351:                   tempx -= A_data[jj] * x_data[A_j[jj]];

352:                }

353:                y_data[i] = tempx;

354:             }

355:          } // y = -A*x - y

356:          else

357:          {

358:             for (i = iBegin; i < iEnd; i++)

359:             {

360:                tempx = b_data[i];

361:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

362:                {

363:                   tempx += A_data[jj] * x_data[A_j[jj]];

364:                }

365:                y_data[i] = alpha*tempx;

[...]

371:          if (1 == alpha) // JSP: a common path

372:          {

373:             for (i = iBegin; i < iEnd; i++)

374:             {

375:                tempx = b_data[i]*temp;

376:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

377:                {

378:                   tempx += A_data[jj] * x_data[A_j[jj]];

379:                }

380:                y_data[i] = tempx;

381:             }

382:          } // y = A*x + temp*y

383:          else if (-1 == alpha)

384:          {

385:             for (i = iBegin; i < iEnd; i++)

386:             {

387:                tempx = -b_data[i]*temp;

388:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

389:                {

390:                   tempx -= A_data[jj] * x_data[A_j[jj]];

391:                }

392:                y_data[i] = tempx;

393:             }

394:          } // y = -A*x - temp*y

395:          else

396:          {

397:             for (i = iBegin; i < iEnd; i++)

398:             {

399:                tempx = b_data[i]*temp;

400:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

401:                {

402:                   tempx += A_data[jj] * x_data[A_j[jj]];

403:                }

404:                y_data[i] = alpha*tempx;

0x4a43d0 STP	X29, X30, [SP, #928]!

0x4a43d4 STP	X28, X27, [SP, #16]

0x4a43d8 STP	X26, X25, [SP, #32]

0x4a43dc STP	X24, X23, [SP, #48]

0x4a43e0 STP	X22, X21, [SP, #64]

0x4a43e4 STP	X20, X19, [SP, #80]

0x4a43e8 ADD	X29, SP, #0

0x4a43ec LDR	X0, [X2]

0x4a43f0 ORR	X23, XZR, X7

0x4a43f4 ORR	X24, XZR, X6

0x4a43f8 ORR	X21, XZR, X5

0x4a43fc ORR	X22, XZR, X4

0x4a4400 ORR	X25, XZR, X3

0x4a4404 ORR	X19, XZR, X2

0x4a4408 BL	4a30f0

0x4a440c ORR	X20, XZR, X0

0x4a4410 LDR	X0, [X19]

0x4a4414 BL	4a3180

0x4a4418 ADRP	X28,

0x4a441c CMP	X20, X0

0x4a4420 ORR	X19, XZR, X0

0x4a4424 LDR	X28, [X28, #3824]

0x4a4428 B.LE	4a445c

0x4a442c LDR	X0, [X28]

0x4a4430 ADRP	X1,

0x4a4434 ADD	X1, X1, #422

0x4a4438 ADRP	X2,

0x4a443c ADD	X2, X2, #2936

0x4a4440 BL	4ac770

0x4a4444 ADRP	X0,

0x4a4448 ADD	X0, X0, #3378

0x4a444c MOVZ	W1, #248

0x4a4450 MOVZ	W2, #1

0x4a4454 ORR	X3, XZR, XZR

0x4a4458 BL	4aeb20

0x4a445c TBNZ	X20, #63, 4a446c

0x4a4460 LDR	X8, [X25]

0x4a4464 CMP	X20, X8

0x4a4468 B.LE	4a44a0

0x4a446c LDR	X0, [X28]

0x4a4470 ADRP	X1,

0x4a4474 ADD	X1, X1, #422

0x4a4478 ADRP	X2,

0x4a447c ADD	X2, X2, #3505

0x4a4480 BL	4ac770

0x4a4484 ADRP	X0,

0x4a4488 ADD	X0, X0, #3378

0x4a448c MOVZ	W1, #249

0x4a4490 MOVZ	W2, #1

0x4a4494 ORR	X3, XZR, XZR

0x4a4498 BL	4aeb20

0x4a449c LDR	X8, [X25]

0x4a44a0 LDP	X26, X25, [X29, #104]

0x4a44a4 LDR	X27, [X29, #96]

0x4a44a8 TBNZ	X19, #63, 4a461c

0x4a44ac CMP	X19, X8

0x4a44b0 B.GT	4a461c

0x4a44b4 LDR	D1, [X22]

0x4a44b8 FCMP	D1, #0

0x4a44bc B.NE	4a4658

0x4a44c0 LDR	D0, [X21]

0x4a44c4 FMOV	D1, #1.0000000

0x4a44c8 FCMP	D0, D1

0x4a44cc B.NE	4a47dc

0x4a44d0 CMP	X20, X19

0x4a44d4 B.GE	4a55bc

0x4a44d8 LDR	X8, [X24]

0x4a44dc LDR	X9, [X23]

0x4a44e0 LDR	X11, [X26]

0x4a44e4 ADD	X13, X11, #8

0x4a44e8 LDR	X10, [X27]

0x4a44ec LDR	X12, [X25]

0x4a44f0 LDR	X14, [X8, X20,LSL #3]

0x4a44f4 ADD	X15, X9, #8

0x4a44f8 ADD	X16, X11, #16

0x4a44fc ADD	X17, X9, #16

0x4a4500 B	4a4514

  (3680) 0x4a4504 CMP	X18, X19

  (3680) 0x4a4508 STR	D0, [X12, X20,LSL #3]

  (3680) 0x4a450c ORR	X20, XZR, X18

  (3680) 0x4a4510 B.EQ	4a55bc

  (3680) 0x4a4514 ADD	X18, X20, #1

  (3680) 0x4a4518 ORR	X4, XZR, X14

  (3680) 0x4a451c MOVI	D0, #0

  (3680) 0x4a4520 LDR	X14, [X8, X18,LSL #3]

  (3680) 0x4a4524 SUBS	X1, X14, X4

  (3680) 0x4a4528 B.LE	4a4504

  (3680) 0x4a452c CMP	X1, #2

  (3680) 0x4a4530 B.CS	4a4540

  (3680) 0x4a4534 ORR	X0, XZR, X4

  (3680) 0x4a4538 B	4a4594

0x4a453c HINT	#0

(3681) 0x4a4540 AND	X2, X1, #0xfffffffe

(3681) 0x4a4544 MOVI	D1, #0

(3681) 0x4a4548 ADD	X3, X13, X4,LSL #3

(3681) 0x4a454c AND	X5, X1, #0xfffffffe

(3681) 0x4a4550 ADD	X0, X4, X2

(3681) 0x4a4554 ADD	X4, X15, X4,LSL #3

(3681) 0x4a4558 HINT	#0

(3681) 0x4a455c HINT	#0

  (3679) 0x4a4560 LDP	X6, X7, [X3, #1016]

  (3679) 0x4a4564 LDP	D2, D3, [X4, #1016]

  (3679) 0x4a4568 SUBS	X5, X5, #2

  (3679) 0x4a456c ADD	X3, X3, #16

  (3679) 0x4a4570 ADD	X4, X4, #16

  (3679) 0x4a4574 LDR	D4, [X10, X6,LSL #3]

  (3679) 0x4a4578 LDR	D5, [X10, X7,LSL #3]

  (3679) 0x4a457c FMADD	D0, D4, D2, D0

  (3679) 0x4a4580 FMADD	D1, D5, D3, D1

  (3679) 0x4a4584 B.NE	4a4560

(3681) 0x4a4588 FADD	D0, D1, D0

(3681) 0x4a458c CMP	X1, X2

(3681) 0x4a4590 B.EQ	4a4504

  (3680) 0x4a4594 SUB	W1, W14, W0

  (3680) 0x4a4598 ORR	X2, XZR, X0

  (3680) 0x4a459c ANDS	X1, X1, #0x3

  (3680) 0x4a45a0 B.EQ	4a45c0

    (3683) 0x4a45a4 LDR	X3, [X11, X2,LSL #3]

    (3683) 0x4a45a8 LDR	D1, [X9, X2,LSL #3]

    (3683) 0x4a45ac ADD	X2, X2, #1

    (3683) 0x4a45b0 SUBS	X1, X1, #1

    (3683) 0x4a45b4 LDR	D2, [X10, X3,LSL #3]

    (3683) 0x4a45b8 FMADD	D0, D2, D1, D0

    (3683) 0x4a45bc B.NE	4a45a4

  (3680) 0x4a45c0 SUB	X0, X0, X14

  (3680) 0x4a45c4 CMN	X0, #4

  (3680) 0x4a45c8 B.HI	4a4504

  (3680) 0x4a45cc SUB	X0, X14, X2

  (3680) 0x4a45d0 ADD	X1, X16, X2,LSL #3

  (3680) 0x4a45d4 ADD	X2, X17, X2,LSL #3

  (3680) 0x4a45d8 HINT	#0

  (3680) 0x4a45dc HINT	#0

    (3682) 0x4a45e0 LDP	X3, X4, [X1, #1008]

    (3682) 0x4a45e4 LDP	D2, D3, [X2, #1008]

    (3682) 0x4a45e8 SUBS	X0, X0, #4

    (3682) 0x4a45ec LDR	D1, [X10, X3,LSL #3]

    (3682) 0x4a45f0 FMADD	D0, D1, D2, D0

    (3682) 0x4a45f4 LDR	D1, [X10, X4,LSL #3]

    (3682) 0x4a45f8 FMADD	D0, D1, D3, D0

    (3682) 0x4a45fc LDP	X3, X4, [X1], #32

    (3682) 0x4a4600 LDR	D2, [X10, X3,LSL #3]

    (3682) 0x4a4604 LDP	D1, D3, [X2], #32

    (3682) 0x4a4608 FMADD	D0, D2, D1, D0

    (3682) 0x4a460c LDR	D1, [X10, X4,LSL #3]

    (3682) 0x4a4610 FMADD	D0, D1, D3, D0

    (3682) 0x4a4614 B.NE	4a45e0

  (3680) 0x4a4618 B	4a4504

0x4a461c LDR	X0, [X28]

0x4a4620 ADRP	X1,

0x4a4624 ADD	X1, X1, #422

0x4a4628 ADRP	X2,

0x4a462c ADD	X2, X2, #3539

0x4a4630 BL	4ac770

0x4a4634 ADRP	X0,

0x4a4638 ADD	X0, X0, #3378

0x4a463c MOVZ	W1, #250

0x4a4640 MOVZ	W2, #1

0x4a4644 ORR	X3, XZR, XZR

0x4a4648 BL	4aeb20

0x4a464c LDR	D1, [X22]

0x4a4650 FCMP	D1, #0

0x4a4654 B.EQ	4a44c0

0x4a4658 LDR	X8, [X29, #120]

0x4a465c FMOV	D0, #-1.0000000

0x4a4660 FCMP	D1, D0

0x4a4664 B.NE	4a4940

0x4a4668 LDR	D0, [X21]

0x4a466c FMOV	D1, #1.0000000

0x4a4670 FCMP	D0, D1

0x4a4674 B.NE	4a4abc

0x4a4678 CMP	X20, X19

0x4a467c B.GE	4a55bc

0x4a4680 LDR	X9, [X24]

0x4a4684 LDR	X10, [X23]

0x4a4688 LDR	X12, [X26]

0x4a468c ADD	X14, X12, #8

0x4a4690 LDR	X8, [X8]

0x4a4694 LDR	X11, [X27]

0x4a4698 LDR	X13, [X25]

0x4a469c LDR	X17, [X9, X20,LSL #3]

0x4a46a0 ADD	X15, X10, #8

0x4a46a4 ADD	X16, X12, #16

0x4a46a8 ADD	X18, X10, #16

0x4a46ac B	4a46d0

0x4a46b0 HINT	#0

0x4a46b4 HINT	#0

0x4a46b8 HINT	#0

0x4a46bc HINT	#0

  (3675) 0x4a46c0 CMP	X0, X19

  (3675) 0x4a46c4 STR	D0, [X13, X20,LSL #3]

  (3675) 0x4a46c8 ORR	X20, XZR, X0

  (3675) 0x4a46cc B.EQ	4a55bc

  (3675) 0x4a46d0 LDR	D0, [X8, X20,LSL #3]

  (3675) 0x4a46d4 ADD	X0, X20, #1

  (3675) 0x4a46d8 ORR	X5, XZR, X17

  (3675) 0x4a46dc LDR	X17, [X9, X0,LSL #3]

  (3675) 0x4a46e0 SUBS	X2, X17, X5

  (3675) 0x4a46e4 FNEG	D0, D0

  (3675) 0x4a46e8 B.LE	4a46c0

  (3675) 0x4a46ec CMP	X2, #2

  (3675) 0x4a46f0 B.CS	4a4700

  (3675) 0x4a46f4 ORR	X1, XZR, X5

  (3675) 0x4a46f8 B	4a4754

0x4a46fc HINT	#0

(3676) 0x4a4700 AND	X3, X2, #0xfffffffe

(3676) 0x4a4704 MOVI	D1, #0

(3676) 0x4a4708 ADD	X4, X14, X5,LSL #3

(3676) 0x4a470c AND	X6, X2, #0xfffffffe

(3676) 0x4a4710 ADD	X1, X5, X3

(3676) 0x4a4714 ADD	X5, X15, X5,LSL #3

(3676) 0x4a4718 HINT	#0

(3676) 0x4a471c HINT	#0

  (3674) 0x4a4720 LDP	X7, X21, [X4, #1016]

  (3674) 0x4a4724 LDP	D2, D3, [X5, #1016]

  (3674) 0x4a4728 SUBS	X6, X6, #2

  (3674) 0x4a472c ADD	X4, X4, #16

  (3674) 0x4a4730 ADD	X5, X5, #16

  (3674) 0x4a4734 LDR	D4, [X11, X7,LSL #3]

  (3674) 0x4a4738 LDR	D5, [X11, X21,LSL #3]

  (3674) 0x4a473c FMADD	D0, D4, D2, D0

  (3674) 0x4a4740 FMADD	D1, D5, D3, D1

  (3674) 0x4a4744 B.NE	4a4720

(3676) 0x4a4748 FADD	D0, D1, D0

(3676) 0x4a474c CMP	X2, X3

(3676) 0x4a4750 B.EQ	4a46c0

  (3675) 0x4a4754 SUB	W2, W17, W1

  (3675) 0x4a4758 ORR	X3, XZR, X1

  (3675) 0x4a475c ANDS	X2, X2, #0x3

  (3675) 0x4a4760 B.EQ	4a4780

    (3678) 0x4a4764 LDR	X4, [X12, X3,LSL #3]

    (3678) 0x4a4768 LDR	D1, [X10, X3,LSL #3]

    (3678) 0x4a476c ADD	X3, X3, #1

    (3678) 0x4a4770 SUBS	X2, X2, #1

    (3678) 0x4a4774 LDR	D2, [X11, X4,LSL #3]

    (3678) 0x4a4778 FMADD	D0, D2, D1, D0

    (3678) 0x4a477c B.NE	4a4764

  (3675) 0x4a4780 SUB	X1, X1, X17

  (3675) 0x4a4784 CMN	X1, #4

  (3675) 0x4a4788 B.HI	4a46c0

  (3675) 0x4a478c SUB	X1, X17, X3

  (3675) 0x4a4790 ADD	X2, X16, X3,LSL #3

  (3675) 0x4a4794 ADD	X3, X18, X3,LSL #3

  (3675) 0x4a4798 HINT	#0

  (3675) 0x4a479c HINT	#0

    (3677) 0x4a47a0 LDP	X4, X5, [X2, #1008]

    (3677) 0x4a47a4 LDP	D2, D3, [X3, #1008]

    (3677) 0x4a47a8 SUBS	X1, X1, #4

    (3677) 0x4a47ac LDR	D1, [X11, X4,LSL #3]

    (3677) 0x4a47b0 FMADD	D0, D1, D2, D0

    (3677) 0x4a47b4 LDR	D1, [X11, X5,LSL #3]

    (3677) 0x4a47b8 FMADD	D0, D1, D3, D0

    (3677) 0x4a47bc LDP	X4, X5, [X2], #32

    (3677) 0x4a47c0 LDR	D2, [X11, X4,LSL #3]

    (3677) 0x4a47c4 LDP	D1, D3, [X3], #32

    (3677) 0x4a47c8 FMADD	D0, D2, D1, D0

    (3677) 0x4a47cc LDR	D1, [X11, X5,LSL #3]

    (3677) 0x4a47d0 FMADD	D0, D1, D3, D0

    (3677) 0x4a47d4 B.NE	4a47a0

  (3675) 0x4a47d8 B	4a46c0

0x4a47dc FMOV	D1, #-1.0000000

0x4a47e0 FCMP	D0, D1

0x4a47e4 B.NE	4a4c20

0x4a47e8 CMP	X20, X19

0x4a47ec B.GE	4a55bc

0x4a47f0 LDR	X8, [X24]

0x4a47f4 LDR	X9, [X23]

0x4a47f8 LDR	X11, [X26]

0x4a47fc ADD	X13, X11, #8

0x4a4800 LDR	X10, [X27]

0x4a4804 LDR	X12, [X25]

0x4a4808 LDR	X14, [X8, X20,LSL #3]

0x4a480c ADD	X15, X9, #8

0x4a4810 ADD	X16, X11, #16

0x4a4814 ADD	X17, X9, #16

0x4a4818 B	4a4830

0x4a481c HINT	#0

  (3670) 0x4a4820 CMP	X18, X19

  (3670) 0x4a4824 STR	D0, [X12, X20,LSL #3]

  (3670) 0x4a4828 ORR	X20, XZR, X18

  (3670) 0x4a482c B.EQ	4a55bc

  (3670) 0x4a4830 ADD	X18, X20, #1

  (3670) 0x4a4834 ORR	X4, XZR, X14

  (3670) 0x4a4838 MOVI	D0, #0

  (3670) 0x4a483c LDR	X14, [X8, X18,LSL #3]

  (3670) 0x4a4840 SUBS	X1, X14, X4

  (3670) 0x4a4844 B.LE	4a4820

  (3670) 0x4a4848 CMP	X1, #2

  (3670) 0x4a484c B.CS	4a4860

  (3670) 0x4a4850 ORR	X0, XZR, X4

  (3670) 0x4a4854 B	4a48b4

0x4a4858 HINT	#0

0x4a485c HINT	#0

(3671) 0x4a4860 AND	X2, X1, #0xfffffffe

(3671) 0x4a4864 MOVI	D1, #0

(3671) 0x4a4868 ADD	X3, X13, X4,LSL #3

(3671) 0x4a486c AND	X5, X1, #0xfffffffe

(3671) 0x4a4870 ADD	X0, X4, X2

(3671) 0x4a4874 ADD	X4, X15, X4,LSL #3

(3671) 0x4a4878 HINT	#0

(3671) 0x4a487c HINT	#0

  (3669) 0x4a4880 LDP	X6, X7, [X3, #1016]

  (3669) 0x4a4884 LDP	D2, D3, [X4, #1016]

  (3669) 0x4a4888 SUBS	X5, X5, #2

  (3669) 0x4a488c ADD	X3, X3, #16

  (3669) 0x4a4890 ADD	X4, X4, #16

  (3669) 0x4a4894 LDR	D4, [X10, X6,LSL #3]

  (3669) 0x4a4898 LDR	D5, [X10, X7,LSL #3]

  (3669) 0x4a489c FMSUB	D0, D4, D2, D0

  (3669) 0x4a48a0 FMSUB	D1, D5, D3, D1

  (3669) 0x4a48a4 B.NE	4a4880

(3671) 0x4a48a8 FADD	D0, D1, D0

(3671) 0x4a48ac CMP	X1, X2

(3671) 0x4a48b0 B.EQ	4a4820

  (3670) 0x4a48b4 SUB	W1, W14, W0

  (3670) 0x4a48b8 ORR	X2, XZR, X0

  (3670) 0x4a48bc ANDS	X1, X1, #0x3

  (3670) 0x4a48c0 B.EQ	4a48e0

    (3673) 0x4a48c4 LDR	X3, [X11, X2,LSL #3]

    (3673) 0x4a48c8 LDR	D1, [X9, X2,LSL #3]

    (3673) 0x4a48cc ADD	X2, X2, #1

    (3673) 0x4a48d0 SUBS	X1, X1, #1

    (3673) 0x4a48d4 LDR	D2, [X10, X3,LSL #3]

    (3673) 0x4a48d8 FMSUB	D0, D2, D1, D0

    (3673) 0x4a48dc B.NE	4a48c4

  (3670) 0x4a48e0 SUB	X0, X0, X14

  (3670) 0x4a48e4 CMN	X0, #4

  (3670) 0x4a48e8 B.HI	4a4820

  (3670) 0x4a48ec SUB	X0, X14, X2

  (3670) 0x4a48f0 ADD	X1, X16, X2,LSL #3

  (3670) 0x4a48f4 ADD	X2, X17, X2,LSL #3

  (3670) 0x4a48f8 HINT	#0

  (3670) 0x4a48fc HINT	#0

    (3672) 0x4a4900 LDP	X3, X4, [X1, #1008]

    (3672) 0x4a4904 LDP	D2, D3, [X2, #1008]

    (3672) 0x4a4908 SUBS	X0, X0, #4

    (3672) 0x4a490c LDR	D4, [X10, X4,LSL #3]

    (3672) 0x4a4910 LDR	D1, [X10, X3,LSL #3]

    (3672) 0x4a4914 FMUL	D3, D4, D3

    (3672) 0x4a4918 FMADD	D1, D1, D2, D3

    (3672) 0x4a491c LDP	X3, X4, [X1], #32

    (3672) 0x4a4920 LDR	D4, [X10, X3,LSL #3]

    (3672) 0x4a4924 LDP	D2, D3, [X2], #32

    (3672) 0x4a4928 FMADD	D1, D4, D2, D1

    (3672) 0x4a492c LDR	D2, [X10, X4,LSL #3]

    (3672) 0x4a4930 FMADD	D1, D2, D3, D1

    (3672) 0x4a4934 FSUB	D0, D0, S1

    (3672) 0x4a4938 B.NE	4a4900

  (3670) 0x4a493c B	4a4820

0x4a4940 LDR	D0, [X21]

0x4a4944 FMOV	D2, #1.0000000

0x4a4948 FCMP	D1, D2

0x4a494c B.NE	4a4d7c

0x4a4950 FCMP	D0, D2

0x4a4954 B.NE	4a4edc

0x4a4958 CMP	X20, X19

0x4a495c B.GE	4a55bc

0x4a4960 LDR	X9, [X24]

0x4a4964 LDR	X10, [X23]

0x4a4968 LDR	X12, [X26]

0x4a496c ADD	X14, X12, #8

0x4a4970 LDR	X8, [X8]

0x4a4974 LDR	X11, [X27]

0x4a4978 LDR	X13, [X25]

0x4a497c LDR	X16, [X9, X20,LSL #3]

0x4a4980 ADD	X15, X10, #8

0x4a4984 ADD	X17, X12, #16

0x4a4988 ADD	X18, X10, #16

0x4a498c B	4a49b0

0x4a4990 HINT	#0

0x4a4994 HINT	#0

0x4a4998 HINT	#0

0x4a499c HINT	#0

  (3665) 0x4a49a0 CMP	X0, X19

  (3665) 0x4a49a4 STR	D0, [X13, X20,LSL #3]

  (3665) 0x4a49a8 ORR	X20, XZR, X0

  (3665) 0x4a49ac B.EQ	4a55bc

  (3665) 0x4a49b0 LDR	D0, [X8, X20,LSL #3]

  (3665) 0x4a49b4 ADD	X0, X20, #1

  (3665) 0x4a49b8 ORR	X5, XZR, X16

  (3665) 0x4a49bc LDR	X16, [X9, X0,LSL #3]

  (3665) 0x4a49c0 SUBS	X2, X16, X5

  (3665) 0x4a49c4 B.LE	4a49a0

  (3665) 0x4a49c8 CMP	X2, #2

  (3665) 0x4a49cc B.CS	4a49e0

  (3665) 0x4a49d0 ORR	X1, XZR, X5

  (3665) 0x4a49d4 B	4a4a34

0x4a49d8 HINT	#0

0x4a49dc HINT	#0

(3666) 0x4a49e0 AND	X3, X2, #0xfffffffe

(3666) 0x4a49e4 MOVI	D1, #0

(3666) 0x4a49e8 ADD	X4, X14, X5,LSL #3

(3666) 0x4a49ec AND	X6, X2, #0xfffffffe

(3666) 0x4a49f0 ADD	X1, X5, X3

(3666) 0x4a49f4 ADD	X5, X15, X5,LSL #3

(3666) 0x4a49f8 HINT	#0

(3666) 0x4a49fc HINT	#0

  (3664) 0x4a4a00 LDP	X7, X21, [X4, #1016]

  (3664) 0x4a4a04 LDP	D2, D3, [X5, #1016]

  (3664) 0x4a4a08 SUBS	X6, X6, #2

  (3664) 0x4a4a0c ADD	X4, X4, #16

  (3664) 0x4a4a10 ADD	X5, X5, #16

  (3664) 0x4a4a14 LDR	D4, [X11, X7,LSL #3]

  (3664) 0x4a4a18 LDR	D5, [X11, X21,LSL #3]

  (3664) 0x4a4a1c FMADD	D0, D4, D2, D0

  (3664) 0x4a4a20 FMADD	D1, D5, D3, D1

  (3664) 0x4a4a24 B.NE	4a4a00

(3666) 0x4a4a28 FADD	D0, D1, D0

(3666) 0x4a4a2c CMP	X2, X3

(3666) 0x4a4a30 B.EQ	4a49a0

  (3665) 0x4a4a34 SUB	W2, W16, W1

  (3665) 0x4a4a38 ORR	X3, XZR, X1

  (3665) 0x4a4a3c ANDS	X2, X2, #0x3

  (3665) 0x4a4a40 B.EQ	4a4a60

    (3668) 0x4a4a44 LDR	X4, [X12, X3,LSL #3]

    (3668) 0x4a4a48 LDR	D1, [X10, X3,LSL #3]

    (3668) 0x4a4a4c ADD	X3, X3, #1

    (3668) 0x4a4a50 SUBS	X2, X2, #1

    (3668) 0x4a4a54 LDR	D2, [X11, X4,LSL #3]

    (3668) 0x4a4a58 FMADD	D0, D2, D1, D0

    (3668) 0x4a4a5c B.NE	4a4a44

  (3665) 0x4a4a60 SUB	X1, X1, X16

  (3665) 0x4a4a64 CMN	X1, #4

  (3665) 0x4a4a68 B.HI	4a49a0

  (3665) 0x4a4a6c SUB	X1, X16, X3

  (3665) 0x4a4a70 ADD	X2, X17, X3,LSL #3

  (3665) 0x4a4a74 ADD	X3, X18, X3,LSL #3

  (3665) 0x4a4a78 HINT	#0

  (3665) 0x4a4a7c HINT	#0

    (3667) 0x4a4a80 LDP	X4, X5, [X2, #1008]

    (3667) 0x4a4a84 LDP	D2, D3, [X3, #1008]

    (3667) 0x4a4a88 SUBS	X1, X1, #4

    (3667) 0x4a4a8c LDR	D1, [X11, X4,LSL #3]

    (3667) 0x4a4a90 FMADD	D0, D1, D2, D0

    (3667) 0x4a4a94 LDR	D1, [X11, X5,LSL #3]

    (3667) 0x4a4a98 FMADD	D0, D1, D3, D0

    (3667) 0x4a4a9c LDP	X4, X5, [X2], #32

    (3667) 0x4a4aa0 LDR	D2, [X11, X4,LSL #3]

    (3667) 0x4a4aa4 LDP	D1, D3, [X3], #32

    (3667) 0x4a4aa8 FMADD	D0, D2, D1, D0

    (3667) 0x4a4aac LDR	D1, [X11, X5,LSL #3]

    (3667) 0x4a4ab0 FMADD	D0, D1, D3, D0

    (3667) 0x4a4ab4 B.NE	4a4a80

  (3665) 0x4a4ab8 B	4a49a0

0x4a4abc FMOV	D1, #-1.0000000

0x4a4ac0 FCMP	D0, D1

0x4a4ac4 B.NE	4a5040

0x4a4ac8 CMP	X20, X19

0x4a4acc B.GE	4a55bc

0x4a4ad0 LDR	X9, [X24]

0x4a4ad4 LDR	X10, [X23]

0x4a4ad8 LDR	X12, [X26]

0x4a4adc ADD	X14, X12, #8

0x4a4ae0 LDR	X8, [X8]

0x4a4ae4 LDR	X11, [X27]

0x4a4ae8 LDR	X13, [X25]

0x4a4aec LDR	X16, [X9, X20,LSL #3]

0x4a4af0 ADD	X15, X10, #8

0x4a4af4 ADD	X17, X12, #16

0x4a4af8 ADD	X18, X10, #16

0x4a4afc B	4a4b10

  (3660) 0x4a4b00 CMP	X0, X19

  (3660) 0x4a4b04 STR	D0, [X13, X20,LSL #3]

  (3660) 0x4a4b08 ORR	X20, XZR, X0

  (3660) 0x4a4b0c B.EQ	4a55bc

  (3660) 0x4a4b10 LDR	D0, [X8, X20,LSL #3]

  (3660) 0x4a4b14 ADD	X0, X20, #1

  (3660) 0x4a4b18 ORR	X5, XZR, X16

  (3660) 0x4a4b1c LDR	X16, [X9, X0,LSL #3]

  (3660) 0x4a4b20 SUBS	X2, X16, X5

  (3660) 0x4a4b24 B.LE	4a4b00

  (3660) 0x4a4b28 CMP	X2, #2

  (3660) 0x4a4b2c B.CS	4a4b40

  (3660) 0x4a4b30 ORR	X1, XZR, X5

  (3660) 0x4a4b34 B	4a4b94

0x4a4b38 HINT	#0

0x4a4b3c HINT	#0

(3661) 0x4a4b40 AND	X3, X2, #0xfffffffe

(3661) 0x4a4b44 MOVI	D1, #0

(3661) 0x4a4b48 ADD	X4, X14, X5,LSL #3

(3661) 0x4a4b4c AND	X6, X2, #0xfffffffe

(3661) 0x4a4b50 ADD	X1, X5, X3

(3661) 0x4a4b54 ADD	X5, X15, X5,LSL #3

(3661) 0x4a4b58 HINT	#0

(3661) 0x4a4b5c HINT	#0

  (3659) 0x4a4b60 LDP	X7, X21, [X4, #1016]

  (3659) 0x4a4b64 LDP	D2, D3, [X5, #1016]

  (3659) 0x4a4b68 SUBS	X6, X6, #2

  (3659) 0x4a4b6c ADD	X4, X4, #16

  (3659) 0x4a4b70 ADD	X5, X5, #16

  (3659) 0x4a4b74 LDR	D4, [X11, X7,LSL #3]

  (3659) 0x4a4b78 LDR	D5, [X11, X21,LSL #3]

  (3659) 0x4a4b7c FMSUB	D0, D4, D2, D0

  (3659) 0x4a4b80 FMSUB	D1, D5, D3, D1

  (3659) 0x4a4b84 B.NE	4a4b60

(3661) 0x4a4b88 FADD	D0, D1, D0

(3661) 0x4a4b8c CMP	X2, X3

(3661) 0x4a4b90 B.EQ	4a4b00

  (3660) 0x4a4b94 SUB	W2, W16, W1

  (3660) 0x4a4b98 ORR	X3, XZR, X1

  (3660) 0x4a4b9c ANDS	X2, X2, #0x3

  (3660) 0x4a4ba0 B.EQ	4a4bc0

    (3663) 0x4a4ba4 LDR	X4, [X12, X3,LSL #3]

    (3663) 0x4a4ba8 LDR	D1, [X10, X3,LSL #3]

    (3663) 0x4a4bac ADD	X3, X3, #1

    (3663) 0x4a4bb0 SUBS	X2, X2, #1

    (3663) 0x4a4bb4 LDR	D2, [X11, X4,LSL #3]

    (3663) 0x4a4bb8 FMSUB	D0, D2, D1, D0

    (3663) 0x4a4bbc B.NE	4a4ba4

  (3660) 0x4a4bc0 SUB	X1, X1, X16

  (3660) 0x4a4bc4 CMN	X1, #4

  (3660) 0x4a4bc8 B.HI	4a4b00

  (3660) 0x4a4bcc SUB	X1, X16, X3

  (3660) 0x4a4bd0 ADD	X2, X17, X3,LSL #3

  (3660) 0x4a4bd4 ADD	X3, X18, X3,LSL #3

  (3660) 0x4a4bd8 HINT	#0

  (3660) 0x4a4bdc HINT	#0

    (3662) 0x4a4be0 LDP	X4, X5, [X2, #1008]

    (3662) 0x4a4be4 LDP	D2, D3, [X3, #1008]

    (3662) 0x4a4be8 SUBS	X1, X1, #4

    (3662) 0x4a4bec LDR	D4, [X11, X5,LSL #3]

    (3662) 0x4a4bf0 LDR	D1, [X11, X4,LSL #3]

    (3662) 0x4a4bf4 FMUL	D3, D4, D3

    (3662) 0x4a4bf8 FMADD	D1, D1, D2, D3

    (3662) 0x4a4bfc LDP	X4, X5, [X2], #32

    (3662) 0x4a4c00 LDR	D4, [X11, X4,LSL #3]

    (3662) 0x4a4c04 LDP	D2, D3, [X3], #32

    (3662) 0x4a4c08 FMADD	D1, D4, D2, D1

    (3662) 0x4a4c0c LDR	D2, [X11, X5,LSL #3]

    (3662) 0x4a4c10 FMADD	D1, D2, D3, D1

    (3662) 0x4a4c14 FSUB	D0, D0, S1

    (3662) 0x4a4c18 B.NE	4a4be0

  (3660) 0x4a4c1c B	4a4b00

0x4a4c20 CMP	X20, X19

0x4a4c24 B.GE	4a55bc

0x4a4c28 LDR	X8, [X24]

0x4a4c2c LDR	X9, [X23]

0x4a4c30 LDR	X11, [X26]

0x4a4c34 ADD	X13, X11, #8

0x4a4c38 LDR	X10, [X27]

0x4a4c3c LDR	X12, [X25]

0x4a4c40 LDR	X14, [X8, X20,LSL #3]

0x4a4c44 ADD	X15, X9, #8

0x4a4c48 ADD	X16, X11, #16

0x4a4c4c ADD	X17, X9, #16

0x4a4c50 B	4a4c78

0x4a4c54 HINT	#0

0x4a4c58 HINT	#0

0x4a4c5c HINT	#0

(3655) 0x4a4c60 LDR	D1, [X21]

(3655) 0x4a4c64 CMP	X18, X19

(3655) 0x4a4c68 FMUL	D0, D1, D0

(3655) 0x4a4c6c STR	D0, [X12, X20,LSL #3]

(3655) 0x4a4c70 ORR	X20, XZR, X18

(3655) 0x4a4c74 B.EQ	4a55bc

(3655) 0x4a4c78 ADD	X18, X20, #1

(3655) 0x4a4c7c ORR	X4, XZR, X14

(3655) 0x4a4c80 MOVI	D0, #0

(3655) 0x4a4c84 LDR	X14, [X8, X18,LSL #3]

(3655) 0x4a4c88 SUBS	X1, X14, X4

(3655) 0x4a4c8c B.LE	4a4c60

(3655) 0x4a4c90 CMP	X1, #2

(3655) 0x4a4c94 B.CS	4a4ca0

(3655) 0x4a4c98 ORR	X0, XZR, X4

(3655) 0x4a4c9c B	4a4cf4

(3655) 0x4a4ca0 AND	X2, X1, #0xfffffffe

(3655) 0x4a4ca4 MOVI	D1, #0

(3655) 0x4a4ca8 ADD	X3, X13, X4,LSL #3

(3655) 0x4a4cac AND	X5, X1, #0xfffffffe

(3655) 0x4a4cb0 ADD	X0, X4, X2

(3655) 0x4a4cb4 ADD	X4, X15, X4,LSL #3

(3655) 0x4a4cb8 HINT	#0

(3655) 0x4a4cbc HINT	#0

  (3656) 0x4a4cc0 LDP	X6, X7, [X3, #1016]

  (3656) 0x4a4cc4 LDP	D2, D3, [X4, #1016]

  (3656) 0x4a4cc8 SUBS	X5, X5, #2

  (3656) 0x4a4ccc ADD	X3, X3, #16

  (3656) 0x4a4cd0 ADD	X4, X4, #16

  (3656) 0x4a4cd4 LDR	D4, [X10, X6,LSL #3]

  (3656) 0x4a4cd8 LDR	D5, [X10, X7,LSL #3]

  (3656) 0x4a4cdc FMADD	D0, D4, D2, D0

  (3656) 0x4a4ce0 FMADD	D1, D5, D3, D1

  (3656) 0x4a4ce4 B.NE	4a4cc0

(3655) 0x4a4ce8 FADD	D0, D1, D0

(3655) 0x4a4cec CMP	X1, X2

(3655) 0x4a4cf0 B.EQ	4a4c60

(3655) 0x4a4cf4 SUB	W1, W14, W0

(3655) 0x4a4cf8 ORR	X2, XZR, X0

(3655) 0x4a4cfc ANDS	X1, X1, #0x3

(3655) 0x4a4d00 B.EQ	4a4d20

  (3658) 0x4a4d04 LDR	X3, [X11, X2,LSL #3]

  (3658) 0x4a4d08 LDR	D1, [X9, X2,LSL #3]

  (3658) 0x4a4d0c ADD	X2, X2, #1

  (3658) 0x4a4d10 SUBS	X1, X1, #1

  (3658) 0x4a4d14 LDR	D2, [X10, X3,LSL #3]

  (3658) 0x4a4d18 FMADD	D0, D2, D1, D0

  (3658) 0x4a4d1c B.NE	4a4d04

(3655) 0x4a4d20 SUB	X0, X0, X14

(3655) 0x4a4d24 CMN	X0, #4

(3655) 0x4a4d28 B.HI	4a4c60

(3655) 0x4a4d2c SUB	X0, X14, X2

(3655) 0x4a4d30 ADD	X1, X16, X2,LSL #3

(3655) 0x4a4d34 ADD	X2, X17, X2,LSL #3

(3655) 0x4a4d38 HINT	#0

(3655) 0x4a4d3c HINT	#0

  (3657) 0x4a4d40 LDP	X3, X4, [X1, #1008]

  (3657) 0x4a4d44 LDP	D2, D3, [X2, #1008]

  (3657) 0x4a4d48 SUBS	X0, X0, #4

  (3657) 0x4a4d4c LDR	D1, [X10, X3,LSL #3]

  (3657) 0x4a4d50 FMADD	D0, D1, D2, D0

  (3657) 0x4a4d54 LDR	D1, [X10, X4,LSL #3]

  (3657) 0x4a4d58 FMADD	D0, D1, D3, D0

  (3657) 0x4a4d5c LDP	X3, X4, [X1], #32

  (3657) 0x4a4d60 LDR	D2, [X10, X3,LSL #3]

  (3657) 0x4a4d64 LDP	D1, D3, [X2], #32

  (3657) 0x4a4d68 FMADD	D0, D2, D1, D0

  (3657) 0x4a4d6c LDR	D1, [X10, X4,LSL #3]

  (3657) 0x4a4d70 FMADD	D0, D1, D3, D0

  (3657) 0x4a4d74 B.NE	4a4d40

(3655) 0x4a4d78 B	4a4c60

0x4a4d7c FCMP	D0, D2

0x4a4d80 B.NE	4a519c

0x4a4d84 CMP	X20, X19

0x4a4d88 B.GE	4a55bc

0x4a4d8c LDR	X9, [X24]

0x4a4d90 LDR	X10, [X23]

0x4a4d94 LDR	X12, [X26]

0x4a4d98 ADD	X14, X12, #8

0x4a4d9c LDR	X8, [X8]

0x4a4da0 LDR	X11, [X27]

0x4a4da4 LDR	X13, [X25]

0x4a4da8 LDR	X18, [X9, X20,LSL #3]

0x4a4dac ADD	X15, X10, #8

0x4a4db0 ADD	X16, X12, #16

0x4a4db4 ADD	X17, X10, #16

0x4a4db8 B	4a4dd0

0x4a4dbc HINT	#0

(3651) 0x4a4dc0 CMP	X0, X19

(3651) 0x4a4dc4 STR	D0, [X13, X20,LSL #3]

(3651) 0x4a4dc8 ORR	X20, XZR, X0

(3651) 0x4a4dcc B.EQ	4a55bc

(3651) 0x4a4dd0 LDR	D0, [X8, X20,LSL #3]

(3651) 0x4a4dd4 LDR	D1, [X22]

(3651) 0x4a4dd8 ADD	X0, X20, #1

(3651) 0x4a4ddc ORR	X5, XZR, X18

(3651) 0x4a4de0 LDR	X18, [X9, X0,LSL #3]

(3651) 0x4a4de4 SUBS	X2, X18, X5

(3651) 0x4a4de8 FMUL	D0, D1, D0

(3651) 0x4a4dec B.LE	4a4dc0

(3651) 0x4a4df0 CMP	X2, #2

(3651) 0x4a4df4 B.CS	4a4e00

(3651) 0x4a4df8 ORR	X1, XZR, X5

(3651) 0x4a4dfc B	4a4e54

(3651) 0x4a4e00 AND	X3, X2, #0xfffffffe

(3651) 0x4a4e04 MOVI	D1, #0

(3651) 0x4a4e08 ADD	X4, X14, X5,LSL #3

(3651) 0x4a4e0c AND	X6, X2, #0xfffffffe

(3651) 0x4a4e10 ADD	X1, X5, X3

(3651) 0x4a4e14 ADD	X5, X15, X5,LSL #3

(3651) 0x4a4e18 HINT	#0

(3651) 0x4a4e1c HINT	#0

  (3652) 0x4a4e20 LDP	X7, X21, [X4, #1016]

  (3652) 0x4a4e24 LDP	D2, D3, [X5, #1016]

  (3652) 0x4a4e28 SUBS	X6, X6, #2

  (3652) 0x4a4e2c ADD	X4, X4, #16

  (3652) 0x4a4e30 ADD	X5, X5, #16

  (3652) 0x4a4e34 LDR	D4, [X11, X7,LSL #3]

  (3652) 0x4a4e38 LDR	D5, [X11, X21,LSL #3]

  (3652) 0x4a4e3c FMADD	D0, D4, D2, D0

  (3652) 0x4a4e40 FMADD	D1, D5, D3, D1

  (3652) 0x4a4e44 B.NE	4a4e20

(3651) 0x4a4e48 FADD	D0, D1, D0

(3651) 0x4a4e4c CMP	X2, X3

(3651) 0x4a4e50 B.EQ	4a4dc0

(3651) 0x4a4e54 SUB	W2, W18, W1

(3651) 0x4a4e58 ORR	X3, XZR, X1

(3651) 0x4a4e5c ANDS	X2, X2, #0x3

(3651) 0x4a4e60 B.EQ	4a4e80

  (3654) 0x4a4e64 LDR	X4, [X12, X3,LSL #3]

  (3654) 0x4a4e68 LDR	D1, [X10, X3,LSL #3]

  (3654) 0x4a4e6c ADD	X3, X3, #1

  (3654) 0x4a4e70 SUBS	X2, X2, #1

  (3654) 0x4a4e74 LDR	D2, [X11, X4,LSL #3]

  (3654) 0x4a4e78 FMADD	D0, D2, D1, D0

  (3654) 0x4a4e7c B.NE	4a4e64

(3651) 0x4a4e80 SUB	X1, X1, X18

(3651) 0x4a4e84 CMN	X1, #4

(3651) 0x4a4e88 B.HI	4a4dc0

(3651) 0x4a4e8c SUB	X1, X18, X3

(3651) 0x4a4e90 ADD	X2, X16, X3,LSL #3

(3651) 0x4a4e94 ADD	X3, X17, X3,LSL #3

(3651) 0x4a4e98 HINT	#0

(3651) 0x4a4e9c HINT	#0

  (3653) 0x4a4ea0 LDP	X4, X5, [X2, #1008]

  (3653) 0x4a4ea4 LDP	D2, D3, [X3, #1008]

  (3653) 0x4a4ea8 SUBS	X1, X1, #4

  (3653) 0x4a4eac LDR	D1, [X11, X4,LSL #3]

  (3653) 0x4a4eb0 FMADD	D0, D1, D2, D0

  (3653) 0x4a4eb4 LDR	D1, [X11, X5,LSL #3]

  (3653) 0x4a4eb8 FMADD	D0, D1, D3, D0

  (3653) 0x4a4ebc LDP	X4, X5, [X2], #32

  (3653) 0x4a4ec0 LDR	D2, [X11, X4,LSL #3]

  (3653) 0x4a4ec4 LDP	D1, D3, [X3], #32

  (3653) 0x4a4ec8 FMADD	D0, D2, D1, D0

  (3653) 0x4a4ecc LDR	D1, [X11, X5,LSL #3]

  (3653) 0x4a4ed0 FMADD	D0, D1, D3, D0

  (3653) 0x4a4ed4 B.NE	4a4ea0

(3651) 0x4a4ed8 B	4a4dc0

0x4a4edc FMOV	D1, #-1.0000000

0x4a4ee0 FCMP	D0, D1

0x4a4ee4 B.NE	4a5300

0x4a4ee8 CMP	X20, X19

0x4a4eec B.GE	4a55bc

0x4a4ef0 LDR	X9, [X24]

0x4a4ef4 LDR	X10, [X23]

0x4a4ef8 LDR	X12, [X26]

0x4a4efc ADD	X14, X12, #8

0x4a4f00 LDR	X8, [X8]

0x4a4f04 LDR	X11, [X27]

0x4a4f08 LDR	X13, [X25]

0x4a4f0c LDR	X17, [X9, X20,LSL #3]

0x4a4f10 ADD	X15, X10, #8

0x4a4f14 ADD	X16, X12, #16

0x4a4f18 ADD	X18, X10, #16

0x4a4f1c B	4a4f30

(3696) 0x4a4f20 CMP	X0, X19

(3696) 0x4a4f24 STR	D0, [X13, X20,LSL #3]

(3696) 0x4a4f28 ORR	X20, XZR, X0

(3696) 0x4a4f2c B.EQ	4a55bc

(3696) 0x4a4f30 LDR	D0, [X8, X20,LSL #3]

(3696) 0x4a4f34 ADD	X0, X20, #1

(3696) 0x4a4f38 ORR	X5, XZR, X17

(3696) 0x4a4f3c LDR	X17, [X9, X0,LSL #3]

(3696) 0x4a4f40 SUBS	X2, X17, X5

(3696) 0x4a4f44 FNEG	D0, D0

(3696) 0x4a4f48 B.LE	4a4f20

(3696) 0x4a4f4c CMP	X2, #2

(3696) 0x4a4f50 B.CS	4a4f5c

(3696) 0x4a4f54 ORR	X1, XZR, X5

(3696) 0x4a4f58 B	4a4fb4

(3696) 0x4a4f5c AND	X3, X2, #0xfffffffe

(3696) 0x4a4f60 MOVI	D1, #0

(3696) 0x4a4f64 ADD	X4, X14, X5,LSL #3

(3696) 0x4a4f68 AND	X6, X2, #0xfffffffe

(3696) 0x4a4f6c ADD	X1, X5, X3

(3696) 0x4a4f70 ADD	X5, X15, X5,LSL #3

(3696) 0x4a4f74 HINT	#0

(3696) 0x4a4f78 HINT	#0

(3696) 0x4a4f7c HINT	#0

  (3697) 0x4a4f80 LDP	X7, X21, [X4, #1016]

  (3697) 0x4a4f84 LDP	D2, D3, [X5, #1016]

  (3697) 0x4a4f88 SUBS	X6, X6, #2

  (3697) 0x4a4f8c ADD	X4, X4, #16

  (3697) 0x4a4f90 ADD	X5, X5, #16

  (3697) 0x4a4f94 LDR	D4, [X11, X7,LSL #3]

  (3697) 0x4a4f98 LDR	D5, [X11, X21,LSL #3]

  (3697) 0x4a4f9c FMSUB	D0, D4, D2, D0

  (3697) 0x4a4fa0 FMSUB	D1, D5, D3, D1

  (3697) 0x4a4fa4 B.NE	4a4f80

(3696) 0x4a4fa8 FADD	D0, D1, D0

(3696) 0x4a4fac CMP	X2, X3

(3696) 0x4a4fb0 B.EQ	4a4f20

(3696) 0x4a4fb4 SUB	W2, W17, W1

(3696) 0x4a4fb8 ORR	X3, XZR, X1

(3696) 0x4a4fbc ANDS	X2, X2, #0x3

(3696) 0x4a4fc0 B.EQ	4a4fe0

  (3699) 0x4a4fc4 LDR	X4, [X12, X3,LSL #3]

  (3699) 0x4a4fc8 LDR	D1, [X10, X3,LSL #3]

  (3699) 0x4a4fcc ADD	X3, X3, #1

  (3699) 0x4a4fd0 SUBS	X2, X2, #1

  (3699) 0x4a4fd4 LDR	D2, [X11, X4,LSL #3]

  (3699) 0x4a4fd8 FMSUB	D0, D2, D1, D0

  (3699) 0x4a4fdc B.NE	4a4fc4

(3696) 0x4a4fe0 SUB	X1, X1, X17

(3696) 0x4a4fe4 CMN	X1, #4

(3696) 0x4a4fe8 B.HI	4a4f20

(3696) 0x4a4fec SUB	X1, X17, X3

(3696) 0x4a4ff0 ADD	X2, X16, X3,LSL #3

(3696) 0x4a4ff4 ADD	X3, X18, X3,LSL #3

(3696) 0x4a4ff8 HINT	#0

(3696) 0x4a4ffc HINT	#0

  (3698) 0x4a5000 LDP	X4, X5, [X2, #1008]

  (3698) 0x4a5004 LDP	D2, D3, [X3, #1008]

  (3698) 0x4a5008 SUBS	X1, X1, #4

  (3698) 0x4a500c LDR	D4, [X11, X5,LSL #3]

  (3698) 0x4a5010 LDR	D1, [X11, X4,LSL #3]

  (3698) 0x4a5014 FMUL	D3, D4, D3

  (3698) 0x4a5018 FMADD	D1, D1, D2, D3

  (3698) 0x4a501c LDP	X4, X5, [X2], #32

  (3698) 0x4a5020 LDR	D4, [X11, X4,LSL #3]

  (3698) 0x4a5024 LDP	D2, D3, [X3], #32

  (3698) 0x4a5028 FMADD	D1, D4, D2, D1

  (3698) 0x4a502c LDR	D2, [X11, X5,LSL #3]

  (3698) 0x4a5030 FMADD	D1, D2, D3, D1

  (3698) 0x4a5034 FSUB	D0, D0, S1

  (3698) 0x4a5038 B.NE	4a5000

(3696) 0x4a503c B	4a4f20

0x4a5040 CMP	X20, X19

0x4a5044 B.GE	4a55bc

0x4a5048 LDR	X9, [X24]

0x4a504c LDR	X10, [X23]

0x4a5050 LDR	X12, [X26]

0x4a5054 ADD	X14, X12, #8

0x4a5058 LDR	X8, [X8]

0x4a505c LDR	X11, [X27]

0x4a5060 LDR	X13, [X25]

0x4a5064 LDR	X17, [X9, X20,LSL #3]

0x4a5068 ADD	X15, X10, #8

0x4a506c ADD	X16, X12, #16

0x4a5070 ADD	X18, X10, #16

0x4a5074 B	4a5098

0x4a5078 HINT	#0

0x4a507c HINT	#0

(3647) 0x4a5080 LDR	D1, [X21]

(3647) 0x4a5084 CMP	X0, X19

(3647) 0x4a5088 FMUL	D0, D1, D0

(3647) 0x4a508c STR	D0, [X13, X20,LSL #3]

(3647) 0x4a5090 ORR	X20, XZR, X0

(3647) 0x4a5094 B.EQ	4a55bc

(3647) 0x4a5098 LDR	D0, [X8, X20,LSL #3]

(3647) 0x4a509c ADD	X0, X20, #1

(3647) 0x4a50a0 ORR	X5, XZR, X17

(3647) 0x4a50a4 LDR	X17, [X9, X0,LSL #3]

(3647) 0x4a50a8 SUBS	X2, X17, X5

(3647) 0x4a50ac FNEG	D0, D0

(3647) 0x4a50b0 B.LE	4a5080

(3647) 0x4a50b4 CMP	X2, #2

(3647) 0x4a50b8 B.CS	4a50c4

(3647) 0x4a50bc ORR	X1, XZR, X5

(3647) 0x4a50c0 B	4a5114

(3647) 0x4a50c4 AND	X3, X2, #0xfffffffe

(3647) 0x4a50c8 MOVI	D1, #0

(3647) 0x4a50cc ADD	X4, X14, X5,LSL #3

(3647) 0x4a50d0 AND	X6, X2, #0xfffffffe

(3647) 0x4a50d4 ADD	X1, X5, X3

(3647) 0x4a50d8 ADD	X5, X15, X5,LSL #3

(3647) 0x4a50dc HINT	#0

  (3648) 0x4a50e0 LDP	X7, X22, [X4, #1016]

  (3648) 0x4a50e4 LDP	D2, D3, [X5, #1016]

  (3648) 0x4a50e8 SUBS	X6, X6, #2

  (3648) 0x4a50ec ADD	X4, X4, #16

  (3648) 0x4a50f0 ADD	X5, X5, #16

  (3648) 0x4a50f4 LDR	D4, [X11, X7,LSL #3]

  (3648) 0x4a50f8 LDR	D5, [X11, X22,LSL #3]

  (3648) 0x4a50fc FMADD	D0, D4, D2, D0

  (3648) 0x4a5100 FMADD	D1, D5, D3, D1

  (3648) 0x4a5104 B.NE	4a50e0

(3647) 0x4a5108 FADD	D0, D1, D0

(3647) 0x4a510c CMP	X2, X3

(3647) 0x4a5110 B.EQ	4a5080

(3647) 0x4a5114 SUB	W2, W17, W1

(3647) 0x4a5118 ORR	X3, XZR, X1

(3647) 0x4a511c ANDS	X2, X2, #0x3

(3647) 0x4a5120 B.EQ	4a5140

  (3650) 0x4a5124 LDR	X4, [X12, X3,LSL #3]

  (3650) 0x4a5128 LDR	D1, [X10, X3,LSL #3]

  (3650) 0x4a512c ADD	X3, X3, #1

  (3650) 0x4a5130 SUBS	X2, X2, #1

  (3650) 0x4a5134 LDR	D2, [X11, X4,LSL #3]

  (3650) 0x4a5138 FMADD	D0, D2, D1, D0

  (3650) 0x4a513c B.NE	4a5124

(3647) 0x4a5140 SUB	X1, X1, X17

(3647) 0x4a5144 CMN	X1, #4

(3647) 0x4a5148 B.HI	4a5080

(3647) 0x4a514c SUB	X1, X17, X3

(3647) 0x4a5150 ADD	X2, X16, X3,LSL #3

(3647) 0x4a5154 ADD	X3, X18, X3,LSL #3

(3647) 0x4a5158 HINT	#0

(3647) 0x4a515c HINT	#0

  (3649) 0x4a5160 LDP	X4, X5, [X2, #1008]

  (3649) 0x4a5164 LDP	D2, D3, [X3, #1008]

  (3649) 0x4a5168 SUBS	X1, X1, #4

  (3649) 0x4a516c LDR	D1, [X11, X4,LSL #3]

  (3649) 0x4a5170 FMADD	D0, D1, D2, D0

  (3649) 0x4a5174 LDR	D1, [X11, X5,LSL #3]

  (3649) 0x4a5178 FMADD	D0, D1, D3, D0

  (3649) 0x4a517c LDP	X4, X5, [X2], #32

  (3649) 0x4a5180 LDR	D2, [X11, X4,LSL #3]

  (3649) 0x4a5184 LDP	D1, D3, [X3], #32

  (3649) 0x4a5188 FMADD	D0, D2, D1, D0

  (3649) 0x4a518c LDR	D1, [X11, X5,LSL #3]

  (3649) 0x4a5190 FMADD	D0, D1, D3, D0

  (3649) 0x4a5194 B.NE	4a5160

(3647) 0x4a5198 B	4a5080

0x4a519c FMOV	D1, #-1.0000000

0x4a51a0 FCMP	D0, D1

0x4a51a4 B.NE	4a545c

0x4a51a8 CMP	X20, X19

0x4a51ac B.GE	4a55bc

0x4a51b0 LDR	X9, [X24]

0x4a51b4 LDR	X10, [X23]

0x4a51b8 LDR	X12, [X26]

0x4a51bc ADD	X14, X12, #8

0x4a51c0 LDR	X8, [X8]

0x4a51c4 LDR	X11, [X27]

0x4a51c8 LDR	X13, [X25]

0x4a51cc LDR	X18, [X9, X20,LSL #3]

0x4a51d0 ADD	X15, X10, #8

0x4a51d4 ADD	X16, X12, #16

0x4a51d8 ADD	X17, X10, #16

0x4a51dc B	4a51f0

(3688) 0x4a51e0 CMP	X0, X19

(3688) 0x4a51e4 STR	D0, [X13, X20,LSL #3]

(3688) 0x4a51e8 ORR	X20, XZR, X0

(3688) 0x4a51ec B.EQ	4a55bc

(3688) 0x4a51f0 LDR	D0, [X8, X20,LSL #3]

(3688) 0x4a51f4 LDR	D1, [X22]

(3688) 0x4a51f8 ADD	X0, X20, #1

(3688) 0x4a51fc ORR	X5, XZR, X18

(3688) 0x4a5200 LDR	X18, [X9, X0,LSL #3]

(3688) 0x4a5204 SUBS	X2, X18, X5

(3688) 0x4a5208 FNMUL	D0, D0, D1

(3688) 0x4a520c B.LE	4a51e0

(3688) 0x4a5210 CMP	X2, #2

(3688) 0x4a5214 B.CS	4a5220

(3688) 0x4a5218 ORR	X1, XZR, X5

(3688) 0x4a521c B	4a5274

(3688) 0x4a5220 AND	X3, X2, #0xfffffffe

(3688) 0x4a5224 MOVI	D1, #0

(3688) 0x4a5228 ADD	X4, X14, X5,LSL #3

(3688) 0x4a522c AND	X6, X2, #0xfffffffe

(3688) 0x4a5230 ADD	X1, X5, X3

(3688) 0x4a5234 ADD	X5, X15, X5,LSL #3

(3688) 0x4a5238 HINT	#0

(3688) 0x4a523c HINT	#0

  (3689) 0x4a5240 LDP	X7, X21, [X4, #1016]

  (3689) 0x4a5244 LDP	D2, D3, [X5, #1016]

  (3689) 0x4a5248 SUBS	X6, X6, #2

  (3689) 0x4a524c ADD	X4, X4, #16

  (3689) 0x4a5250 ADD	X5, X5, #16

  (3689) 0x4a5254 LDR	D4, [X11, X7,LSL #3]

  (3689) 0x4a5258 LDR	D5, [X11, X21,LSL #3]

  (3689) 0x4a525c FMSUB	D0, D4, D2, D0

  (3689) 0x4a5260 FMSUB	D1, D5, D3, D1

  (3689) 0x4a5264 B.NE	4a5240

(3688) 0x4a5268 FADD	D0, D1, D0

(3688) 0x4a526c CMP	X2, X3

(3688) 0x4a5270 B.EQ	4a51e0

(3688) 0x4a5274 SUB	W2, W18, W1

(3688) 0x4a5278 ORR	X3, XZR, X1

(3688) 0x4a527c ANDS	X2, X2, #0x3

(3688) 0x4a5280 B.EQ	4a52a0

  (3691) 0x4a5284 LDR	X4, [X12, X3,LSL #3]

  (3691) 0x4a5288 LDR	D1, [X10, X3,LSL #3]

  (3691) 0x4a528c ADD	X3, X3, #1

  (3691) 0x4a5290 SUBS	X2, X2, #1

  (3691) 0x4a5294 LDR	D2, [X11, X4,LSL #3]

  (3691) 0x4a5298 FMSUB	D0, D2, D1, D0

  (3691) 0x4a529c B.NE	4a5284

(3688) 0x4a52a0 SUB	X1, X1, X18

(3688) 0x4a52a4 CMN	X1, #4

(3688) 0x4a52a8 B.HI	4a51e0

(3688) 0x4a52ac SUB	X1, X18, X3

(3688) 0x4a52b0 ADD	X2, X16, X3,LSL #3

(3688) 0x4a52b4 ADD	X3, X17, X3,LSL #3

(3688) 0x4a52b8 HINT	#0

(3688) 0x4a52bc HINT	#0

  (3690) 0x4a52c0 LDP	X4, X5, [X2, #1008]

  (3690) 0x4a52c4 LDP	D2, D3, [X3, #1008]

  (3690) 0x4a52c8 SUBS	X1, X1, #4

  (3690) 0x4a52cc LDR	D4, [X11, X5,LSL #3]

  (3690) 0x4a52d0 LDR	D1, [X11, X4,LSL #3]

  (3690) 0x4a52d4 FMUL	D3, D4, D3

  (3690) 0x4a52d8 FMADD	D1, D1, D2, D3

  (3690) 0x4a52dc LDP	X4, X5, [X2], #32

  (3690) 0x4a52e0 LDR	D4, [X11, X4,LSL #3]

  (3690) 0x4a52e4 LDP	D2, D3, [X3], #32

  (3690) 0x4a52e8 FMADD	D1, D4, D2, D1

  (3690) 0x4a52ec LDR	D2, [X11, X5,LSL #3]

  (3690) 0x4a52f0 FMADD	D1, D2, D3, D1

  (3690) 0x4a52f4 FSUB	D0, D0, S1

  (3690) 0x4a52f8 B.NE	4a52c0

(3688) 0x4a52fc B	4a51e0

0x4a5300 CMP	X20, X19

0x4a5304 B.GE	4a55bc

0x4a5308 LDR	X9, [X24]

0x4a530c LDR	X10, [X23]

0x4a5310 LDR	X12, [X26]

0x4a5314 ADD	X14, X12, #8

0x4a5318 LDR	X8, [X8]

0x4a531c LDR	X11, [X27]

0x4a5320 LDR	X13, [X25]

0x4a5324 LDR	X16, [X9, X20,LSL #3]

0x4a5328 ADD	X15, X10, #8

0x4a532c ADD	X17, X12, #16

0x4a5330 ADD	X18, X10, #16

0x4a5334 B	4a5350

(3692) 0x4a5338 LDR	D1, [X21]

(3692) 0x4a533c CMP	X0, X19

(3692) 0x4a5340 FMUL	D0, D1, D0

(3692) 0x4a5344 STR	D0, [X13, X20,LSL #3]

(3692) 0x4a5348 ORR	X20, XZR, X0

(3692) 0x4a534c B.EQ	4a55bc

(3692) 0x4a5350 LDR	D0, [X8, X20,LSL #3]

(3692) 0x4a5354 ADD	X0, X20, #1

(3692) 0x4a5358 ORR	X5, XZR, X16

(3692) 0x4a535c LDR	X16, [X9, X0,LSL #3]

(3692) 0x4a5360 SUBS	X2, X16, X5

(3692) 0x4a5364 B.LE	4a5338

(3692) 0x4a5368 CMP	X2, #2

(3692) 0x4a536c B.CS	4a5378

(3692) 0x4a5370 ORR	X1, XZR, X5

(3692) 0x4a5374 B	4a53d4

(3692) 0x4a5378 AND	X3, X2, #0xfffffffe

(3692) 0x4a537c MOVI	D1, #0

(3692) 0x4a5380 ADD	X4, X14, X5,LSL #3

(3692) 0x4a5384 AND	X6, X2, #0xfffffffe

(3692) 0x4a5388 ADD	X1, X5, X3

(3692) 0x4a538c ADD	X5, X15, X5,LSL #3

(3692) 0x4a5390 HINT	#0

(3692) 0x4a5394 HINT	#0

(3692) 0x4a5398 HINT	#0

(3692) 0x4a539c HINT	#0

  (3693) 0x4a53a0 LDP	X7, X22, [X4, #1016]

  (3693) 0x4a53a4 LDP	D2, D3, [X5, #1016]

  (3693) 0x4a53a8 SUBS	X6, X6, #2

  (3693) 0x4a53ac ADD	X4, X4, #16

  (3693) 0x4a53b0 ADD	X5, X5, #16

  (3693) 0x4a53b4 LDR	D4, [X11, X7,LSL #3]

  (3693) 0x4a53b8 LDR	D5, [X11, X22,LSL #3]

  (3693) 0x4a53bc FMADD	D0, D4, D2, D0

  (3693) 0x4a53c0 FMADD	D1, D5, D3, D1

  (3693) 0x4a53c4 B.NE	4a53a0

(3692) 0x4a53c8 FADD	D0, D1, D0

(3692) 0x4a53cc CMP	X2, X3

(3692) 0x4a53d0 B.EQ	4a5338

(3692) 0x4a53d4 SUB	W2, W16, W1

(3692) 0x4a53d8 ORR	X3, XZR, X1

(3692) 0x4a53dc ANDS	X2, X2, #0x3

(3692) 0x4a53e0 B.EQ	4a5400

  (3695) 0x4a53e4 LDR	X4, [X12, X3,LSL #3]

  (3695) 0x4a53e8 LDR	D1, [X10, X3,LSL #3]

  (3695) 0x4a53ec ADD	X3, X3, #1

  (3695) 0x4a53f0 SUBS	X2, X2, #1

  (3695) 0x4a53f4 LDR	D2, [X11, X4,LSL #3]

  (3695) 0x4a53f8 FMADD	D0, D2, D1, D0

  (3695) 0x4a53fc B.NE	4a53e4

(3692) 0x4a5400 SUB	X1, X1, X16

(3692) 0x4a5404 CMN	X1, #4

(3692) 0x4a5408 B.HI	4a5338

(3692) 0x4a540c SUB	X1, X16, X3

(3692) 0x4a5410 ADD	X2, X17, X3,LSL #3

(3692) 0x4a5414 ADD	X3, X18, X3,LSL #3

(3692) 0x4a5418 HINT	#0

(3692) 0x4a541c HINT	#0

  (3694) 0x4a5420 LDP	X4, X5, [X2, #1008]

  (3694) 0x4a5424 LDP	D2, D3, [X3, #1008]

  (3694) 0x4a5428 SUBS	X1, X1, #4

  (3694) 0x4a542c LDR	D1, [X11, X4,LSL #3]

  (3694) 0x4a5430 FMADD	D0, D1, D2, D0

  (3694) 0x4a5434 LDR	D1, [X11, X5,LSL #3]

  (3694) 0x4a5438 FMADD	D0, D1, D3, D0

  (3694) 0x4a543c LDP	X4, X5, [X2], #32

  (3694) 0x4a5440 LDR	D2, [X11, X4,LSL #3]

  (3694) 0x4a5444 LDP	D1, D3, [X3], #32

  (3694) 0x4a5448 FMADD	D0, D2, D1, D0

  (3694) 0x4a544c LDR	D1, [X11, X5,LSL #3]

  (3694) 0x4a5450 FMADD	D0, D1, D3, D0

  (3694) 0x4a5454 B.NE	4a5420

(3692) 0x4a5458 B	4a5338

0x4a545c CMP	X20, X19

0x4a5460 B.GE	4a55bc

0x4a5464 LDR	X9, [X24]

0x4a5468 LDR	X10, [X23]

0x4a546c LDR	X12, [X26]

0x4a5470 ADD	X14, X12, #8

0x4a5474 LDR	X8, [X8]

0x4a5478 LDR	X11, [X27]

0x4a547c LDR	X13, [X25]

0x4a5480 LDR	X18, [X9, X20,LSL #3]

0x4a5484 ADD	X15, X10, #8

0x4a5488 ADD	X16, X12, #16

0x4a548c ADD	X17, X10, #16

0x4a5490 B	4a54ac

(3684) 0x4a5494 LDR	D1, [X21]

(3684) 0x4a5498 CMP	X0, X19

(3684) 0x4a549c FMUL	D0, D1, D0

(3684) 0x4a54a0 STR	D0, [X13, X20,LSL #3]

(3684) 0x4a54a4 ORR	X20, XZR, X0

(3684) 0x4a54a8 B.EQ	4a55bc

(3684) 0x4a54ac LDR	D0, [X8, X20,LSL #3]

(3684) 0x4a54b0 LDR	D1, [X22]

(3684) 0x4a54b4 ADD	X0, X20, #1

(3684) 0x4a54b8 ORR	X5, XZR, X18

(3684) 0x4a54bc LDR	X18, [X9, X0,LSL #3]

(3684) 0x4a54c0 SUBS	X2, X18, X5

(3684) 0x4a54c4 FMUL	D0, D1, D0

(3684) 0x4a54c8 B.LE	4a5494

(3684) 0x4a54cc CMP	X2, #2

(3684) 0x4a54d0 B.CS	4a54dc

(3684) 0x4a54d4 ORR	X1, XZR, X5

(3684) 0x4a54d8 B	4a5534

(3684) 0x4a54dc AND	X3, X2, #0xfffffffe

(3684) 0x4a54e0 MOVI	D1, #0

(3684) 0x4a54e4 ADD	X4, X14, X5,LSL #3

(3684) 0x4a54e8 AND	X6, X2, #0xfffffffe

(3684) 0x4a54ec ADD	X1, X5, X3

(3684) 0x4a54f0 ADD	X5, X15, X5,LSL #3

(3684) 0x4a54f4 HINT	#0

(3684) 0x4a54f8 HINT	#0

(3684) 0x4a54fc HINT	#0

  (3685) 0x4a5500 LDP	X7, X23, [X4, #1016]

  (3685) 0x4a5504 LDP	D2, D3, [X5, #1016]

  (3685) 0x4a5508 SUBS	X6, X6, #2

  (3685) 0x4a550c ADD	X4, X4, #16

  (3685) 0x4a5510 ADD	X5, X5, #16

  (3685) 0x4a5514 LDR	D4, [X11, X7,LSL #3]

  (3685) 0x4a5518 LDR	D5, [X11, X23,LSL #3]

  (3685) 0x4a551c FMADD	D0, D4, D2, D0

  (3685) 0x4a5520 FMADD	D1, D5, D3, D1

  (3685) 0x4a5524 B.NE	4a5500

(3684) 0x4a5528 FADD	D0, D1, D0

(3684) 0x4a552c CMP	X2, X3

(3684) 0x4a5530 B.EQ	4a5494

(3684) 0x4a5534 SUB	W2, W18, W1

(3684) 0x4a5538 ORR	X3, XZR, X1

(3684) 0x4a553c ANDS	X2, X2, #0x3

(3684) 0x4a5540 B.EQ	4a5560

  (3687) 0x4a5544 LDR	X4, [X12, X3,LSL #3]

  (3687) 0x4a5548 LDR	D1, [X10, X3,LSL #3]

  (3687) 0x4a554c ADD	X3, X3, #1

  (3687) 0x4a5550 SUBS	X2, X2, #1

  (3687) 0x4a5554 LDR	D2, [X11, X4,LSL #3]

  (3687) 0x4a5558 FMADD	D0, D2, D1, D0

  (3687) 0x4a555c B.NE	4a5544

(3684) 0x4a5560 SUB	X1, X1, X18

(3684) 0x4a5564 CMN	X1, #4

(3684) 0x4a5568 B.HI	4a5494

(3684) 0x4a556c SUB	X1, X18, X3

(3684) 0x4a5570 ADD	X2, X16, X3,LSL #3

(3684) 0x4a5574 ADD	X3, X17, X3,LSL #3

(3684) 0x4a5578 HINT	#0

(3684) 0x4a557c HINT	#0

  (3686) 0x4a5580 LDP	X4, X5, [X2, #1008]

  (3686) 0x4a5584 LDP	D2, D3, [X3, #1008]

  (3686) 0x4a5588 SUBS	X1, X1, #4

  (3686) 0x4a558c LDR	D1, [X11, X4,LSL #3]

  (3686) 0x4a5590 FMADD	D0, D1, D2, D0

  (3686) 0x4a5594 LDR	D1, [X11, X5,LSL #3]

  (3686) 0x4a5598 FMADD	D0, D1, D3, D0

  (3686) 0x4a559c LDP	X4, X5, [X2], #32

  (3686) 0x4a55a0 LDR	D2, [X11, X4,LSL #3]

  (3686) 0x4a55a4 LDP	D1, D3, [X3], #32

  (3686) 0x4a55a8 FMADD	D0, D2, D1, D0

  (3686) 0x4a55ac LDR	D1, [X11, X5,LSL #3]

  (3686) 0x4a55b0 FMADD	D0, D1, D3, D0

  (3686) 0x4a55b4 B.NE	4a5580

(3684) 0x4a55b8 B	4a5494

0x4a55bc LDP	X20, X19, [SP, #80]

0x4a55c0 LDP	X22, X21, [SP, #64]

0x4a55c4 LDP	X24, X23, [SP, #48]

0x4a55c8 LDP	X26, X25, [SP, #32]

0x4a55cc LDP	X28, X27, [SP, #16]

0x4a55d0 LDP	X29, X30, [SP], #96

0x4a55d4 RET

0x4a55d8 HINT	#0

0x4a55dc HINT	#0

Coverage (%)	Name	Module
►98.42+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 36.33 to 6.67 cycles (5.45x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 36.33 to 7.46 cycles (4.87x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CSRMatrixGetLoadBalancedPartitionBegin: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:246
hypre_CSRMatrixGetLoadBalancedPartitionEnd: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:247
hypre_error_handler: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
hypre_fprintf: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	304
nb uops	279
loop length	1216
used w registers	2
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	34.88 cycles
front end	34.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	25.00	25.00	27.25	27.25	27.25	27.25	12.00	2.75	2.75	2.50	36.33	36.33	36.33	3.00	3.00
cycles	25.00	25.00	27.25	27.25	27.25	27.25	12.00	2.75	2.75	2.50	36.33	36.33	36.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	34.88
Dispatch	36.33
Overall L1	36.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 36.33 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4a43d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X23, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4a30f0 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4a3180 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X28, <4ff418>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X28, [X28, #3824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LE 4a445c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X1, <4c2430>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #422	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, <4c2438>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #2936	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ac770 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4c2444>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3378	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aeb20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBNZ X20, #63, 4a446c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4a44a0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X1, <4c2470>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #422	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, <4c2478>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3505	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ac770 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4c2484>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3378	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #249	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aeb20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X26, X25, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
TBNZ X19, #63, 4a461c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 4a461c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMP D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a4658 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a47dc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x40c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X13, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a4514 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
LDR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X1, <4c2620>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #422	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, <4c2628>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3539	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ac770 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4c2634>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3378	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #250	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aeb20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMP D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 4a44c0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D1, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a4940 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a4abc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a46d0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a4c20 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x850>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X13, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a4830 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMOV D2, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D1, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a4d7c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x9ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a4edc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xb0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a49b0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a5040 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xc70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a4b10 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x740>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X13, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a4c78 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x8a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a519c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xdcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a4dd0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xa00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a5300 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xf30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a4f30 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xb60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a5098 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xcc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a545c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x108c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a51f0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xe20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a5350 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a54ac <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x10dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_4

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 36.33 to 6.67 cycles (5.45x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CSRMatrixGetLoadBalancedPartitionBegin: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:246
hypre_CSRMatrixGetLoadBalancedPartitionEnd: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:247
hypre_error_handler: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
hypre_fprintf: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	304
nb uops	279
loop length	1216
used w registers	2
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	34.88 cycles
front end	34.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	25.00	25.00	27.25	27.25	27.25	27.25	12.00	2.75	2.75	2.50	36.33	36.33	36.33	3.00	3.00
cycles	25.00	25.00	27.25	27.25	27.25	27.25	12.00	2.75	2.75	2.50	36.33	36.33	36.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	34.88
Dispatch	36.33
Overall L1	36.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 36.33 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4a43d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X23, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4a30f0 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4a3180 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X28, <4ff418>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X28, [X28, #3824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LE 4a445c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X1, <4c2430>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #422	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, <4c2438>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #2936	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ac770 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4c2444>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3378	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aeb20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBNZ X20, #63, 4a446c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4a44a0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X1, <4c2470>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #422	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, <4c2478>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3505	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ac770 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4c2484>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3378	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #249	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aeb20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X26, X25, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
TBNZ X19, #63, 4a461c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 4a461c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMP D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a4658 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a47dc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x40c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X13, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a4514 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
LDR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X1, <4c2620>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #422	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, <4c2628>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3539	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ac770 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4c2634>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3378	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #250	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aeb20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMP D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 4a44c0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D1, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a4940 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a4abc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a46d0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a4c20 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x850>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X13, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a4830 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMOV D2, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D1, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a4d7c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x9ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a4edc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xb0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a49b0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a5040 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xc70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a4b10 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x740>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X13, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a4c78 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x8a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a519c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xdcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a4dd0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xa00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a5300 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xf30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a4f30 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xb60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a5098 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xcc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4a545c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x108c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a51f0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xe20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a5350 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4a55bc <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a54ac <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14+0x10dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.14–	16.13	7.74
▼Loop 3666 - csr_matvec.c:334-341 - exec–	0.03	0.01
○Loop 3664 - csr_matvec.c:337-339 - exec	0.41	0.14
▼Loop 3665 - csr_matvec.c:334-341 - exec–	0.13	0.05
○Loop 3668 - csr_matvec.c:337-339 - exec	0.26	0.09
○Loop 3667 - csr_matvec.c:337-339 - exec	0.00	0.00
▼Loop 3681 - csr_matvec.c:256-263 - exec–	0.03	0.01
○Loop 3679 - csr_matvec.c:259-261 - exec	6.80	2.34
▼Loop 3680 - csr_matvec.c:256-263 - exec–	0.07	0.03
○Loop 3683 - csr_matvec.c:259-261 - exec	0.28	0.10
○Loop 3682 - csr_matvec.c:259-261 - exec	0.00	0.00
▼Loop 3661 - csr_matvec.c:307-314 - exec–	0.03	0.01
○Loop 3659 - csr_matvec.c:310-312 - exec	7.66	2.64
▼Loop 3660 - csr_matvec.c:307-314 - exec–	0.12	0.04
○Loop 3663 - csr_matvec.c:310-312 - exec	0.31	0.11
○Loop 3662 - csr_matvec.c:310-312 - exec	0.00	0.00
▼Loop 3684 - csr_matvec.c:397-404 - exec–	0.00	0.00
○Loop 3687 - csr_matvec.c:400-402 - exec	0.00	0.00
○Loop 3685 - csr_matvec.c:400-402 - exec	0.00	0.00
○Loop 3686 - csr_matvec.c:400-402 - exec	0.00	0.00
▼Loop 3676 - csr_matvec.c:295-302 - exec–	0.00	0.00
▼Loop 3675 - csr_matvec.c:295-302 - exec–	0.00	0.00
○Loop 3678 - csr_matvec.c:298-300 - exec	0.00	0.00
○Loop 3677 - csr_matvec.c:298-300 - exec	0.00	0.00
○Loop 3674 - csr_matvec.c:298-300 - exec	0.00	0.00
▼Loop 3651 - csr_matvec.c:373-380 - exec–	0.00	0.00
○Loop 3654 - csr_matvec.c:376-378 - exec	0.00	0.00
○Loop 3652 - csr_matvec.c:376-378 - exec	0.00	0.00
○Loop 3653 - csr_matvec.c:376-378 - exec	0.00	0.00
▼Loop 3688 - csr_matvec.c:385-392 - exec–	0.00	0.00
○Loop 3690 - csr_matvec.c:388-390 - exec	0.00	0.00
○Loop 3689 - csr_matvec.c:388-390 - exec	0.00	0.00
○Loop 3691 - csr_matvec.c:388-390 - exec	0.00	0.00
▼Loop 3655 - csr_matvec.c:280-287 - exec–	0.00	0.00
○Loop 3658 - csr_matvec.c:283-285 - exec	0.00	0.00
○Loop 3656 - csr_matvec.c:283-285 - exec	0.00	0.00
○Loop 3657 - csr_matvec.c:283-285 - exec	0.00	0.00
▼Loop 3647 - csr_matvec.c:319-326 - exec–	0.00	0.00
○Loop 3648 - csr_matvec.c:322-324 - exec	0.00	0.00
○Loop 3649 - csr_matvec.c:322-324 - exec	0.00	0.00
○Loop 3650 - csr_matvec.c:322-324 - exec	0.00	0.00
▼Loop 3671 - csr_matvec.c:268-275 - exec–	0.00	0.00
▼Loop 3670 - csr_matvec.c:268-275 - exec–	0.00	0.00
○Loop 3673 - csr_matvec.c:271-273 - exec	0.00	0.00
○Loop 3672 - csr_matvec.c:271-273 - exec	0.00	0.00
○Loop 3669 - csr_matvec.c:271-273 - exec	0.00	0.00
▼Loop 3692 - csr_matvec.c:358-365 - exec–	0.00	0.00
○Loop 3693 - csr_matvec.c:361-363 - exec	0.00	0.00
○Loop 3694 - csr_matvec.c:361-363 - exec	0.00	0.00
○Loop 3695 - csr_matvec.c:361-363 - exec	0.00	0.00
▼Loop 3696 - csr_matvec.c:346-353 - exec–	0.00	0.00
○Loop 3697 - csr_matvec.c:349-351 - exec	0.00	0.00
○Loop 3698 - csr_matvec.c:349-351 - exec	0.00	0.00
○Loop 3699 - csr_matvec.c:349-351 - exec	0.00	0.00

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Details

Matching between your function (in the source code) and the binary function

General properties

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ASM code