OV - exec - Loop 2916

  (2915) 0x486280 CMP	X30, X21

  (2915) 0x486284 STR	X23, [X5, X26,LSL #3]

  (2915) 0x486288 STR	X20, [X7, X26,LSL #3]

  (2915) 0x48628c ORR	X19, XZR, X21

  (2915) 0x486290 ORR	X20, XZR, X24

  (2915) 0x486294 ORR	X23, XZR, X6

  (2915) 0x486298 ORR	X26, XZR, X30

  (2915) 0x48629c B.EQ	4864a0

  (2915) 0x4862a0 LDUR	X8, [X29, #496]

  (2915) 0x4862a4 LDR	X8, [X8]

  (2915) 0x4862a8 CBZ	X8, 4862b4

  (2915) 0x4862ac ADD	X6, X23, #1

  (2915) 0x4862b0 STR	X23, [X0, X26,LSL #3]

  (2915) 0x4862b4 LDR	X8, [X15]

  (2915) 0x4862b8 CBZ	X8, 486380

  (2915) 0x4862bc LDUR	X8, [X29, #488]

  (2915) 0x4862c0 ADD	X13, X8, X26,LSL #3

  (2915) 0x4862c4 LDP	X14, X8, [X13]

  (2915) 0x4862c8 CMP	X14, X8

  (2915) 0x4862cc B.GE	4863a0

  (2915) 0x4862d0 LDR	X8, [SP, #72]

  (2915) 0x4862d4 ORR	X24, XZR, X20

  (2915) 0x4862d8 LDR	X19, [X8]

  (2915) 0x4862dc LDUR	X8, [X29, #448]

  (2915) 0x4862e0 LDR	X27, [X8]

  (2915) 0x4862e4 B	4862f8

    (2919) 0x4862e8 LDR	X8, [X13, #8]

    (2919) 0x4862ec ADD	X14, X14, #1

    (2919) 0x4862f0 CMP	X14, X8

    (2919) 0x4862f4 B.GE	486384

    (2919) 0x4862f8 LDR	X28, [X17, X14,LSL #3]

    (2919) 0x4862fc ADD	X8, X28, #1

    (2919) 0x486300 LDR	X9, [X18, X28,LSL #3]

    (2919) 0x486304 LDR	X10, [X18, X8,LSL #3]

    (2919) 0x486308 B	486310

      (2921) 0x48630c ADD	X9, X9, #1

      (2921) 0x486310 CMP	X9, X10

      (2921) 0x486314 B.GE	486340

      (2921) 0x486318 LDR	X25, [X22]

      (2921) 0x48631c LDR	X12, [X19, X9,LSL #3]

      (2921) 0x486320 ADD	X30, X0, X25,LSL #3

      (2921) 0x486324 LDR	X25, [X30, X12,LSL #3]

      (2921) 0x486328 CMP	X25, X20

      (2921) 0x48632c B.GE	48630c

      (2921) 0x486330 STR	X24, [X30, X12,LSL #3]

      (2921) 0x486334 ADD	X24, X24, #1

      (2921) 0x486338 LDR	X10, [X18, X8,LSL #3]

      (2921) 0x48633c B	48630c

    (2919) 0x486340 LDR	X9, [X1, X28,LSL #3]

    (2919) 0x486344 LDR	X10, [X1, X8,LSL #3]

    (2919) 0x486348 B	486350

      (2920) 0x48634c ADD	X9, X9, #1

      (2920) 0x486350 CMP	X9, X10

      (2920) 0x486354 B.GE	4862e8

      (2920) 0x486358 LDR	X12, [X27, X9,LSL #3]

      (2920) 0x48635c LDR	X25, [X0, X12,LSL #3]

      (2920) 0x486360 CMP	X25, X23

      (2920) 0x486364 B.GE	48634c

      (2920) 0x486368 STR	X6, [X0, X12,LSL #3]

      (2920) 0x48636c ADD	X6, X6, #1

      (2920) 0x486370 LDR	X10, [X1, X8,LSL #3]

      (2920) 0x486374 B	48634c

  (2915) 0x486380 ORR	X24, XZR, X20

  (2915) 0x486384 ADD	X30, X26, #1

  (2915) 0x486388 LDR	X28, [X2, X26,LSL #3]

  (2915) 0x48638c LDR	X8, [X2, X30,LSL #3]

  (2915) 0x486390 CMP	X28, X8

  (2915) 0x486394 B.GE	486280

0x486398 B	4863b8

  (2915) 0x4863a0 ORR	X24, XZR, X20

  (2915) 0x4863a4 ADD	X30, X26, #1

  (2915) 0x4863a8 LDR	X28, [X2, X26,LSL #3]

  (2915) 0x4863ac LDR	X8, [X2, X30,LSL #3]

  (2915) 0x4863b0 CMP	X28, X8

  (2915) 0x4863b4 B.GE	486280

0x4863b8 LDP	X9, X8, [X29, #968]

0x4863bc LDR	X27, [X9]

0x4863c0 LDR	X13, [X8]

0x4863c4 LDP	X9, X8, [X29, #984]

0x4863c8 LDR	X14, [X9]

0x4863cc LDR	X19, [X8]

0x4863d0 B	4863f0

0x4863e0 LDR	X8, [X2, X30,LSL #3]

0x4863e4 ADD	X28, X28, #1

0x4863e8 CMP	X28, X8

0x4863ec B.GE	486280

0x4863f0 LDR	X9, [X3, X28,LSL #3]

0x4863f4 ADD	X8, X9, #1

0x4863f8 LDR	X10, [X4, X9,LSL #3]

0x4863fc LDR	X12, [X4, X8,LSL #3]

0x486400 B	486408

  (2918) 0x486404 ADD	X10, X10, #1

  (2918) 0x486408 CMP	X10, X12

  (2918) 0x48640c B.GE	486440

  (2918) 0x486410 LDR	X25, [X27, X10,LSL #3]

  (2918) 0x486414 LDR	X16, [X0, X25,LSL #3]

  (2918) 0x486418 CMP	X16, X23

  (2918) 0x48641c B.GE	486404

  (2918) 0x486420 STR	X6, [X0, X25,LSL #3]

  (2918) 0x486424 ADD	X6, X6, #1

  (2918) 0x486428 LDR	X12, [X4, X8,LSL #3]

  (2918) 0x48642c B	486404

0x486440 LDR	X10, [X11]

0x486444 CBZ	X10, 4863e0

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242

--------------------------------------------------------------------------------

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

136:          B_marker[i1] = jj_count_diag;

137:          jj_count_diag++;

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

147:          {

148:             i2 = A_offd_j[jj2];

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

188:       {

189:          i2 = A_diag_j[jj2];

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

196:          {

197:             i3 = B_diag_j[jj3];

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module
►98.42+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_ParMatmul_RowSizes	par_csr_matop.c:286	exec
○	hypre_ParMatmul	par_csr_matop.c:811	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1226	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P10, P11, P12,
Function	hypre_ParMatmul_RowSizes.omp_outlined
Source	par_csr_matop.c:187-189,par_csr_matop.c:195-195,par_csr_matop.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.67
CQA cycles if no scalar integer	3.67
CQA cycles if FP arith vectorized	3.67
CQA cycles if fully vectorized	0.92
Front-end cycles	2.38
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.67
P11 cycles	3.67
P12 cycles	3.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	19.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P10, P11, P12,
Function	hypre_ParMatmul_RowSizes.omp_outlined
Source	par_csr_matop.c:187-189,par_csr_matop.c:195-195,par_csr_matop.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.67
CQA cycles if no scalar integer	3.67
CQA cycles if FP arith vectorized	3.67
CQA cycles if fully vectorized	0.92
Front-end cycles	2.38
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.67
P11 cycles	3.67
P12 cycles	3.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	19.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes.omp_outlined
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-148,154-156,164-177,187-189,195-197,205-208,216,241-242.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:187-189,195,216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.67 to 0.92 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	19
nb uops	19
loop length	76
used w registers	0
used x registers	15
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.38 cycles
front end	2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	3.67	3.67	3.67	0.00	0.00
cycles	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	3.67	3.67	3.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.38
Dispatch	3.67
Overall L1	3.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4863e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
B 4863b8 <hypre_ParMatmul_RowSizes.omp_outlined+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [X29, #968]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDR X27, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR X13, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDP X9, X8, [X29, #984]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDR X14, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR X19, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
B 4863f0 <hypre_ParMatmul_RowSizes.omp_outlined+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X2, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
CMP X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.GE 486280 <hypre_ParMatmul_RowSizes.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X3, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X8, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X10, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR X12, [X4, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
B 486408 <hypre_ParMatmul_RowSizes.omp_outlined+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CBZ X10, 4863e0 <hypre_ParMatmul_RowSizes.omp_outlined+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParMatmul_RowSizes.omp_outlined
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-148,154-156,164-177,187-189,195-197,205-208,216,241-242.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:187-189,195,216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.67 to 0.92 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	19
nb uops	19
loop length	76
used w registers	0
used x registers	15
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.38 cycles
front end	2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	3.67	3.67	3.67	0.00	0.00
cycles	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	3.67	3.67	3.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.38
Dispatch	3.67
Overall L1	3.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4863e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
B 4863b8 <hypre_ParMatmul_RowSizes.omp_outlined+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [X29, #968]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDR X27, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR X13, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDP X9, X8, [X29, #984]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDR X14, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR X19, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
B 4863f0 <hypre_ParMatmul_RowSizes.omp_outlined+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X2, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
CMP X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.GE 486280 <hypre_ParMatmul_RowSizes.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X3, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X8, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X10, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR X12, [X4, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
B 486408 <hypre_ParMatmul_RowSizes.omp_outlined+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CBZ X10, 4863e0 <hypre_ParMatmul_RowSizes.omp_outlined+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code