| Loop Id: 3525 | Module: exec | Source: csr_matop.c:272-298 | Coverage: 0.01% |
|---|
| Loop Id: 3525 | Module: exec | Source: csr_matop.c:272-298 | Coverage: 0.01% |
|---|
(3523) 0x4a09c0 CMP X21, X28 |
(3523) 0x4a09c4 B.GE 4a0a98 |
(3523) 0x4a09c8 LDR X16, [X8, X21,LSL #3] |
(3523) 0x4a09cc LDR X17, [X19] |
(3523) 0x4a09d0 CBZ X17, 4a09e4 |
(3523) 0x4a09d4 STR X9, [X20, X21,LSL #3] |
(3523) 0x4a09d8 STR XZR, [X10, X9,LSL #3] |
(3523) 0x4a09dc STR X21, [X11, X9,LSL #3] |
(3523) 0x4a09e0 ADD X9, X9, #1 |
(3523) 0x4a09e4 LDR X17, [X12, X21,LSL #3] |
(3523) 0x4a09e8 ADD X21, X21, #1 |
(3523) 0x4a09ec LDR X3, [X12, X21,LSL #3] |
(3523) 0x4a09f0 CMP X17, X3 |
(3523) 0x4a09f4 B.GE 4a09c0 |
(3524) 0x4a09f8 LDR X18, [X27] |
(3524) 0x4a09fc LDR X0, [X24] |
(3524) 0x4a0a00 B 4a0a14 |
(3527) 0x4a0a04 LDR X3, [X12, X21,LSL #3] |
(3524) 0x4a0a08 ADD X17, X17, #1 |
(3524) 0x4a0a0c CMP X17, X3 |
(3524) 0x4a0a10 B.GE 4a09c0 |
(3524) 0x4a0a14 LDR X1, [X13, X17,LSL #3] |
(3524) 0x4a0a18 ADD X1, X15, X1,LSL #3 |
(3524) 0x4a0a1c LDP X2, X4, [X1] |
(3524) 0x4a0a20 CMP X2, X4 |
(3524) 0x4a0a24 B.GE 4a0a08 |
0x4a0a28 LDR D0, [X14, X17,LSL #3] |
0x4a0a2c LDR X3, [X22] |
0x4a0a30 LDR X5, [X23] |
0x4a0a34 B 4a0a68 |
0x4a0a40 STR X9, [X20, X6,LSL #3] |
0x4a0a44 STR X6, [X5, X9,LSL #3] |
0x4a0a48 FMUL D1, D1, D0 |
0x4a0a4c ADD X9, X9, #1 |
0x4a0a50 LDR X4, [X20, X6,LSL #3] |
0x4a0a54 STR D1, [X3, X4,LSL #3] |
0x4a0a58 LDR X4, [X1, #8] |
0x4a0a5c ADD X2, X2, #1 |
0x4a0a60 CMP X2, X4 |
0x4a0a64 B.GE 4a0a04 |
(3526) 0x4a0a68 LDR X6, [X18, X2,LSL #3] |
(3526) 0x4a0a6c LDR D1, [X0, X2,LSL #3] |
(3526) 0x4a0a70 LDR X7, [X20, X6,LSL #3] |
(3526) 0x4a0a74 CMP X7, X16 |
(3526) 0x4a0a78 B.LT 4a0a40 |
(3526) 0x4a0a7c LDR D2, [X3, X7,LSL #3] |
(3526) 0x4a0a80 FMADD D1, D1, D0, D2 |
(3526) 0x4a0a84 STR D1, [X3, X7,LSL #3] |
(3526) 0x4a0a88 ADD X2, X2, #1 |
(3526) 0x4a0a8c CMP X2, X4 |
(3526) 0x4a0a90 B.LT 4a0a68 |
(3527) 0x4a0a94 B 4a0a04 |
/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 272 - 298 |
-------------------------------------------------------------------------------- |
272: for (ic = ns; ic < ne; ic++) |
273: { |
274: row_start = C_i[ic]; |
275: if (allsquare) |
276: { |
277: B_marker[ic] = counter; |
278: C_data[counter] = 0; |
279: C_j[counter] = ic; |
280: counter++; |
281: } |
282: for (ia = A_i[ic]; ia < A_i[ic+1]; ia++) |
283: { |
284: ja = A_j[ia]; |
285: a_entry = A_data[ia]; |
286: for (ib = B_i[ja]; ib < B_i[ja+1]; ib++) |
287: { |
288: jb = B_j[ib]; |
289: b_entry = B_data[ib]; |
290: if (B_marker[jb] < row_start) |
291: { |
292: B_marker[jb] = counter; |
293: C_j[B_marker[jb]] = jb; |
294: C_data[B_marker[jb]] = a_entry*b_entry; |
295: counter++; |
296: } |
297: else |
298: C_data[B_marker[jb]] += a_entry*b_entry; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_launch_thread | libomp.so | |
| ○ | __kmp_launch_worker(void*) | libomp.so | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.89 |
| CQA speedup if FP arith vectorized | 1.70 |
| CQA speedup if fully vectorized | 4.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.06 |
| Bottlenecks | P10, |
| Function | hypre_CSRMatrixMultiply.omp_outlined |
| Source | csr_matop.c:286-286,csr_matop.c:292-295 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.83 |
| CQA cycles if no scalar integer | 1.50 |
| CQA cycles if FP arith vectorized | 1.67 |
| CQA cycles if fully vectorized | 0.71 |
| Front-end cycles | 1.75 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 0.75 |
| P3 cycles | 0.75 |
| P4 cycles | 0.75 |
| P5 cycles | 0.75 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 0.50 |
| P10 cycles | 2.83 |
| P11 cycles | 2.50 |
| P12 cycles | 2.67 |
| P13 cycles | 1.00 |
| P14 cycles | 1.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 14.00 |
| Nb uops | 14.00 |
| Nb loads | NA |
| Nb stores | 3.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.35 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 0.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 0.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 25.00 |
| Vector-efficiency ratio load | 25.00 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | 25.00 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.89 |
| CQA speedup if FP arith vectorized | 1.70 |
| CQA speedup if fully vectorized | 4.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.06 |
| Bottlenecks | P10, |
| Function | hypre_CSRMatrixMultiply.omp_outlined |
| Source | csr_matop.c:286-286,csr_matop.c:292-295 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.83 |
| CQA cycles if no scalar integer | 1.50 |
| CQA cycles if FP arith vectorized | 1.67 |
| CQA cycles if fully vectorized | 0.71 |
| Front-end cycles | 1.75 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 0.75 |
| P3 cycles | 0.75 |
| P4 cycles | 0.75 |
| P5 cycles | 0.75 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 0.50 |
| P10 cycles | 2.83 |
| P11 cycles | 2.50 |
| P12 cycles | 2.67 |
| P13 cycles | 1.00 |
| P14 cycles | 1.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 14.00 |
| Nb uops | 14.00 |
| Nb loads | NA |
| Nb stores | 3.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.35 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 0.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 0.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 25.00 |
| Vector-efficiency ratio load | 25.00 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | 25.00 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | hypre_CSRMatrixMultiply.omp_outlined |
| Source file and lines | csr_matop.c:272-298 |
| Module | exec |
| nb instructions | 14 |
| nb uops | 14 |
| loop length | 56 |
| used w registers | 0 |
| used x registers | 12 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 2 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 1.75 cycles |
| front end | 1.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 0.75 | 0.75 | 0.75 | 0.75 | 0.50 | 0.50 | 0.50 | 0.50 | 2.83 | 2.50 | 2.67 | 1.00 | 1.00 |
| cycles | 1.00 | 1.00 | 0.75 | 0.75 | 0.75 | 0.75 | 0.50 | 0.50 | 0.50 | 0.50 | 2.83 | 2.50 | 2.67 | 1.00 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 1.75 |
| Dispatch | 2.83 |
| Overall L1 | 2.83 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 25% |
| load | 25% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 25% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 25% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 25% |
| load | 25% |
| store | 25% |
| mul | 25% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDR D0, [X14, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR X3, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X5, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| B 4a0a68 <hypre_CSRMatrixMultiply.omp_outlined+0x508> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR X9, [X20, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| STR X6, [X5, X9,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| FMUL D1, D1, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| ADD X9, X9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X4, [X20, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR D1, [X3, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| LDR X4, [X1, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD X2, X2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X2, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.GE 4a0a04 <hypre_CSRMatrixMultiply.omp_outlined+0x4a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| Function | hypre_CSRMatrixMultiply.omp_outlined |
| Source file and lines | csr_matop.c:272-298 |
| Module | exec |
| nb instructions | 14 |
| nb uops | 14 |
| loop length | 56 |
| used w registers | 0 |
| used x registers | 12 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 2 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 1.75 cycles |
| front end | 1.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 0.75 | 0.75 | 0.75 | 0.75 | 0.50 | 0.50 | 0.50 | 0.50 | 2.83 | 2.50 | 2.67 | 1.00 | 1.00 |
| cycles | 1.00 | 1.00 | 0.75 | 0.75 | 0.75 | 0.75 | 0.50 | 0.50 | 0.50 | 0.50 | 2.83 | 2.50 | 2.67 | 1.00 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 1.75 |
| Dispatch | 2.83 |
| Overall L1 | 2.83 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 25% |
| load | 25% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 25% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 25% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 25% |
| load | 25% |
| store | 25% |
| mul | 25% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDR D0, [X14, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR X3, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X5, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| B 4a0a68 <hypre_CSRMatrixMultiply.omp_outlined+0x508> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR X9, [X20, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| STR X6, [X5, X9,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| FMUL D1, D1, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| ADD X9, X9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X4, [X20, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR D1, [X3, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| LDR X4, [X1, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD X2, X2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X2, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.GE 4a0a04 <hypre_CSRMatrixMultiply.omp_outlined+0x4a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
