OV - exec - Loop 695

	Loop Id: 695	Module: exec	Source: par_multi_interp.c:1072-1104	Coverage: 0.04%

0x4353ec LDUR	X10, [X29, #472]

0x4353f0 ADD	X27, X27, #1

0x4353f4 CMP	X27, X10

0x4353f8 B.GE	435644

0x4353fc LDUR	X10, [X29, #440]

0x435400 LDR	X18, [X10, X27,LSL #3]

0x435404 ADD	X17, X18, #1

0x435408 LDR	X0, [X11, X18,LSL #3]

0x43540c LDR	X10, [X11, X17,LSL #3]

0x435410 CMP	X0, X10

0x435414 B.GE	435540

0x435418 LDUR	X10, [X29, #424]

0x43541c LDR	X3, [X19]

0x435420 ORN	X4, XZR, X18

0x435424 LDR	X1, [X10]

0x435428 LDUR	X10, [X29, #480]

0x43542c LDR	X2, [X10]

0x435430 LDUR	X10, [X29, #432]

0x435434 LDR	X5, [X10]

0x435438 LDUR	X10, [X29, #488]

0x43543c LDR	X6, [X10]

0x435440 LDUR	X10, [X29, #496]

0x435444 LDR	X7, [X10]

0x435448 B	43545c

  (699) 0x43544c LDR	X10, [X11, X17,LSL #3]

  (699) 0x435450 ADD	X0, X0, #1

  (699) 0x435454 CMP	X0, X10

  (699) 0x435458 B.GE	435540

  (699) 0x43545c LDR	X26, [X12, X0,LSL #3]

  (699) 0x435460 LDR	X20, [X21]

  (699) 0x435464 LDR	X10, [X13, X26,LSL #3]

  (699) 0x435468 SUB	X20, X20, #1

  (699) 0x43546c CMP	X10, X20

  (699) 0x435470 B.NE	43544c

  (699) 0x435474 ADD	X30, X26, #1

  (699) 0x435478 LDR	X20, [X2, X30,LSL #3]

  (699) 0x43547c CMP	X20, #1

  (699) 0x435480 B.LT	4354e0

  (699) 0x435484 LDR	X10, [X1, X26,LSL #3]

  (699) 0x435488 ADD	X25, X20, X10

  (699) 0x43548c B	4354ac

    (701) 0x4354a0 ADD	X10, X10, #1

    (701) 0x4354a4 CMP	X10, X25

    (701) 0x4354a8 B.GE	4354e0

    (701) 0x4354ac LDR	X20, [X21]

    (701) 0x4354b0 ADD	X20, X3, X20,LSL #3

    (701) 0x4354b4 LDUR	X28, [X20, #504]

    (701) 0x4354b8 LDR	X28, [X28, X10,LSL #3]

    (701) 0x4354bc LDR	X24, [X22, X28,LSL #3]

    (701) 0x4354c0 CMP	X24, X4

    (701) 0x4354c4 B.EQ	4354a0

    (701) 0x4354c8 LDR	X20, [X20]

    (701) 0x4354cc STR	X28, [X20, X8,LSL #3]

    (701) 0x4354d0 ADD	X8, X8, #1

    (701) 0x4354d4 STR	X4, [X22, X28,LSL #3]

    (701) 0x4354d8 B	4354a0

  (699) 0x4354e0 LDR	X20, [X6, X30,LSL #3]

  (699) 0x4354e4 CMP	X20, #1

  (699) 0x4354e8 B.LT	43544c

  (699) 0x4354ec LDR	X10, [X5, X26,LSL #3]

  (699) 0x4354f0 ADD	X25, X20, X10

  (699) 0x4354f4 B	43550c

    (700) 0x435500 ADD	X10, X10, #1

    (700) 0x435504 CMP	X10, X25

    (700) 0x435508 B.GE	43544c

    (700) 0x43550c LDR	X20, [X21]

    (700) 0x435510 ADD	X20, X7, X20,LSL #3

    (700) 0x435514 LDUR	X24, [X20, #504]

    (700) 0x435518 LDR	X26, [X24, X10,LSL #3]

    (700) 0x43551c LDR	X24, [X23, X26,LSL #3]

    (700) 0x435520 CMP	X24, X4

    (700) 0x435524 B.EQ	435500

    (700) 0x435528 LDR	X20, [X20]

    (700) 0x43552c STR	X26, [X20, X9,LSL #3]

    (700) 0x435530 ADD	X9, X9, #1

    (700) 0x435534 STR	X4, [X23, X26,LSL #3]

    (700) 0x435538 B	435500

0x435540 LDR	X0, [X14, X18,LSL #3]

0x435544 LDR	X4, [X14, X17,LSL #3]

0x435548 CMP	X0, X4

0x43554c B.GE	4353ec

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1072 - 1104

--------------------------------------------------------------------------------

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

Coverage (%)	Name	Source Location	Module
►98.86+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.14+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:693	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:785	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.9
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.50
Front-end cycles	3.50
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.9
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.50
Front-end cycles	3.50
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.9
Source file and lines	par_multi_interp.c:1072-1104
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1104.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1104.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	28
nb uops	28
loop length	112
used w registers	0
used x registers	17
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	6.00	6.00	6.00	0.00	0.00
cycles	2.00	2.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	6.00
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4353ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
CMP X27, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.GE 435644 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X10, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X17, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X0, [X11, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X10, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.GE 435540 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x860>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X3, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ORN X4, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X1, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X2, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X5, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X6, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X7, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
B 43545c <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x77c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X4, [X14, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
B.GE 4353ec <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x70c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.9
Source file and lines	par_multi_interp.c:1072-1104
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	28
nb uops	28
loop length	112
used w registers	0
used x registers	17
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	6.00	6.00	6.00	0.00	0.00
cycles	2.00	2.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	6.00
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4353ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
CMP X27, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.GE 435644 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X10, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X17, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X0, [X11, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X10, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.GE 435540 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x860>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X3, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ORN X4, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X1, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X2, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X5, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X6, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X7, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
B 43545c <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x77c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X4, [X14, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
B.GE 4353ec <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x70c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code