OV - exec - Loop 757

	Loop Id: 757	Module: exec	Source: par_multi_interp.c:1774-1876	Coverage: 0.13%

0x4374a0 LDUR	X9, [X29, #472]

0x4374a4 LDUR	X8, [X29, #336]

0x4374a8 ADD	X9, X9, #1

0x4374ac CMP	X9, X8

0x4374b0 B.GE	437bd8

0x4374b4 LDP	X8, X10, [X29, #944]

0x4374b8 STUR	X9, [X29, #472]

0x4374bc LDR	X11, [X10, X9,LSL #3]

0x4374c0 LDR	X9, [X8, X11,LSL #3]

0x4374c4 ADD	X8, X11, #1

0x4374c8 LDR	X12, [X14, X11,LSL #3]

0x4374cc LDR	X13, [X14, X8,LSL #3]

0x4374d0 ADD	X10, X13, X9

0x4374d4 SUB	X10, X10, X12

0x4374d8 CMP	X9, X10

0x4374dc B.GE	437570

0x4374e0 SUB	W16, W13, W12

0x4374e4 ADD	X15, X12, #1

0x4374e8 TBZ	W16, #0, 437514

0x4374ec LDR	X16, [X28]

0x4374f0 LDR	X18, [SP, #176]

0x4374f4 LDR	X16, [X0, X16,LSL #3]

0x4374f8 STR	XZR, [X18, X12,LSL #3]

0x4374fc LDR	X18, [SP, #56]

0x437500 LDR	X16, [X16, X9,LSL #3]

0x437504 ADD	X9, X9, #1

0x437508 STR	X12, [X21, X16,LSL #3]

0x43750c STR	X16, [X18, X12,LSL #3]

0x437510 ORR	X12, XZR, X15

0x437514 CMP	X13, X15

0x437518 B.EQ	437570

0x43751c LDP	X15, X13, [SP, #32]

0x437520 ADD	X13, X13, X12,LSL #3

0x437524 ADD	X15, X15, X12,LSL #3

  (766) 0x437528 LDR	X16, [X28]

  (766) 0x43752c ADD	X18, X12, #1

  (766) 0x437530 LDR	X16, [X0, X16,LSL #3]

  (766) 0x437534 LDR	X16, [X16, X9,LSL #3]

  (766) 0x437538 STR	X12, [X21, X16,LSL #3]

  (766) 0x43753c STP	XZR, XZR, [X13, #1016]

  (766) 0x437540 STUR	X16, [X15, #504]

  (766) 0x437544 ADD	X13, X13, #16

  (766) 0x437548 ADD	X12, X12, #2

  (766) 0x43754c LDR	X16, [X28]

  (766) 0x437550 LDR	X16, [X0, X16,LSL #3]

  (766) 0x437554 ADD	X16, X16, X9,LSL #3

  (766) 0x437558 ADD	X9, X9, #2

  (766) 0x43755c LDR	X16, [X16, #8]

  (766) 0x437560 CMP	X10, X9

  (766) 0x437564 STR	X18, [X21, X16,LSL #3]

  (766) 0x437568 STR	X16, [X15], #16

  (766) 0x43756c B.NE	437528

0x437570 LDUR	X9, [X29, #416]

0x437574 LDR	X13, [X17, X8,LSL #3]

0x437578 LDR	X12, [X17, X11,LSL #3]

0x43757c LDR	X9, [X9, X11,LSL #3]

0x437580 ADD	X10, X13, X9

0x437584 SUB	X10, X10, X12

0x437588 CMP	X9, X10

0x43758c B.GE	437628

0x437590 SUB	W16, W13, W12

0x437594 ADD	X15, X12, #1

0x437598 TBZ	W16, #0, 4375c4

0x43759c LDR	X16, [X28]

0x4375a0 LDR	X18, [SP, #168]

0x4375a4 LDR	X16, [X1, X16,LSL #3]

0x4375a8 STR	XZR, [X18, X12,LSL #3]

0x4375ac LDR	X18, [SP, #48]

0x4375b0 LDR	X16, [X16, X9,LSL #3]

0x4375b4 ADD	X9, X9, #1

0x4375b8 STR	X12, [X22, X16,LSL #3]

0x4375bc STR	X16, [X18, X12,LSL #3]

0x4375c0 ORR	X12, XZR, X15

0x4375c4 CMP	X13, X15

0x4375c8 B.EQ	437628

0x4375cc LDP	X15, X13, [SP, #16]

0x4375d0 ADD	X13, X13, X12,LSL #3

0x4375d4 ADD	X15, X15, X12,LSL #3

0x4375d8 HINT	#0

0x4375dc HINT	#0

  (765) 0x4375e0 LDR	X16, [X28]

  (765) 0x4375e4 ADD	X18, X12, #1

  (765) 0x4375e8 LDR	X16, [X1, X16,LSL #3]

  (765) 0x4375ec LDR	X16, [X16, X9,LSL #3]

  (765) 0x4375f0 STR	X12, [X22, X16,LSL #3]

  (765) 0x4375f4 STP	XZR, XZR, [X13, #1016]

  (765) 0x4375f8 STUR	X16, [X15, #504]

  (765) 0x4375fc ADD	X13, X13, #16

  (765) 0x437600 ADD	X12, X12, #2

  (765) 0x437604 LDR	X16, [X28]

  (765) 0x437608 LDR	X16, [X1, X16,LSL #3]

  (765) 0x43760c ADD	X16, X16, X9,LSL #3

  (765) 0x437610 ADD	X9, X9, #2

  (765) 0x437614 LDR	X16, [X16, #8]

  (765) 0x437618 CMP	X10, X9

  (765) 0x43761c STR	X18, [X22, X16,LSL #3]

  (765) 0x437620 STR	X16, [X15], #16

  (765) 0x437624 B.NE	4375e0

0x437628 LDR	X9, [X2, X11,LSL #3]

0x43762c LDR	X10, [X2, X8,LSL #3]

0x437630 B	437644

  (764) 0x437640 ADD	X9, X9, #1

  (764) 0x437644 CMP	X9, X10

  (764) 0x437648 B.GE	437680

  (764) 0x43764c LDR	X12, [X3, X9,LSL #3]

  (764) 0x437650 LDR	X15, [X28]

  (764) 0x437654 LDR	X13, [X4, X12,LSL #3]

  (764) 0x437658 SUB	X15, X15, #1

  (764) 0x43765c CMP	X13, X15

  (764) 0x437660 B.NE	437640

  (764) 0x437664 STR	X11, [X19, X12,LSL #3]

  (764) 0x437668 LDR	X10, [X2, X8,LSL #3]

  (764) 0x43766c B	437640

0x437680 LDR	X9, [X5, X11,LSL #3]

0x437684 LDR	X10, [X5, X8,LSL #3]

0x437688 B	437690

  (763) 0x43768c ADD	X9, X9, #1

  (763) 0x437690 CMP	X9, X10

  (763) 0x437694 B.GE	4376c0

  (763) 0x437698 LDR	X12, [X6, X9,LSL #3]

  (763) 0x43769c LDR	X15, [X28]

  (763) 0x4376a0 LDR	X13, [X7, X12,LSL #3]

  (763) 0x4376a4 SUB	X15, X15, #1

  (763) 0x4376a8 CMP	X13, X15

  (763) 0x4376ac B.NE	43768c

  (763) 0x4376b0 STR	X11, [X20, X12,LSL #3]

  (763) 0x4376b4 LDR	X10, [X5, X8,LSL #3]

  (763) 0x4376b8 B	43768c

0x4376c0 LDUR	X9, [X29, #352]

0x4376c4 MOVI	D2, #0

0x4376c8 LDR	X10, [X9, X11,LSL #3]

0x4376cc LDR	X12, [X9, X8,LSL #3]

0x4376d0 ADD	X13, X10, #1

0x4376d4 STUR	X10, [X29, #464]

0x4376d8 CMP	X13, X12

0x4376dc B.GE	437924

0x4376e0 LDR	X9, [SP, #64]

0x4376e4 MOVI	D1, #0

0x4376e8 LDR	X16, [X9]

0x4376ec LDP	X10, X9, [X29, #960]

0x4376f0 LDR	X25, [X10]

0x4376f4 LDR	X10, [SP, #160]

0x4376f8 LDR	X9, [X9]

0x4376fc LDR	X6, [X10]

0x437700 LDR	X10, [SP, #144]

0x437704 LDR	X4, [X10]

0x437708 LDUR	X10, [X29, #480]

0x43770c LDR	X23, [X10]

0x437710 LDR	X10, [SP, #152]

0x437714 ADD	X5, X4, #8

0x437718 LDR	X27, [X10]

0x43771c LDUR	X10, [X29, #488]

0x437720 ADD	X7, X23, #8

0x437724 LDR	X10, [X10]

0x437728 B	43774c

  (760) 0x43772c LDR	D3, [X6, X13,LSL #3]

  (760) 0x437730 FADD	D1, D3, D1

  (760) 0x437734 HINT	#0

  (760) 0x437738 HINT	#0

  (760) 0x43773c HINT	#0

  (760) 0x437740 ADD	X13, X13, #1

  (760) 0x437744 CMP	X13, X12

  (760) 0x437748 B.EQ	437928

  (760) 0x43774c LDUR	X15, [X29, #496]

  (760) 0x437750 LDR	X0, [X15, X13,LSL #3]

  (760) 0x437754 LDR	X15, [X19, X0,LSL #3]

  (760) 0x437758 CMP	X15, X11

  (760) 0x43775c B.NE	43778c

  (760) 0x437760 ADD	X1, X0, #1

  (760) 0x437764 LDR	X15, [X14, X0,LSL #3]

  (760) 0x437768 LDR	X3, [X14, X1,LSL #3]

  (760) 0x43776c CMP	X3, X15

  (760) 0x437770 B.LE	437858

  (760) 0x437774 SUB	W2, W3, W15

  (760) 0x437778 ADD	X18, X15, #1

  (760) 0x43777c TBNZ	W2, #0, 4377b4

  (760) 0x437780 CMP	X3, X18

  (760) 0x437784 B.NE	4377e8

  (760) 0x437788 B	437858

  (760) 0x43778c LDR	X15, [X16, X0,LSL #3]

  (760) 0x437790 CMN	X15, #3

  (760) 0x437794 B.EQ	437740

  (760) 0x437798 CMP	X25, #1

  (760) 0x43779c B.EQ	43772c

  (760) 0x4377a0 LDR	X15, [X9, X11,LSL #3]

  (760) 0x4377a4 LDR	X18, [X9, X0,LSL #3]

  (760) 0x4377a8 CMP	X15, X18

  (760) 0x4377ac B.EQ	43772c

  (760) 0x4377b0 B	437740

  (760) 0x4377b4 LDR	X2, [X4, X15,LSL #3]

  (760) 0x4377b8 LDR	D0, [X6, X13,LSL #3]

  (760) 0x4377bc LDR	D3, [X23, X15,LSL #3]

  (760) 0x4377c0 FMUL	D0, D3, D0

  (760) 0x4377c4 LDR	X15, [X21, X2,LSL #3]

  (760) 0x4377c8 LDR	D3, [X23, X15,LSL #3]

  (760) 0x4377cc FADD	D2, D0, D2

  (760) 0x4377d0 FADD	D1, D0, D1

  (760) 0x4377d4 FADD	D3, D3, D0

  (760) 0x4377d8 STR	D3, [X23, X15,LSL #3]

  (760) 0x4377dc ORR	X15, XZR, X18

  (760) 0x4377e0 CMP	X3, X18

  (760) 0x4377e4 B.EQ	437858

  (760) 0x4377e8 SUB	X3, X3, X15

  (760) 0x4377ec ADD	X26, X5, X15,LSL #3

  (760) 0x4377f0 ADD	X24, X7, X15,LSL #3

  (760) 0x4377f4 HINT	#0

  (760) 0x4377f8 HINT	#0

  (760) 0x4377fc HINT	#0

    (762) 0x437800 LDP	X15, X18, [X26, #1016]

    (762) 0x437804 LDR	D0, [X6, X13,LSL #3]

    (762) 0x437808 SUBS	X3, X3, #2

    (762) 0x43780c ADD	X26, X26, #16

    (762) 0x437810 LDUR	D3, [X24, #504]

    (762) 0x437814 FMUL	D0, D3, D0

    (762) 0x437818 LDR	X15, [X21, X15,LSL #3]

    (762) 0x43781c LDR	D3, [X23, X15,LSL #3]

    (762) 0x437820 FADD	D2, D0, D2

    (762) 0x437824 FADD	D1, D0, D1

    (762) 0x437828 FADD	D3, D3, D0

    (762) 0x43782c STR	D3, [X23, X15,LSL #3]

    (762) 0x437830 LDR	X15, [X21, X18,LSL #3]

    (762) 0x437834 LDR	D0, [X6, X13,LSL #3]

    (762) 0x437838 LDR	D3, [X24], #16

    (762) 0x43783c FMUL	D0, D3, D0

    (762) 0x437840 LDR	D3, [X23, X15,LSL #3]

    (762) 0x437844 FADD	D2, D0, D2

    (762) 0x437848 FADD	D1, D0, D1

    (762) 0x43784c FADD	D3, D3, D0

    (762) 0x437850 STR	D3, [X23, X15,LSL #3]

    (762) 0x437854 B.NE	437800

  (760) 0x437858 LDR	X15, [X17, X0,LSL #3]

  (760) 0x43785c LDR	X0, [X17, X1,LSL #3]

  (760) 0x437860 CMP	X0, X15

  (760) 0x437864 B.LE	437740

  (760) 0x437868 SUB	W1, W0, W15

  (760) 0x43786c ADD	X18, X15, #1

  (760) 0x437870 TBNZ	W1, #0, 437880

  (760) 0x437874 CMP	X0, X18

  (760) 0x437878 B.EQ	437740

  (760) 0x43787c B	4378b4

  (760) 0x437880 LDR	X1, [X27, X15,LSL #3]

  (760) 0x437884 LDR	D0, [X6, X13,LSL #3]

  (760) 0x437888 LDR	D3, [X10, X15,LSL #3]

  (760) 0x43788c FMUL	D0, D3, D0

  (760) 0x437890 LDR	X15, [X22, X1,LSL #3]

  (760) 0x437894 LDR	D3, [X10, X15,LSL #3]

  (760) 0x437898 FADD	D2, D0, D2

  (760) 0x43789c FADD	D1, D0, D1

  (760) 0x4378a0 FADD	D3, D3, D0

  (760) 0x4378a4 STR	D3, [X10, X15,LSL #3]

  (760) 0x4378a8 ORR	X15, XZR, X18

  (760) 0x4378ac CMP	X0, X18

  (760) 0x4378b0 B.EQ	437740

  (760) 0x4378b4 ADD	X18, X27, #8

  (760) 0x4378b8 SUB	X0, X0, X15

  (760) 0x4378bc ADD	X1, X18, X15,LSL #3

  (760) 0x4378c0 ADD	X18, X10, #8

  (760) 0x4378c4 ADD	X3, X18, X15,LSL #3

    (761) 0x4378c8 LDP	X15, X18, [X1, #1016]

    (761) 0x4378cc LDR	D0, [X6, X13,LSL #3]

    (761) 0x4378d0 SUBS	X0, X0, #2

    (761) 0x4378d4 ADD	X1, X1, #16

    (761) 0x4378d8 LDUR	D3, [X3, #504]

    (761) 0x4378dc FMUL	D0, D3, D0

    (761) 0x4378e0 LDR	X15, [X22, X15,LSL #3]

    (761) 0x4378e4 LDR	D3, [X10, X15,LSL #3]

    (761) 0x4378e8 FADD	D2, D0, D2

    (761) 0x4378ec FADD	D1, D0, D1

    (761) 0x4378f0 FADD	D3, D3, D0

    (761) 0x4378f4 STR	D3, [X10, X15,LSL #3]

    (761) 0x4378f8 LDR	X15, [X22, X18,LSL #3]

    (761) 0x4378fc LDR	D0, [X6, X13,LSL #3]

    (761) 0x437900 LDR	D3, [X3], #16

    (761) 0x437904 FMUL	D0, D3, D0

    (761) 0x437908 LDR	D3, [X10, X15,LSL #3]

    (761) 0x43790c FADD	D2, D0, D2

    (761) 0x437910 FADD	D1, D0, D1

    (761) 0x437914 FADD	D3, D3, D0

    (761) 0x437918 STR	D3, [X10, X15,LSL #3]

    (761) 0x43791c B.NE	4378c8

  (760) 0x437920 B	437740

0x437924 MOVI	D1, #0

0x437928 LDUR	X10, [X29, #344]

0x43792c LDR	X9, [X10, X11,LSL #3]

0x437930 LDR	X10, [X10, X8,LSL #3]

0x437934 CMP	X9, X10

0x437938 B.GE	437aa0

0x43793c LDR	X15, [SP, #128]

0x437940 LDP	X12, X13, [SP, #72]

0x437944 LDR	X3, [X28]

0x437948 LDR	X16, [X15]

0x43794c LDUR	X15, [X29, #448]

0x437950 LDR	X12, [X12]

0x437954 LDR	X13, [X13]

0x437958 LDR	X6, [X15]

0x43795c LDR	X15, [SP, #136]

0x437960 LDR	X23, [X15]

0x437964 LDUR	X15, [X29, #456]

0x437968 LDR	X24, [X15]

0x43796c LDR	X15, [SP, #112]

0x437970 LDR	X25, [X15]

0x437974 LDR	X15, [SP, #88]

0x437978 LDR	X27, [X15]

0x43797c LDR	X15, [SP, #96]

0x437980 LDR	X26, [X15]

0x437984 LDR	X15, [SP, #104]

0x437988 LDR	X0, [X15]

0x43798c LDR	X15, [SP, #120]

0x437990 LDR	X1, [X15]

0x437994 B	4379b4

  (758) 0x4379a0 LDR	D3, [X25, X9,LSL #3]

  (758) 0x4379a4 FADD	D1, D3, D1

  (758) 0x4379a8 ADD	X9, X9, #1

  (758) 0x4379ac CMP	X9, X10

  (758) 0x4379b0 B.EQ	437aa0

  (758) 0x4379b4 ADD	X15, X13, X9,LSL #3

  (758) 0x4379b8 CBZ	X30, 4379c4

  (758) 0x4379bc LDR	X15, [X15]

  (758) 0x4379c0 ADD	X15, X12, X15,LSL #3

  (758) 0x4379c4 LDR	X15, [X15]

  (758) 0x4379c8 TBNZ	X15, #63, 437a6c

  (758) 0x4379cc LDR	X18, [X20, X15,LSL #3]

  (758) 0x4379d0 CMP	X18, X11

  (758) 0x4379d4 B.NE	437a6c

  (758) 0x4379d8 ADD	X18, X26, X15,LSL #3

  (758) 0x4379dc LDR	X18, [X18, #8]

  (758) 0x4379e0 CMP	X18, #1

  (758) 0x4379e4 B.LT	4379a8

  (758) 0x4379e8 UBFM	X15, X15, #61, #60

  (758) 0x4379ec LDR	X2, [X27, X15]

  (758) 0x4379f0 LDR	X15, [X0, X3,LSL #3]

  (758) 0x4379f4 ADD	X4, X18, X2

  (758) 0x4379f8 LDP	X18, X7, [X29, #992]

  (758) 0x4379fc LDR	X5, [X7]

  (758) 0x437a00 LDR	X18, [X18]

  (758) 0x437a04 B	437a30

    (759) 0x437a08 ORN	X7, XZR, X7

    (759) 0x437a0c LDR	X7, [X21, X7,LSL #3]

    (759) 0x437a10 LDR	D3, [X18, X7,LSL #3]

    (759) 0x437a14 FADD	D3, D3, D0

    (759) 0x437a18 STR	D3, [X18, X7,LSL #3]

    (759) 0x437a1c FADD	D2, D0, D2

    (759) 0x437a20 FADD	D1, D0, D1

    (759) 0x437a24 ADD	X2, X2, #1

    (759) 0x437a28 CMP	X2, X4

    (759) 0x437a2c B.GE	4379a8

    (759) 0x437a30 LDR	D0, [X25, X9,LSL #3]

    (759) 0x437a34 LDR	D3, [X1, X2,LSL #3]

    (759) 0x437a38 LDR	X7, [X15, X2,LSL #3]

    (759) 0x437a3c FMUL	D0, D3, D0

    (759) 0x437a40 TBNZ	X7, #63, 437a08

    (759) 0x437a44 LDR	X7, [X22, X7,LSL #3]

    (759) 0x437a48 LDR	D3, [X5, X7,LSL #3]

    (759) 0x437a4c FADD	D3, D3, D0

    (759) 0x437a50 STR	D3, [X5, X7,LSL #3]

    (759) 0x437a54 FADD	D2, D0, D2

    (759) 0x437a58 FADD	D1, D0, D1

    (759) 0x437a5c ADD	X2, X2, #1

    (759) 0x437a60 CMP	X2, X4

    (759) 0x437a64 B.LT	437a30

  (758) 0x437a68 B	4379a8

  (758) 0x437a6c LDR	X18, [X16, X15,LSL #3]

  (758) 0x437a70 CMN	X18, #3

  (758) 0x437a74 B.EQ	4379a8

  (758) 0x437a78 CMP	X6, #1

  (758) 0x437a7c B.EQ	4379a0

  (758) 0x437a80 LDR	X15, [X23, X15,LSL #3]

  (758) 0x437a84 LDR	X18, [X24, X11,LSL #3]

  (758) 0x437a88 CMP	X15, X18

  (758) 0x437a8c B.EQ	4379a0

  (758) 0x437a90 B	4379a8

0x437aa0 LDR	X9, [SP, #184]

0x437aa4 LDUR	X10, [X29, #464]

0x437aa8 LDR	D3, [X9, X10,LSL #3]

0x437aac FMUL	D2, D3, D2

0x437ab0 FCMP	D2, #0

0x437ab4 B.EQ	437ac0

0x437ab8 FNEG	D0, D1

0x437abc FDIV	D0, D0, D2

0x437ac0 LDR	X15, [X14, X11,LSL #3]

0x437ac4 LDR	X9, [X14, X8,LSL #3]

0x437ac8 LDUR	X0, [X29, #424]

0x437acc SUBS	X10, X9, X15

0x437ad0 LDP	X2, X1, [X29, #912]

0x437ad4 LDP	X4, X3, [X29, #896]

0x437ad8 LDP	X6, X5, [X29, #880]

0x437adc LDUR	X7, [X29, #360]

0x437ae0 B.LE	437b54

0x437ae4 CMP	X10, #4

0x437ae8 ORR	X12, XZR, X15

0x437aec B.CC	437b28

0x437af0 LDR	X16, [SP, #8]

0x437af4 AND	X13, X10, #0x0

0x437af8 ADD	X12, X15, X13

0x437afc ADD	X15, X16, X15,LSL #3

0x437b00 AND	X16, X10, #0x0

  (770) 0x437b04 LDP	Q1, Q2, [X15, #2032]

  (770) 0x437b08 SUBS	X16, X16, #4

  (770) 0x437b0c FMUL	V2.2D, V2.2D, V0.D[0]

  (770) 0x437b10 FMUL	V1.2D, V1.2D, V0.D[0]

  (770) 0x437b14 STP	Q1, Q2, [X15, #2032]

  (770) 0x437b18 ADD	X15, X15, #32

  (770) 0x437b1c B.NE	437b04

0x437b20 CMP	X10, X13

0x437b24 B.EQ	437b54

0x437b28 LDR	X10, [SP, #176]

0x437b2c SUB	X9, X9, X12

0x437b30 ADD	X10, X10, X12,LSL #3

0x437b34 HINT	#0

0x437b38 HINT	#0

0x437b3c HINT	#0

  (769) 0x437b40 LDR	D1, [X10]

  (769) 0x437b44 SUBS	X9, X9, #1

  (769) 0x437b48 FMUL	D1, D1, D0

  (769) 0x437b4c STR	D1, [X10], #8

  (769) 0x437b50 B.NE	437b40

0x437b54 LDR	X12, [X17, X11,LSL #3]

0x437b58 LDR	X8, [X17, X8,LSL #3]

0x437b5c SUBS	X9, X8, X12

0x437b60 B.LE	4374a0

0x437b64 CMP	X9, #4

0x437b68 ORR	X10, XZR, X12

0x437b6c B.CC	437ba8

0x437b70 LDR	X13, [SP]

0x437b74 AND	X11, X9, #0x0

0x437b78 ADD	X10, X12, X11

0x437b7c ADD	X12, X13, X12,LSL #3

0x437b80 AND	X13, X9, #0x0

  (768) 0x437b84 LDP	Q1, Q2, [X12, #2032]

  (768) 0x437b88 SUBS	X13, X13, #4

  (768) 0x437b8c FMUL	V2.2D, V2.2D, V0.D[0]

  (768) 0x437b90 FMUL	V1.2D, V1.2D, V0.D[0]

  (768) 0x437b94 STP	Q1, Q2, [X12, #2032]

  (768) 0x437b98 ADD	X12, X12, #32

  (768) 0x437b9c B.NE	437b84

0x437ba0 CMP	X9, X11

0x437ba4 B.EQ	4374a0

0x437ba8 LDR	X9, [SP, #168]

0x437bac SUB	X8, X8, X10

0x437bb0 ADD	X9, X9, X10,LSL #3

0x437bb4 HINT	#0

0x437bb8 HINT	#0

0x437bbc HINT	#0

  (767) 0x437bc0 LDR	D1, [X9]

  (767) 0x437bc4 SUBS	X8, X8, #1

  (767) 0x437bc8 FMUL	D1, D1, D0

  (767) 0x437bcc STR	D1, [X9], #8

  (767) 0x437bd0 B.NE	437bc0

0x437bd4 B	4374a0

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1774 - 1876

--------------------------------------------------------------------------------

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module
►98.95+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.05+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1884	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:785	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.24
CQA speedup if FP arith vectorized	2.31
CQA speedup if fully vectorized	3.96
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.19
Source	par_multi_interp.c:1774-1776,par_multi_interp.c:1779-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1824-1824,par_multi_interp.c:1840-1840,par_multi_interp.c:1865-1865,par_multi_interp.c:1870-1875
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	31.33
CQA cycles if no scalar integer	9.67
CQA cycles if FP arith vectorized	13.58
CQA cycles if fully vectorized	7.92
Front-end cycles	21.25
P0 cycles	10.50
P1 cycles	10.50
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	12.00
P5 cycles	12.00
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	31.33
P11 cycles	31.33
P12 cycles	31.33
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	178.00
Nb uops	170.00
Nb loads	NA
Nb stores	8.00
Nb stack references	23.00
FLOP/cycle	0.06
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.60
Vector-efficiency ratio load	26.67
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	3.24
CQA speedup if FP arith vectorized	2.31
CQA speedup if fully vectorized	3.96
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.19
Source	par_multi_interp.c:1774-1776,par_multi_interp.c:1779-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1824-1824,par_multi_interp.c:1840-1840,par_multi_interp.c:1865-1865,par_multi_interp.c:1870-1875
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	31.33
CQA cycles if no scalar integer	9.67
CQA cycles if FP arith vectorized	13.58
CQA cycles if fully vectorized	7.92
Front-end cycles	21.25
P0 cycles	10.50
P1 cycles	10.50
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	12.00
P5 cycles	12.00
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	31.33
P11 cycles	31.33
P12 cycles	31.33
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	178.00
Nb uops	170.00
Nb loads	NA
Nb stores	8.00
Nb stack references	23.00
FLOP/cycle	0.06
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.60
Vector-efficiency ratio load	26.67
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.19
Source file and lines	par_multi_interp.c:1774-1876
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1774-1876.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1774-1776,1779-1799,1805,1811,1824,1840,1865,1870-1875.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.33 to 9.67 cycles (3.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 31.33 to 7.92 cycles (3.96x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop does not load or store any data.

General properties

nb instructions	178
nb uops	170
loop length	712
used w registers	3
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	4
used q registers	0
used v registers	0
used z registers	0
nb stack references	23

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.25 cycles
front end	21.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.50	10.50	12.00	12.00	12.00	12.00	1.75	1.75	1.75	1.75	31.33	31.33	31.33	4.00	4.00
cycles	10.50	10.50	12.00	12.00	12.00	12.00	1.75	1.75	1.75	1.75	31.33	31.33	31.33	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	21.25
Dispatch	31.33
DIV/SQRT	1.75-3.50
Overall L1	31.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	25%
load	26%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	25%
load	26%
store	25%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.33 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 437aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437bd8 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0xa68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X14, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X10, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437570 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W16, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W16, #0, 437514 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [X21, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X16, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X12, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 437570 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X13, X13, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X15, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X17, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X10, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437628 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W16, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W16, #0, 4375c4 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X1, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X16, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X12, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 437628 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X13, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X13, X13, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X15, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X9, [X2, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X2, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 437644 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x4d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X5, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X5, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 437690 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X10, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437924 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X25, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 43774c <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDUR X10, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437aa0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x930>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X3, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X15, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X15, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4379b4 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x844>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D3, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D2, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMP D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 437ac0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x950>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FNEG D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FDIV D0, D0, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR X15, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X14, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X10, X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDP X2, X1, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X3, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X6, X5, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X7, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B.LE 437b54 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x9e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR X12, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.CC 437b28 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x9b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
AND X13, X10, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X15, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X16, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X16, X10, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 437b54 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x9e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X9, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X12, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X17, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X9, X8, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 4374a0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR X10, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.CC 437ba8 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0xa38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
AND X11, X9, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X13, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X13, X9, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4374a0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
B 4374a0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.19
Source file and lines	par_multi_interp.c:1774-1876
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.33 to 9.67 cycles (3.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop does not load or store any data.

General properties

nb instructions	178
nb uops	170
loop length	712
used w registers	3
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	4
used q registers	0
used v registers	0
used z registers	0
nb stack references	23

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.25 cycles
front end	21.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.50	10.50	12.00	12.00	12.00	12.00	1.75	1.75	1.75	1.75	31.33	31.33	31.33	4.00	4.00
cycles	10.50	10.50	12.00	12.00	12.00	12.00	1.75	1.75	1.75	1.75	31.33	31.33	31.33	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	21.25
Dispatch	31.33
DIV/SQRT	1.75-3.50
Overall L1	31.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	25%
load	26%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	25%
load	26%
store	25%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.33 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 437aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437bd8 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0xa68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X14, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X10, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437570 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W16, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W16, #0, 437514 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [X21, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X16, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X12, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 437570 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X13, X13, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X15, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X17, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X10, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437628 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W16, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W16, #0, 4375c4 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X1, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X16, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X12, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 437628 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X13, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X13, X13, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X15, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X9, [X2, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X2, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 437644 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x4d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X5, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X5, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 437690 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X10, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437924 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X25, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 43774c <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDUR X10, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437aa0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x930>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X3, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X15, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X15, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4379b4 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x844>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D3, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D2, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMP D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 437ac0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x950>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FNEG D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FDIV D0, D0, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR X15, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X14, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X10, X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDP X2, X1, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X3, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X6, X5, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X7, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B.LE 437b54 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x9e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR X12, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.CC 437b28 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x9b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
AND X13, X10, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X15, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X16, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X16, X10, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 437b54 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x9e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X9, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X12, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X17, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X9, X8, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 4374a0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR X10, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.CC 437ba8 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0xa38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
AND X11, X9, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X13, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X13, X9, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4374a0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
B 4374a0 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code