OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.5	Module: exec	Source: par_multi_interp.c:891-1134 [...]	Coverage (incl. loops): 1.19% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 891 - 1134

--------------------------------------------------------------------------------

891:       #pragma omp parallel private(i,my_thread_num,num_threads,thread_start,thread_stop,cnt_nz,cnt_nz_offd,i1,j,j1,j_start,j_end,k1,k,P_marker,P_marker_offd)

[...]

900:           my_thread_num = hypre_GetThreadNum();

901:           num_threads = hypre_NumActiveThreads();

902:           thread_start = (pass_length/num_threads)*my_thread_num;

903:           if (my_thread_num == num_threads-1)

904:           {  thread_stop = pass_length; }

905:           else

906:           {  thread_stop = (pass_length/num_threads)*(my_thread_num+1); }

907:           thread_start += pass_pointer[pass];

908:           thread_stop += pass_pointer[pass];

909:

910:           /* Local initializations */

911:           cnt_nz = 0;

912:           cnt_nz_offd = 0;

913:

914:           /* This block of code is to go to the top of the parallel region starting before

915:            * the loop over num_passes. */

916:           P_marker = hypre_CTAlloc(HYPRE_Int, n_coarse); /* marks points to see if they're counted */

917:           for (i=0; i < n_coarse; i++)

918:           {   P_marker[i] = -1; }

919:           if (new_num_cols_offd == local_index+1)

920:           {

921:              P_marker_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd);

922:              for (i=0; i < new_num_cols_offd; i++)

923:              {   P_marker_offd[i] = -1; }

924:           }

925:           else if (n_coarse_offd)

926:           {

927:              P_marker_offd = hypre_CTAlloc(HYPRE_Int, n_coarse_offd);

[...]

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

[...]

1008:           if(my_thread_num == 0)

1009:           {   max_num_threads[0] = num_threads; }

1010:           cnt_nz_offd_per_thread[my_thread_num] = cnt_nz_offd;

1011:           cnt_nz_per_thread[my_thread_num] = cnt_nz;

1012: #ifdef HYPRE_USING_OPENMP

1013: #pragma omp barrier

1014: #endif

1015:           if(my_thread_num == 0)

1016:           {

1017:               for(i = 1; i < max_num_threads[0]; i++)

1018:               {

1019:                   cnt_nz_offd_per_thread[i] += cnt_nz_offd_per_thread[i-1];

1020:                   cnt_nz_per_thread[i] += cnt_nz_per_thread[i-1];

1021:               }

1022:           }

1023: #ifdef HYPRE_USING_OPENMP

1024: #pragma omp barrier

1025: #endif

1026:           if(my_thread_num > 0)

1027:           {

1028:               /* update this thread's section of P_diag_start and P_offd_start

1029:                * with the num of nz's counted by previous threads */

1030:               for (i=thread_start; i < thread_stop; i++)

1031:                {

1032:                    i1 = pass_array[i];

1033:                    P_diag_start[i1] += cnt_nz_per_thread[my_thread_num-1];

1034:                    P_offd_start[i1] += cnt_nz_offd_per_thread[my_thread_num-1];

[...]

1040:               cnt_nz = cnt_nz_per_thread[max_num_threads[0]-1];

1041:               cnt_nz_offd = cnt_nz_offd_per_thread[max_num_threads[0]-1];

1042:

1043:               /* Updated total nz count */

1044:               total_nz += cnt_nz;

1045:               total_nz_offd += cnt_nz_offd;

1046:

1047:               /* Allocate P_diag_pass and P_offd_pass for all threads */

1048:               P_diag_pass[pass] = hypre_CTAlloc(HYPRE_Int, cnt_nz);

1049:               if (cnt_nz_offd)

1050:                  P_offd_pass[pass] = hypre_CTAlloc(HYPRE_Int, cnt_nz_offd);

1051:               else if (num_procs > 1)

1052:                  P_offd_pass[pass] = NULL;

1053:           }

1054: #ifdef HYPRE_USING_OPENMP

1055: #pragma omp barrier

1056: #endif

1057:

1058:           /* offset cnt_nz and cnt_nz_offd to point to the starting

1059:            * point in P_diag_pass and P_offd_pass for each thread */

1060:           if(my_thread_num > 0)

1061:           {

1062:               cnt_nz = cnt_nz_per_thread[my_thread_num-1];

1063:               cnt_nz_offd = cnt_nz_offd_per_thread[my_thread_num-1];

1064:           }

1065:           else

1066:           {

1067:               cnt_nz = 0;

1068:               cnt_nz_offd = 0;

1069:           }

1070:

1071:           /* Set P_diag_pass and P_offd_pass */

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

[...]

1132:           hypre_TFree(P_marker);

1133:           if ( (n_coarse_offd) || (new_num_cols_offd  == local_index+1) )

1134:           {    hypre_TFree(P_marker_offd); }

0x455cac STP	X29, X30, [SP, #736]!

0x455cb0 ORR	X3, XZR, X0

0x455cb4 ADD	X29, SP, #0

0x455cb8 STP	X19, X20, [SP, #16]

0x455cbc STP	X21, X22, [SP, #32]

0x455cc0 STP	X23, X24, [SP, #48]

0x455cc4 STP	X25, X26, [SP, #64]

0x455cc8 STP	X27, X28, [SP, #80]

0x455ccc LDP	X1, X18, [X3, #64]

0x455cd0 LDP	X10, X8, [X3, #88]

0x455cd4 LDP	X11, X26, [X0, #16]

0x455cd8 LDP	X12, X27, [X0]

0x455cdc LDP	X23, X21, [X0, #32]

0x455ce0 STR	X1, [SP, #128]

0x455ce4 LDR	X0, [X0, #48]

0x455ce8 STP	X8, X10, [SP, #240]

0x455cec STP	X18, X11, [SP, #256]

0x455cf0 LDR	X2, [X3, #56]

0x455cf4 STR	X0, [SP, #208]

0x455cf8 LDR	X4, [X3, #80]

0x455cfc STR	X3, [SP, #216]

0x455d00 LDR	X5, [X3, #104]

0x455d04 STR	X2, [SP, #104]

0x455d08 STR	X12, [SP, #272]

0x455d0c STR	X4, [SP, #136]

0x455d10 STR	X5, [SP, #120]

0x455d14 LDR	X6, [X3, #112]

0x455d18 LDP	X20, X7, [X3, #200]

0x455d1c LDP	X14, X13, [X3, #216]

0x455d20 LDP	X22, X28, [X3, #128]

0x455d24 LDP	X25, X24, [X3, #152]

0x455d28 STP	X14, X7, [SP, #224]

0x455d2c LDR	X9, [X3, #144]

0x455d30 STR	X6, [SP, #112]

0x455d34 LDR	X15, [X3, #184]

0x455d38 STR	X13, [SP, #144]

0x455d3c LDR	X16, [X3, #192]

0x455d40 STR	X22, [SP, #160]

0x455d44 UBFM	X22, X22, #61, #60

0x455d48 STR	X9, [SP, #200]

0x455d4c STR	X15, [SP, #96]

0x455d50 STR	X16, [SP, #192]

0x455d54 BL	52c0a0

0x455d58 STR	X0, [SP, #152]

0x455d5c BL	52c080

0x455d60 SDIV	X11, X20, X0

0x455d64 LDR	X1, [SP, #128]

0x455d68 SUB	X12, X0, #1

0x455d6c STR	X0, [SP, #280]

0x455d70 ORR	X0, XZR, X28

0x455d74 LDR	X18, [SP, #152]

0x455d78 LDR	X10, [X1, X22]

0x455d7c MOVZ	X1, #8

0x455d80 CMP	X18, X12

0x455d84 MUL	X8, X18, X11

0x455d88 ADD	X2, X11, X8

0x455d8c ADD	X5, X8, X10

0x455d90 CSEL	X4, X2, X20, #1

0x455d94 ADD	X6, X4, X10

0x455d98 STR	X8, [SP, #168]

0x455d9c STR	X5, [SP, #128]

0x455da0 STR	X6, [SP, #176]

0x455da4 STR	X4, [SP, #184]

0x455da8 BL	529428

0x455dac CMP	X28, #0

0x455db0 LDR	X9, [SP, #128]

0x455db4 ORR	X20, XZR, X0

0x455db8 LDP	X3, X14, [SP, #216]

0x455dbc LDP	X4, X8, [SP, #232]

0x455dc0 LDP	X10, X18, [SP, #248]

0x455dc4 LDP	X11, X12, [SP, #264]

0x455dc8 LDR	X13, [SP, #144]

0x455dcc B.LE	455e0c

0x455dd0 UBFM	X2, X28, #61, #60

0x455dd4 MOVZ	W1, #255

0x455dd8 STR	X13, [SP, #128]

0x455ddc STR	X14, [SP, #144]

0x455de0 STP	X4, X8, [SP, #216]

0x455de4 STP	X10, X18, [SP, #232]

0x455de8 STP	X11, X12, [SP, #248]

0x455dec STP	X9, X3, [SP, #264]

0x455df0 BL	410340

0x455df4 LDR	X13, [SP, #128]

0x455df8 LDP	X4, X8, [SP, #216]

0x455dfc LDP	X10, X18, [SP, #232]

0x455e00 LDP	X11, X12, [SP, #248]

0x455e04 LDP	X9, X3, [SP, #264]

0x455e08 LDR	X14, [SP, #144]

0x455e0c LDR	X17, [SP, #96]

0x455e10 LDR	X30, [SP, #192]

0x455e14 ADD	X0, X17, #1

0x455e18 STR	X0, [SP, #216]

0x455e1c CMP	X30, X0

0x455e20 B.EQ	4570f0

0x455e24 LDR	X0, [SP, #200]

0x455e28 CBNZ	X0, 457074

0x455e2c LDR	X17, [SP, #184]

0x455e30 ADD	X1, X10, X22

0x455e34 ORR	X15, XZR, X9

0x455e38 LDP	X7, X16, [SP, #160]

0x455e3c MOVZ	X5, #0

0x455e40 MOVZ	X6, #0

0x455e44 ADD	X2, X8, X22

0x455e48 STR	X1, [SP, #144]

0x455e4c SUB	X7, X7, #1

0x455e50 CMP	X17, X16

0x455e54 B.LE	45637c

0x455e58 LDR	X16, [SP, #136]

0x455e5c ORR	X30, XZR, X2

0x455e60 STP	X13, X14, [SP, #224]

0x455e64 LDR	X13, [SP, #208]

0x455e68 STP	X10, X9, [SP, #256]

0x455e6c LDR	X9, [SP, #176]

0x455e70 STP	X4, X8, [SP, #240]

0x455e74 STR	X3, [SP, #272]

0x455e78 HINT	#0

0x455e7c HINT	#0

(670) 0x455e80 LDR	X14, [SP, #104]

(670) 0x455e84 LDR	X0, [X14, X15,LSL #3]

(670) 0x455e88 UBFM	X10, X0, #61, #60

(670) 0x455e8c ADD	X1, X10, #8

(670) 0x455e90 STR	X6, [X18, X10]

(670) 0x455e94 ADD	X4, X12, X1

(670) 0x455e98 STR	X5, [X16, X10]

(670) 0x455e9c LDR	X3, [X12, X10]

(670) 0x455ea0 LDR	X8, [X12, X1]

(670) 0x455ea4 CMP	X3, X8

(670) 0x455ea8 B.GE	456214

(670) 0x455eac ORR	X28, XZR, X24

(670) 0x455eb0 STR	X9, [SP, #128]

(670) 0x455eb4 ORR	X9, XZR, X4

(670) 0x455eb8 B	455ec8

  (673) 0x455ebc ADD	X3, X3, #1

  (673) 0x455ec0 CMP	X3, X8

  (673) 0x455ec4 B.GE	45620c

  (673) 0x455ec8 LDR	X24, [X27, X3,LSL #3]

  (673) 0x455ecc UBFM	X2, X24, #61, #60

  (673) 0x455ed0 LDR	X17, [X25, X2]

  (673) 0x455ed4 STR	X2, [SP, #96]

  (673) 0x455ed8 CMP	X17, X7

  (673) 0x455edc B.NE	455ebc

  (673) 0x455ee0 ADD	X17, X2, #8

  (673) 0x455ee4 LDR	X8, [X18, X2]

  (673) 0x455ee8 LDR	X14, [X23, X17]

  (673) 0x455eec ADD	X4, X8, X14

  (673) 0x455ef0 CMP	X8, X4

  (673) 0x455ef4 B.GE	456070

  (673) 0x455ef8 LDR	X24, [SP, #144]

  (673) 0x455efc UBFM	X2, X8, #61, #60

  (673) 0x455f00 LDUR	X24, [X24, #504]

  (673) 0x455f04 ADD	X14, X24, X4,LSL #3

  (673) 0x455f08 ADD	X4, X24, X8,LSL #3

  (673) 0x455f0c SUB	X8, X14, X4

  (673) 0x455f10 SUB	X8, X8, #8

  (673) 0x455f14 UBFM	X8, X8, #3, #63

  (673) 0x455f18 ADD	X8, X8, #1

  (673) 0x455f1c ANDS	X8, X8, #0x3

  (673) 0x455f20 B.EQ	455fc0

  (673) 0x455f24 CMP	X8, #1

  (673) 0x455f28 B.EQ	455f8c

  (673) 0x455f2c CMP	X8, #2

  (673) 0x455f30 B.EQ	455f60

  (673) 0x455f34 LDR	X24, [X24, X2]

  (673) 0x455f38 UBFM	X2, X24, #61, #60

  (673) 0x455f3c LDR	X8, [X20, X2]

  (673) 0x455f40 CMP	X0, X8

  (673) 0x455f44 B.EQ	455f5c

  (673) 0x455f48 LDR	X24, [X23, X1]

  (673) 0x455f4c ADD	X6, X6, #1

  (673) 0x455f50 ADD	X8, X24, #1

  (673) 0x455f54 STR	X8, [X23, X1]

  (673) 0x455f58 STR	X0, [X20, X2]

  (673) 0x455f5c ADD	X4, X4, #8

  (673) 0x455f60 LDR	X2, [X4]

  (673) 0x455f64 UBFM	X8, X2, #61, #60

  (673) 0x455f68 LDR	X24, [X20, X8]

  (673) 0x455f6c CMP	X0, X24

  (673) 0x455f70 B.EQ	455f88

  (673) 0x455f74 LDR	X2, [X23, X1]

  (673) 0x455f78 ADD	X6, X6, #1

  (673) 0x455f7c ADD	X24, X2, #1

  (673) 0x455f80 STR	X24, [X23, X1]

  (673) 0x455f84 STR	X0, [X20, X8]

  (673) 0x455f88 ADD	X4, X4, #8

  (673) 0x455f8c LDR	X8, [X4]

  (673) 0x455f90 UBFM	X2, X8, #61, #60

  (673) 0x455f94 LDR	X24, [X20, X2]

  (673) 0x455f98 CMP	X0, X24

  (673) 0x455f9c B.EQ	455fb4

  (673) 0x455fa0 LDR	X8, [X23, X1]

  (673) 0x455fa4 ADD	X6, X6, #1

  (673) 0x455fa8 ADD	X24, X8, #1

  (673) 0x455fac STR	X24, [X23, X1]

  (673) 0x455fb0 STR	X0, [X20, X2]

  (673) 0x455fb4 ADD	X4, X4, #8

  (673) 0x455fb8 CMP	X14, X4

  (673) 0x455fbc B.EQ	456070

    (675) 0x455fc0 LDR	X2, [X4]

    (675) 0x455fc4 ADD	X8, X4, #8

    (675) 0x455fc8 UBFM	X2, X2, #61, #60

    (675) 0x455fcc LDR	X24, [X20, X2]

    (675) 0x455fd0 CMP	X0, X24

    (675) 0x455fd4 B.EQ	455fec

    (675) 0x455fd8 LDR	X24, [X23, X1]

    (675) 0x455fdc ADD	X6, X6, #1

    (675) 0x455fe0 ADD	X24, X24, #1

    (675) 0x455fe4 STR	X24, [X23, X1]

    (675) 0x455fe8 STR	X0, [X20, X2]

    (675) 0x455fec LDR	X4, [X4, #8]

    (675) 0x455ff0 UBFM	X2, X4, #61, #60

    (675) 0x455ff4 LDR	X24, [X20, X2]

    (675) 0x455ff8 CMP	X0, X24

    (675) 0x455ffc B.EQ	456014

    (675) 0x456000 LDR	X4, [X23, X1]

    (675) 0x456004 ADD	X6, X6, #1

    (675) 0x456008 ADD	X24, X4, #1

    (675) 0x45600c STR	X24, [X23, X1]

    (675) 0x456010 STR	X0, [X20, X2]

    (675) 0x456014 LDR	X2, [X8, #8]

    (675) 0x456018 ADD	X4, X8, #24

    (675) 0x45601c UBFM	X2, X2, #61, #60

    (675) 0x456020 LDR	X24, [X20, X2]

    (675) 0x456024 CMP	X0, X24

    (675) 0x456028 B.EQ	456040

    (675) 0x45602c LDR	X24, [X23, X1]

    (675) 0x456030 ADD	X6, X6, #1

    (675) 0x456034 ADD	X24, X24, #1

    (675) 0x456038 STR	X24, [X23, X1]

    (675) 0x45603c STR	X0, [X20, X2]

    (675) 0x456040 LDR	X8, [X8, #16]

    (675) 0x456044 UBFM	X2, X8, #61, #60

    (675) 0x456048 LDR	X24, [X20, X2]

    (675) 0x45604c CMP	X0, X24

    (675) 0x456050 B.EQ	456068

    (675) 0x456054 LDR	X8, [X23, X1]

    (675) 0x456058 ADD	X6, X6, #1

    (675) 0x45605c ADD	X24, X8, #1

    (675) 0x456060 STR	X24, [X23, X1]

    (675) 0x456064 STR	X0, [X20, X2]

    (675) 0x456068 CMP	X14, X4

    (675) 0x45606c B.NE	455fc0

  (673) 0x456070 LDR	X14, [SP, #96]

  (673) 0x456074 LDR	X17, [X21, X17]

  (673) 0x456078 LDR	X4, [X16, X14]

  (673) 0x45607c ADD	X2, X4, X17

  (673) 0x456080 CMP	X4, X2

  (673) 0x456084 B.GE	4561fc

  (673) 0x456088 LDUR	X17, [X30, #504]

  (673) 0x45608c UBFM	X24, X4, #61, #60

  (673) 0x456090 ADD	X8, X17, X2,LSL #3

  (673) 0x456094 ADD	X2, X17, X4,LSL #3

  (673) 0x456098 SUB	X14, X8, X2

  (673) 0x45609c SUB	X4, X14, #8

  (673) 0x4560a0 UBFM	X14, X4, #3, #63

  (673) 0x4560a4 ADD	X4, X14, #1

  (673) 0x4560a8 ANDS	X14, X4, #0x3

  (673) 0x4560ac B.EQ	45614c

  (673) 0x4560b0 CMP	X14, #1

  (673) 0x4560b4 B.EQ	456118

  (673) 0x4560b8 CMP	X14, #2

  (673) 0x4560bc B.EQ	4560ec

  (673) 0x4560c0 LDR	X24, [X17, X24]

  (673) 0x4560c4 UBFM	X17, X24, #61, #60

  (673) 0x4560c8 LDR	X4, [X19, X17]

  (673) 0x4560cc CMP	X0, X4

  (673) 0x4560d0 B.EQ	4560e8

  (673) 0x4560d4 LDR	X14, [X21, X1]

  (673) 0x4560d8 ADD	X5, X5, #1

  (673) 0x4560dc ADD	X24, X14, #1

  (673) 0x4560e0 STR	X24, [X21, X1]

  (673) 0x4560e4 STR	X0, [X19, X17]

  (673) 0x4560e8 ADD	X2, X2, #8

  (673) 0x4560ec LDR	X17, [X2]

  (673) 0x4560f0 UBFM	X4, X17, #61, #60

  (673) 0x4560f4 LDR	X14, [X19, X4]

  (673) 0x4560f8 CMP	X0, X14

  (673) 0x4560fc B.EQ	456114

  (673) 0x456100 LDR	X24, [X21, X1]

  (673) 0x456104 ADD	X5, X5, #1

  (673) 0x456108 ADD	X17, X24, #1

  (673) 0x45610c STR	X17, [X21, X1]

  (673) 0x456110 STR	X0, [X19, X4]

  (673) 0x456114 ADD	X2, X2, #8

  (673) 0x456118 LDR	X4, [X2]

  (673) 0x45611c UBFM	X24, X4, #61, #60

  (673) 0x456120 LDR	X14, [X19, X24]

  (673) 0x456124 CMP	X0, X14

  (673) 0x456128 B.EQ	456140

  (673) 0x45612c LDR	X17, [X21, X1]

  (673) 0x456130 ADD	X5, X5, #1

  (673) 0x456134 ADD	X4, X17, #1

  (673) 0x456138 STR	X4, [X21, X1]

  (673) 0x45613c STR	X0, [X19, X24]

  (673) 0x456140 ADD	X2, X2, #8

  (673) 0x456144 CMP	X2, X8

  (673) 0x456148 B.EQ	4561fc

    (674) 0x45614c LDR	X14, [X2]

    (674) 0x456150 ADD	X24, X2, #8

    (674) 0x456154 UBFM	X4, X14, #61, #60

    (674) 0x456158 LDR	X17, [X19, X4]

    (674) 0x45615c CMP	X0, X17

    (674) 0x456160 B.EQ	456178

    (674) 0x456164 LDR	X14, [X21, X1]

    (674) 0x456168 ADD	X5, X5, #1

    (674) 0x45616c ADD	X17, X14, #1

    (674) 0x456170 STR	X17, [X21, X1]

    (674) 0x456174 STR	X0, [X19, X4]

    (674) 0x456178 LDR	X2, [X2, #8]

    (674) 0x45617c UBFM	X14, X2, #61, #60

    (674) 0x456180 LDR	X4, [X19, X14]

    (674) 0x456184 CMP	X0, X4

    (674) 0x456188 B.EQ	4561a0

    (674) 0x45618c LDR	X17, [X21, X1]

    (674) 0x456190 ADD	X5, X5, #1

    (674) 0x456194 ADD	X2, X17, #1

    (674) 0x456198 STR	X2, [X21, X1]

    (674) 0x45619c STR	X0, [X19, X14]

    (674) 0x4561a0 LDR	X14, [X24, #8]

    (674) 0x4561a4 ADD	X2, X24, #24

    (674) 0x4561a8 UBFM	X4, X14, #61, #60

    (674) 0x4561ac LDR	X17, [X19, X4]

    (674) 0x4561b0 CMP	X0, X17

    (674) 0x4561b4 B.EQ	4561cc

    (674) 0x4561b8 LDR	X14, [X21, X1]

    (674) 0x4561bc ADD	X5, X5, #1

    (674) 0x4561c0 ADD	X17, X14, #1

    (674) 0x4561c4 STR	X17, [X21, X1]

    (674) 0x4561c8 STR	X0, [X19, X4]

    (674) 0x4561cc LDR	X24, [X24, #16]

    (674) 0x4561d0 UBFM	X4, X24, #61, #60

    (674) 0x4561d4 LDR	X14, [X19, X4]

    (674) 0x4561d8 CMP	X0, X14

    (674) 0x4561dc B.EQ	4561f4

    (674) 0x4561e0 LDR	X17, [X21, X1]

    (674) 0x4561e4 ADD	X5, X5, #1

    (674) 0x4561e8 ADD	X24, X17, #1

    (674) 0x4561ec STR	X24, [X21, X1]

    (674) 0x4561f0 STR	X0, [X19, X4]

    (674) 0x4561f4 CMP	X2, X8

    (674) 0x4561f8 B.NE	45614c

  (673) 0x4561fc LDR	X8, [X9]

  (673) 0x456200 ADD	X3, X3, #1

  (673) 0x456204 CMP	X3, X8

  (673) 0x456208 B.LT	455ec8

(670) 0x45620c LDR	X9, [SP, #128]

(670) 0x456210 ORR	X24, XZR, X28

(670) 0x456214 LDR	X3, [X11, X10]

(670) 0x456218 ADD	X10, X11, X1

(670) 0x45621c LDR	X4, [X11, X1]

(670) 0x456220 CMP	X3, X4

(670) 0x456224 B.GE	456360

(670) 0x456228 LDP	X14, X28, [SP, #112]

(670) 0x45622c ORR	X2, XZR, X10

(670) 0x456230 B	456240

  (671) 0x456234 ADD	X3, X3, #1

  (671) 0x456238 CMP	X3, X4

  (671) 0x45623c B.GE	456360

  (671) 0x456240 LDR	X17, [X26, X3,LSL #3]

  (671) 0x456244 UBFM	X8, X17, #61, #60

  (671) 0x456248 LDR	X10, [X24, X8]

  (671) 0x45624c CMP	X10, X7

  (671) 0x456250 B.NE	456234

  (671) 0x456254 ADD	X17, X14, X8

  (671) 0x456258 LDR	X8, [X13, X8]

  (671) 0x45625c LDR	X10, [X17, #8]

  (671) 0x456260 ADD	X10, X8, X10

  (671) 0x456264 CMP	X8, X10

  (671) 0x456268 B.GE	456234

  (671) 0x45626c LDR	X17, [X28, X22]

  (671) 0x456270 UBFM	X4, X8, #61, #60

  (671) 0x456274 STR	X4, [SP, #96]

  (671) 0x456278 ADD	X10, X17, X10,LSL #3

  (671) 0x45627c ADD	X4, X17, X8,LSL #3

  (671) 0x456280 SUB	X8, X10, X4

  (671) 0x456284 SUB	X8, X8, #8

  (671) 0x456288 UBFM	X8, X8, #3, #63

  (671) 0x45628c ADD	X8, X8, #1

  (671) 0x456290 ANDS	X8, X8, #0x3

  (671) 0x456294 B.EQ	45659c

  (671) 0x456298 CMP	X8, #1

  (671) 0x45629c B.EQ	45630c

  (671) 0x4562a0 CMP	X8, #2

  (671) 0x4562a4 B.EQ	4562dc

  (671) 0x4562a8 LDR	X8, [SP, #96]

  (671) 0x4562ac LDR	X17, [X17, X8]

  (671) 0x4562b0 TBNZ	X17, #63, 4566bc

  (671) 0x4562b4 UBFM	X8, X17, #61, #60

  (671) 0x4562b8 LDR	X17, [X19, X8]

  (671) 0x4562bc CMP	X0, X17

  (671) 0x4562c0 B.EQ	4562d8

  (671) 0x4562c4 LDR	X17, [X21, X1]

  (671) 0x4562c8 ADD	X5, X5, #1

  (671) 0x4562cc ADD	X17, X17, #1

  (671) 0x4562d0 STR	X17, [X21, X1]

  (671) 0x4562d4 STR	X0, [X19, X8]

  (671) 0x4562d8 ADD	X4, X4, #8

  (671) 0x4562dc LDR	X8, [X4]

  (671) 0x4562e0 TBNZ	X8, #63, 456690

  (671) 0x4562e4 UBFM	X8, X8, #61, #60

  (671) 0x4562e8 LDR	X17, [X19, X8]

  (671) 0x4562ec CMP	X0, X17

  (671) 0x4562f0 B.EQ	456308

  (671) 0x4562f4 LDR	X17, [X21, X1]

  (671) 0x4562f8 ADD	X5, X5, #1

  (671) 0x4562fc ADD	X17, X17, #1

  (671) 0x456300 STR	X17, [X21, X1]

  (671) 0x456304 STR	X0, [X19, X8]

  (671) 0x456308 ADD	X4, X4, #8

  (671) 0x45630c LDR	X8, [X4]

  (671) 0x456310 TBNZ	X8, #63, 456664

  (671) 0x456314 UBFM	X8, X8, #61, #60

  (671) 0x456318 LDR	X17, [X19, X8]

  (671) 0x45631c CMP	X0, X17

  (671) 0x456320 B.EQ	456338

  (671) 0x456324 LDR	X17, [X21, X1]

  (671) 0x456328 ADD	X5, X5, #1

  (671) 0x45632c ADD	X17, X17, #1

  (671) 0x456330 STR	X17, [X21, X1]

  (671) 0x456334 STR	X0, [X19, X8]

  (671) 0x456338 ADD	X4, X4, #8

  (671) 0x45633c CMP	X4, X10

  (671) 0x456340 B.NE	45659c

  (671) 0x456344 LDR	X4, [X2]

  (671) 0x456348 ADD	X3, X3, #1

  (671) 0x45634c CMP	X3, X4

  (671) 0x456350 B.LT	456240

(670) 0x456354 HINT	#0

(670) 0x456358 HINT	#0

(670) 0x45635c HINT	#0

(670) 0x456360 ADD	X15, X15, #1

(670) 0x456364 CMP	X9, X15

(670) 0x456368 B.GT	455e80

0x45636c LDR	X3, [SP, #272]

0x456370 LDP	X13, X14, [SP, #224]

0x456374 LDP	X4, X8, [SP, #240]

0x456378 LDP	X10, X9, [SP, #256]

0x45637c STP	X8, X10, [SP, #224]

0x456380 LDR	X17, [SP, #152]

0x456384 STP	X18, X11, [SP, #240]

0x456388 STP	X12, X9, [SP, #256]

0x45638c STR	X3, [SP, #272]

0x456390 CBNZ	X17, 4566e8

0x456394 LDR	X11, [SP, #280]

0x456398 ORR	X18, XZR, X13

0x45639c ORR	X28, XZR, X14

0x4563a0 STR	X14, [SP, #128]

0x4563a4 STR	X11, [X4]

0x4563a8 STR	X5, [X18], #504

0x4563ac STR	X6, [X28], #504

0x4563b0 STR	X18, [SP, #96]

0x4563b4 STP	X4, X13, [SP, #144]

0x4563b8 BL	410120

0x4563bc LDP	X4, X6, [SP, #144]

0x4563c0 MOVZ	X7, #1

0x4563c4 LDP	X8, X10, [SP, #224]

0x4563c8 LDP	X15, X13, [SP, #240]

0x4563cc LDP	X12, X9, [SP, #256]

0x4563d0 LDR	X2, [X4]

0x4563d4 LDR	X0, [SP, #96]

0x4563d8 LDR	X1, [SP, #128]

0x4563dc LDR	X3, [SP, #272]

0x4563e0 CMP	X2, X7

0x4563e4 B.LE	456418

(669) 0x4563e8 LDR	X30, [X6, X7,LSL #3]

(669) 0x4563ec LDR	X5, [X0, X7,LSL #3]

(669) 0x4563f0 ADD	X16, X30, X5

(669) 0x4563f4 STR	X16, [X6, X7,LSL #3]

(669) 0x4563f8 LDR	X17, [X1, X7,LSL #3]

(669) 0x4563fc LDR	X14, [X28, X7,LSL #3]

(669) 0x456400 ADD	X18, X17, X14

(669) 0x456404 STR	X18, [X1, X7,LSL #3]

(669) 0x456408 ADD	X7, X7, #1

(669) 0x45640c LDR	X11, [X4]

(669) 0x456410 CMP	X11, X7

(669) 0x456414 B.GT	4563e8

0x456418 STR	X6, [SP, #96]

0x45641c STR	X1, [SP, #128]

0x456420 STP	X4, X8, [SP, #144]

0x456424 STP	X10, X15, [SP, #224]

0x456428 STP	X13, X12, [SP, #240]

0x45642c STP	X9, X3, [SP, #256]

0x456430 BL	410120

0x456434 LDR	X13, [SP, #96]

0x456438 LDP	X7, X8, [SP, #144]

0x45643c LDP	X10, X18, [SP, #224]

0x456440 LDP	X11, X12, [SP, #240]

0x456444 LDP	X9, X15, [SP, #256]

0x456448 LDR	X14, [SP, #128]

0x45644c MOVZ	X1, #8

0x456450 STR	X8, [SP, #96]

0x456454 LDR	X28, [X7]

0x456458 STR	X10, [SP, #128]

0x45645c LDR	X6, [X15, #120]

0x456460 STR	X15, [SP, #240]

0x456464 LDR	X3, [X15, #176]

0x456468 UBFM	X0, X28, #61, #60

0x45646c SUB	X4, X0, #8

0x456470 LDR	X0, [X14, X4]

0x456474 LDR	X28, [X13, X4]

0x456478 ADD	X30, X6, X0

0x45647c ADD	X2, X3, X28

0x456480 STR	X30, [X15, #120]

0x456484 STR	X2, [X15, #176]

0x456488 STP	X18, X11, [SP, #144]

0x45648c STP	X12, X9, [SP, #224]

0x456490 BL	529428

0x456494 LDR	X13, [SP, #128]

0x456498 LDP	X14, X7, [SP, #144]

0x45649c LDP	X8, X10, [SP, #224]

0x4564a0 STR	X0, [X13, X22]

0x4564a4 LDR	X5, [SP, #96]

0x4564a8 CBNZ	X28, 457168

0x4564ac LDR	X1, [SP, #240]

0x4564b0 LDR	X16, [X1, #168]

0x4564b4 LDR	X17, [X16]

0x4564b8 CMP	X17, #1

0x4564bc B.LE	4571ac

0x4564c0 STR	XZR, [X5, X22]

0x4564c4 BL	410120

0x4564c8 LDR	X8, [SP, #96]

0x4564cc LDP	X15, X11, [SP, #144]

0x4564d0 LDP	X12, X9, [SP, #224]

0x4564d4 LDR	X10, [SP, #128]

0x4564d8 MOVZ	X2, #0

0x4564dc MOVZ	X4, #0

0x4564e0 B	456920

    (672) 0x4564e4 UBFM	X8, X8, #61, #60

    (672) 0x4564e8 LDR	X17, [X19, X8]

    (672) 0x4564ec CMP	X0, X17

    (672) 0x4564f0 B.EQ	456508

    (672) 0x4564f4 LDR	X17, [X21, X1]

    (672) 0x4564f8 ADD	X5, X5, #1

    (672) 0x4564fc ADD	X17, X17, #1

    (672) 0x456500 STR	X17, [X21, X1]

    (672) 0x456504 STR	X0, [X19, X8]

    (672) 0x456508 LDR	X8, [X4, #8]

    (672) 0x45650c ADD	X4, X4, #8

    (672) 0x456510 TBNZ	X8, #63, 4565d8

    (672) 0x456514 UBFM	X8, X8, #61, #60

    (672) 0x456518 LDR	X17, [X19, X8]

    (672) 0x45651c CMP	X0, X17

    (672) 0x456520 B.EQ	456538

    (672) 0x456524 LDR	X17, [X21, X1]

    (672) 0x456528 ADD	X5, X5, #1

    (672) 0x45652c ADD	X17, X17, #1

    (672) 0x456530 STR	X17, [X21, X1]

    (672) 0x456534 STR	X0, [X19, X8]

    (672) 0x456538 LDR	X8, [X4, #8]

    (672) 0x45653c TBNZ	X8, #63, 456608

    (672) 0x456540 UBFM	X8, X8, #61, #60

    (672) 0x456544 LDR	X17, [X19, X8]

    (672) 0x456548 CMP	X0, X17

    (672) 0x45654c B.EQ	456564

    (672) 0x456550 LDR	X17, [X21, X1]

    (672) 0x456554 ADD	X5, X5, #1

    (672) 0x456558 ADD	X17, X17, #1

    (672) 0x45655c STR	X17, [X21, X1]

    (672) 0x456560 STR	X0, [X19, X8]

    (672) 0x456564 LDR	X8, [X4, #16]

    (672) 0x456568 TBNZ	X8, #63, 456638

    (672) 0x45656c UBFM	X8, X8, #61, #60

    (672) 0x456570 LDR	X17, [X19, X8]

    (672) 0x456574 CMP	X0, X17

    (672) 0x456578 B.EQ	456590

    (672) 0x45657c LDR	X17, [X21, X1]

    (672) 0x456580 ADD	X5, X5, #1

    (672) 0x456584 ADD	X17, X17, #1

    (672) 0x456588 STR	X17, [X21, X1]

    (672) 0x45658c STR	X0, [X19, X8]

    (672) 0x456590 ADD	X4, X4, #24

    (672) 0x456594 CMP	X4, X10

    (672) 0x456598 B.EQ	456344

    (672) 0x45659c LDR	X8, [X4]

    (672) 0x4565a0 TBZ	X8, #63, 4564e4

    (672) 0x4565a4 ORN	X8, XZR, X8

    (672) 0x4565a8 UBFM	X8, X8, #61, #60

    (672) 0x4565ac LDR	X17, [X20, X8]

    (672) 0x4565b0 CMP	X0, X17

    (672) 0x4565b4 B.EQ	456508

    (672) 0x4565b8 LDR	X17, [X23, X1]

    (672) 0x4565bc ADD	X6, X6, #1

    (672) 0x4565c0 ADD	X4, X4, #8

    (672) 0x4565c4 ADD	X17, X17, #1

    (672) 0x4565c8 STR	X17, [X23, X1]

    (672) 0x4565cc STR	X0, [X20, X8]

    (672) 0x4565d0 LDR	X8, [X4]

    (672) 0x4565d4 TBZ	X8, #63, 456514

    (672) 0x4565d8 ORN	X8, XZR, X8

    (672) 0x4565dc UBFM	X8, X8, #61, #60

    (672) 0x4565e0 LDR	X17, [X20, X8]

    (672) 0x4565e4 CMP	X0, X17

    (672) 0x4565e8 B.EQ	456538

    (672) 0x4565ec LDR	X17, [X23, X1]

    (672) 0x4565f0 ADD	X6, X6, #1

    (672) 0x4565f4 ADD	X17, X17, #1

    (672) 0x4565f8 STR	X17, [X23, X1]

    (672) 0x4565fc STR	X0, [X20, X8]

    (672) 0x456600 LDR	X8, [X4, #8]

    (672) 0x456604 TBZ	X8, #63, 456540

    (672) 0x456608 ORN	X8, XZR, X8

    (672) 0x45660c UBFM	X8, X8, #61, #60

    (672) 0x456610 LDR	X17, [X20, X8]

    (672) 0x456614 CMP	X0, X17

    (672) 0x456618 B.EQ	456564

    (672) 0x45661c LDR	X17, [X23, X1]

    (672) 0x456620 ADD	X6, X6, #1

    (672) 0x456624 ADD	X17, X17, #1

    (672) 0x456628 STR	X17, [X23, X1]

    (672) 0x45662c STR	X0, [X20, X8]

    (672) 0x456630 LDR	X8, [X4, #16]

    (672) 0x456634 TBZ	X8, #63, 45656c

    (672) 0x456638 ORN	X8, XZR, X8

    (672) 0x45663c UBFM	X8, X8, #61, #60

    (672) 0x456640 LDR	X17, [X20, X8]

    (672) 0x456644 CMP	X0, X17

    (672) 0x456648 B.EQ	456590

    (672) 0x45664c LDR	X17, [X23, X1]

    (672) 0x456650 ADD	X6, X6, #1

    (672) 0x456654 ADD	X17, X17, #1

    (672) 0x456658 STR	X17, [X23, X1]

    (672) 0x45665c STR	X0, [X20, X8]

    (672) 0x456660 B	456590

  (671) 0x456664 ORN	X8, XZR, X8

  (671) 0x456668 UBFM	X8, X8, #61, #60

  (671) 0x45666c LDR	X17, [X20, X8]

  (671) 0x456670 CMP	X0, X17

  (671) 0x456674 B.EQ	456338

  (671) 0x456678 LDR	X17, [X23, X1]

  (671) 0x45667c ADD	X6, X6, #1

  (671) 0x456680 ADD	X17, X17, #1

  (671) 0x456684 STR	X17, [X23, X1]

  (671) 0x456688 STR	X0, [X20, X8]

  (671) 0x45668c B	456338

  (671) 0x456690 ORN	X8, XZR, X8

  (671) 0x456694 UBFM	X8, X8, #61, #60

  (671) 0x456698 LDR	X17, [X20, X8]

  (671) 0x45669c CMP	X0, X17

  (671) 0x4566a0 B.EQ	456308

  (671) 0x4566a4 LDR	X17, [X23, X1]

  (671) 0x4566a8 ADD	X6, X6, #1

  (671) 0x4566ac ADD	X17, X17, #1

  (671) 0x4566b0 STR	X17, [X23, X1]

  (671) 0x4566b4 STR	X0, [X20, X8]

  (671) 0x4566b8 B	456308

  (671) 0x4566bc ORN	X8, XZR, X17

  (671) 0x4566c0 UBFM	X8, X8, #61, #60

  (671) 0x4566c4 LDR	X17, [X20, X8]

  (671) 0x4566c8 CMP	X0, X17

  (671) 0x4566cc B.EQ	4562d8

  (671) 0x4566d0 LDR	X17, [X23, X1]

  (671) 0x4566d4 ADD	X6, X6, #1

  (671) 0x4566d8 ADD	X17, X17, #1

  (671) 0x4566dc STR	X17, [X23, X1]

  (671) 0x4566e0 STR	X0, [X20, X8]

  (671) 0x4566e4 B	4562d8

0x4566e8 UBFM	X28, X17, #61, #60

0x4566ec STR	X14, [SP, #96]

0x4566f0 STR	X13, [SP, #128]

0x4566f4 STR	X5, [X13, X28]

0x4566f8 STR	X6, [X14, X28]

0x4566fc STR	X4, [SP, #144]

0x456700 BL	410120

0x456704 BL	410120

0x456708 LDP	X7, X6, [SP, #144]

0x45670c LDP	X8, X10, [SP, #224]

0x456710 LDP	X18, X11, [SP, #240]

0x456714 LDP	X12, X9, [SP, #256]

0x456718 LDR	X14, [SP, #96]

0x45671c LDR	X13, [SP, #128]

0x456720 LDR	X15, [SP, #272]

0x456724 CMP	X6, #0

0x456728 B.LE	45644c

0x45672c SUB	X28, X28, #8

0x456730 LDR	X5, [SP, #168]

0x456734 ADD	X3, X14, X28

0x456738 ADD	X2, X13, X28

0x45673c LDR	X0, [SP, #184]

0x456740 CMP	X0, X5

0x456744 B.LE	4571a4

0x456748 LDR	X16, [SP, #104]

0x45674c ORN	X1, XZR, X9

0x456750 ADD	X0, X9, #1

0x456754 LDR	X7, [X3]

0x456758 LDR	X30, [SP, #136]

0x45675c LDR	X4, [X16, X9,LSL #3]

0x456760 LDR	X15, [SP, #176]

0x456764 ADD	X6, X18, X4,LSL #3

0x456768 ADD	X16, X30, X4,LSL #3

0x45676c LDR	X5, [X6]

0x456770 ADD	X17, X1, X15

0x456774 AND	X1, X17, #0x3

0x456778 ADD	X7, X5, X7

0x45677c STR	X7, [X6]

0x456780 LDR	X30, [X2]

0x456784 LDR	X4, [X16]

0x456788 ADD	X17, X4, X30

0x45678c STR	X17, [X16]

0x456790 CMP	X15, X0

0x456794 B.LE	4568ec

0x456798 CBZ	X1, 45711c

0x45679c CMP	X1, #1

0x4567a0 B.EQ	4567e4

0x4567a4 CMP	X1, #2

0x4567a8 B.NE	45712c

0x4567ac LDR	X16, [SP, #104]

0x4567b0 LDR	X6, [X3]

0x4567b4 LDR	X7, [SP, #136]

0x4567b8 LDR	X30, [X16, X0,LSL #3]

0x4567bc ADD	X0, X0, #1

0x4567c0 ADD	X5, X18, X30,LSL #3

0x4567c4 ADD	X17, X7, X30,LSL #3

0x4567c8 LDR	X4, [X5]

0x4567cc ADD	X15, X4, X6

0x4567d0 STR	X15, [X5]

0x4567d4 LDR	X1, [X17]

0x4567d8 LDR	X6, [X2]

0x4567dc ADD	X16, X1, X6

0x4567e0 STR	X16, [X17]

0x4567e4 LDR	X30, [SP, #104]

0x4567e8 LDR	X7, [X3]

0x4567ec LDR	X17, [SP, #136]

0x4567f0 LDR	X4, [X30, X0,LSL #3]

0x4567f4 ADD	X0, X0, #1

0x4567f8 ADD	X5, X18, X4,LSL #3

0x4567fc ADD	X15, X17, X4,LSL #3

0x456800 LDR	X17, [SP, #176]

0x456804 LDR	X1, [X5]

0x456808 ADD	X6, X1, X7

0x45680c STR	X6, [X5]

0x456810 LDR	X16, [X15]

0x456814 LDR	X7, [X2]

0x456818 ADD	X30, X16, X7

0x45681c STR	X30, [X15]

0x456820 CMP	X17, X0

0x456824 B.LE	4568ec

0x456828 LDR	X5, [SP, #104]

0x45682c ORR	X7, XZR, X17

0x456830 LDR	X1, [SP, #136]

(668) 0x456834 ADD	X17, X0, #1

(668) 0x456838 ADD	X15, X0, #3

(668) 0x45683c LDR	X4, [X5, X0,LSL #3]

(668) 0x456840 ADD	X16, X17, #1

(668) 0x456844 ADD	X0, X0, #4

(668) 0x456848 LDR	X30, [X3]

(668) 0x45684c UBFM	X4, X4, #61, #60

(668) 0x456850 LDR	X6, [X18, X4]

(668) 0x456854 ADD	X6, X6, X30

(668) 0x456858 STR	X6, [X18, X4]

(668) 0x45685c LDR	X6, [X1, X4]

(668) 0x456860 LDR	X30, [X2]

(668) 0x456864 ADD	X6, X6, X30

(668) 0x456868 STR	X6, [X1, X4]

(668) 0x45686c LDR	X17, [X5, X17,LSL #3]

(668) 0x456870 LDR	X6, [X3]

(668) 0x456874 UBFM	X4, X17, #61, #60

(668) 0x456878 LDR	X30, [X18, X4]

(668) 0x45687c ADD	X17, X30, X6

(668) 0x456880 STR	X17, [X18, X4]

(668) 0x456884 LDR	X30, [X1, X4]

(668) 0x456888 LDR	X6, [X2]

(668) 0x45688c ADD	X17, X30, X6

(668) 0x456890 STR	X17, [X1, X4]

(668) 0x456894 LDR	X16, [X5, X16,LSL #3]

(668) 0x456898 LDR	X6, [X3]

(668) 0x45689c UBFM	X4, X16, #61, #60

(668) 0x4568a0 LDR	X30, [X18, X4]

(668) 0x4568a4 ADD	X17, X30, X6

(668) 0x4568a8 STR	X17, [X18, X4]

(668) 0x4568ac LDR	X30, [X1, X4]

(668) 0x4568b0 LDR	X16, [X2]

(668) 0x4568b4 ADD	X6, X30, X16

(668) 0x4568b8 STR	X6, [X1, X4]

(668) 0x4568bc LDR	X15, [X5, X15,LSL #3]

(668) 0x4568c0 LDR	X30, [X3]

(668) 0x4568c4 UBFM	X4, X15, #61, #60

(668) 0x4568c8 LDR	X17, [X18, X4]

(668) 0x4568cc ADD	X16, X17, X30

(668) 0x4568d0 STR	X16, [X18, X4]

(668) 0x4568d4 LDR	X6, [X1, X4]

(668) 0x4568d8 LDR	X15, [X2]

(668) 0x4568dc ADD	X17, X6, X15

(668) 0x4568e0 STR	X17, [X1, X4]

(668) 0x4568e4 CMP	X7, X0

(668) 0x4568e8 B.GT	456834

0x4568ec STR	X13, [SP, #96]

0x4568f0 STR	X14, [SP, #128]

0x4568f4 STP	X8, X10, [SP, #144]

0x4568f8 STP	X18, X11, [SP, #224]

0x4568fc STP	X12, X9, [SP, #240]

0x456900 BL	410120

0x456904 LDR	X13, [SP, #96]

0x456908 LDP	X8, X10, [SP, #144]

0x45690c LDP	X15, X11, [SP, #224]

0x456910 LDP	X12, X9, [SP, #240]

0x456914 LDR	X14, [SP, #128]

0x456918 LDR	X2, [X13, X28]

0x45691c LDR	X4, [X14, X28]

0x456920 LDP	X0, X6, [SP, #160]

0x456924 ADD	X3, X10, X22

0x456928 ADD	X28, X8, X22

0x45692c STR	X3, [SP, #160]

0x456930 LDR	X30, [SP, #184]

0x456934 SUB	X7, X0, #1

0x456938 CMP	X30, X6

0x45693c B.LE	456e2c

0x456940 LDR	X30, [SP, #176]

0x456944 ORR	X18, XZR, X21

0x456948 STR	X15, [SP, #152]

0x45694c LDR	X17, [SP, #208]

0x456950 STR	X28, [SP, #168]

0x456954 HINT	#0

0x456958 HINT	#0

0x45695c HINT	#0

(662) 0x456960 LDR	X21, [SP, #104]

(662) 0x456964 LDR	X6, [X21, X9,LSL #3]

(662) 0x456968 UBFM	X15, X6, #61, #60

(662) 0x45696c ORN	X0, XZR, X6

(662) 0x456970 ADD	X14, X15, #8

(662) 0x456974 LDR	X3, [X12, X15]

(662) 0x456978 ADD	X5, X12, X14

(662) 0x45697c LDR	X13, [X12, X14]

(662) 0x456980 CMP	X3, X13

(662) 0x456984 B.GE	456ce8

(662) 0x456988 ORR	X28, XZR, X24

(662) 0x45698c STR	X6, [SP, #128]

(662) 0x456990 ORR	X6, XZR, X5

(662) 0x456994 B	4569a4

  (665) 0x456998 ADD	X3, X3, #1

  (665) 0x45699c CMP	X3, X13

  (665) 0x4569a0 B.GE	456ce0

  (665) 0x4569a4 LDR	X24, [X27, X3,LSL #3]

  (665) 0x4569a8 UBFM	X1, X24, #61, #60

  (665) 0x4569ac LDR	X16, [X25, X1]

  (665) 0x4569b0 CMP	X16, X7

  (665) 0x4569b4 B.NE	456998

  (665) 0x4569b8 LDR	X21, [SP, #152]

  (665) 0x4569bc ADD	X16, X1, #8

  (665) 0x4569c0 LDR	X13, [X23, X16]

  (665) 0x4569c4 LDR	X5, [X21, X1]

  (665) 0x4569c8 ADD	X13, X5, X13

  (665) 0x4569cc CMP	X5, X13

  (665) 0x4569d0 B.GE	456b58

  (665) 0x4569d4 LDR	X24, [SP, #160]

  (665) 0x4569d8 UBFM	X21, X5, #61, #60

  (665) 0x4569dc STR	X21, [SP, #144]

  (665) 0x4569e0 LDUR	X24, [X24, #504]

  (665) 0x4569e4 ADD	X13, X24, X13,LSL #3

  (665) 0x4569e8 ADD	X5, X24, X5,LSL #3

  (665) 0x4569ec SUB	X21, X13, X5

  (665) 0x4569f0 STR	X13, [SP, #96]

  (665) 0x4569f4 SUB	X21, X21, #8

  (665) 0x4569f8 UBFM	X21, X21, #3, #63

  (665) 0x4569fc ADD	X21, X21, #1

  (665) 0x456a00 ANDS	X21, X21, #0x3

  (665) 0x456a04 B.EQ	456aa0

  (665) 0x456a08 CMP	X21, #1

  (665) 0x456a0c B.EQ	456a6c

  (665) 0x456a10 CMP	X21, #2

  (665) 0x456a14 B.EQ	456a44

  (665) 0x456a18 LDR	X13, [SP, #144]

  (665) 0x456a1c LDR	X24, [X24, X13]

  (665) 0x456a20 UBFM	X21, X24, #61, #60

  (665) 0x456a24 LDR	X13, [X20, X21]

  (665) 0x456a28 CMP	X13, X0

  (665) 0x456a2c B.EQ	456a40

  (665) 0x456a30 LDR	X13, [X10, X22]

  (665) 0x456a34 STR	X24, [X13, X4,LSL #3]

  (665) 0x456a38 ADD	X4, X4, #1

  (665) 0x456a3c STR	X0, [X20, X21]

  (665) 0x456a40 ADD	X5, X5, #8

  (665) 0x456a44 LDR	X24, [X5]

  (665) 0x456a48 UBFM	X21, X24, #61, #60

  (665) 0x456a4c LDR	X13, [X20, X21]

  (665) 0x456a50 CMP	X13, X0

  (665) 0x456a54 B.EQ	456a68

  (665) 0x456a58 LDR	X13, [X10, X22]

  (665) 0x456a5c STR	X24, [X13, X4,LSL #3]

  (665) 0x456a60 ADD	X4, X4, #1

  (665) 0x456a64 STR	X0, [X20, X21]

  (665) 0x456a68 ADD	X5, X5, #8

  (665) 0x456a6c LDR	X24, [X5]

  (665) 0x456a70 UBFM	X21, X24, #61, #60

  (665) 0x456a74 LDR	X13, [X20, X21]

  (665) 0x456a78 CMP	X13, X0

  (665) 0x456a7c B.EQ	456a90

  (665) 0x456a80 LDR	X13, [X10, X22]

  (665) 0x456a84 STR	X24, [X13, X4,LSL #3]

  (665) 0x456a88 ADD	X4, X4, #1

  (665) 0x456a8c STR	X0, [X20, X21]

  (665) 0x456a90 LDR	X13, [SP, #96]

  (665) 0x456a94 ADD	X5, X5, #8

  (665) 0x456a98 CMP	X13, X5

  (665) 0x456a9c B.EQ	456b58

  (665) 0x456aa0 ORR	X24, XZR, X2

  (665) 0x456aa4 STR	X1, [SP, #96]

  (665) 0x456aa8 STR	X19, [SP, #144]

    (667) 0x456aac LDR	X21, [X5]

    (667) 0x456ab0 ADD	X2, X5, #8

    (667) 0x456ab4 UBFM	X19, X21, #61, #60

    (667) 0x456ab8 LDR	X1, [X20, X19]

    (667) 0x456abc CMP	X1, X0

    (667) 0x456ac0 B.EQ	456ad4

    (667) 0x456ac4 LDR	X1, [X10, X22]

    (667) 0x456ac8 STR	X21, [X1, X4,LSL #3]

    (667) 0x456acc ADD	X4, X4, #1

    (667) 0x456ad0 STR	X0, [X20, X19]

    (667) 0x456ad4 LDR	X19, [X5, #8]

    (667) 0x456ad8 UBFM	X5, X19, #61, #60

    (667) 0x456adc LDR	X21, [X20, X5]

    (667) 0x456ae0 CMP	X21, X0

    (667) 0x456ae4 B.EQ	456af8

    (667) 0x456ae8 LDR	X1, [X10, X22]

    (667) 0x456aec STR	X19, [X1, X4,LSL #3]

    (667) 0x456af0 ADD	X4, X4, #1

    (667) 0x456af4 STR	X0, [X20, X5]

    (667) 0x456af8 LDR	X21, [X2, #8]

    (667) 0x456afc ADD	X5, X2, #24

    (667) 0x456b00 UBFM	X19, X21, #61, #60

    (667) 0x456b04 LDR	X1, [X20, X19]

    (667) 0x456b08 CMP	X1, X0

    (667) 0x456b0c B.EQ	456b20

    (667) 0x456b10 LDR	X1, [X10, X22]

    (667) 0x456b14 STR	X21, [X1, X4,LSL #3]

    (667) 0x456b18 ADD	X4, X4, #1

    (667) 0x456b1c STR	X0, [X20, X19]

    (667) 0x456b20 LDR	X19, [X2, #16]

    (667) 0x456b24 UBFM	X2, X19, #61, #60

    (667) 0x456b28 LDR	X21, [X20, X2]

    (667) 0x456b2c CMP	X21, X0

    (667) 0x456b30 B.EQ	456b44

    (667) 0x456b34 LDR	X1, [X10, X22]

    (667) 0x456b38 STR	X19, [X1, X4,LSL #3]

    (667) 0x456b3c ADD	X4, X4, #1

    (667) 0x456b40 STR	X0, [X20, X2]

    (667) 0x456b44 CMP	X13, X5

    (667) 0x456b48 B.NE	456aac

  (665) 0x456b4c LDR	X1, [SP, #96]

  (665) 0x456b50 ORR	X2, XZR, X24

  (665) 0x456b54 LDR	X19, [SP, #144]

  (665) 0x456b58 LDR	X13, [SP, #136]

  (665) 0x456b5c LDR	X16, [X18, X16]

  (665) 0x456b60 LDR	X24, [X13, X1]

  (665) 0x456b64 ADD	X5, X24, X16

  (665) 0x456b68 CMP	X24, X5

  (665) 0x456b6c B.GE	456ccc

  (665) 0x456b70 LDR	X1, [SP, #168]

  (665) 0x456b74 UBFM	X21, X24, #61, #60

  (665) 0x456b78 LDUR	X16, [X1, #504]

  (665) 0x456b7c ADD	X1, X16, X24,LSL #3

  (665) 0x456b80 ADD	X5, X16, X5,LSL #3

  (665) 0x456b84 SUB	X13, X5, X1

  (665) 0x456b88 SUB	X24, X13, #8

  (665) 0x456b8c UBFM	X13, X24, #3, #63

  (665) 0x456b90 ADD	X24, X13, #1

  (665) 0x456b94 ANDS	X13, X24, #0x3

  (665) 0x456b98 B.EQ	456c2c

  (665) 0x456b9c CMP	X13, #1

  (665) 0x456ba0 B.EQ	456bfc

  (665) 0x456ba4 CMP	X13, #2

  (665) 0x456ba8 B.EQ	456bd4

  (665) 0x456bac LDR	X16, [X16, X21]

  (665) 0x456bb0 UBFM	X24, X16, #61, #60

  (665) 0x456bb4 LDR	X21, [X19, X24]

  (665) 0x456bb8 CMP	X21, X0

  (665) 0x456bbc B.EQ	456bd0

  (665) 0x456bc0 LDR	X13, [X8, X22]

  (665) 0x456bc4 STR	X16, [X13, X2,LSL #3]

  (665) 0x456bc8 ADD	X2, X2, #1

  (665) 0x456bcc STR	X0, [X19, X24]

  (665) 0x456bd0 ADD	X1, X1, #8

  (665) 0x456bd4 LDR	X16, [X1]

  (665) 0x456bd8 UBFM	X24, X16, #61, #60

  (665) 0x456bdc LDR	X21, [X19, X24]

  (665) 0x456be0 CMP	X21, X0

  (665) 0x456be4 B.EQ	456bf8

  (665) 0x456be8 LDR	X13, [X8, X22]

  (665) 0x456bec STR	X16, [X13, X2,LSL #3]

  (665) 0x456bf0 ADD	X2, X2, #1

  (665) 0x456bf4 STR	X0, [X19, X24]

  (665) 0x456bf8 ADD	X1, X1, #8

  (665) 0x456bfc LDR	X16, [X1]

  (665) 0x456c00 UBFM	X24, X16, #61, #60

  (665) 0x456c04 LDR	X21, [X19, X24]

  (665) 0x456c08 CMP	X21, X0

  (665) 0x456c0c B.EQ	456c20

  (665) 0x456c10 LDR	X13, [X8, X22]

  (665) 0x456c14 STR	X16, [X13, X2,LSL #3]

  (665) 0x456c18 ADD	X2, X2, #1

  (665) 0x456c1c STR	X0, [X19, X24]

  (665) 0x456c20 ADD	X1, X1, #8

  (665) 0x456c24 CMP	X1, X5

  (665) 0x456c28 B.EQ	456ccc

    (666) 0x456c2c LDR	X21, [X1]

    (666) 0x456c30 ADD	X13, X1, #8

    (666) 0x456c34 UBFM	X16, X21, #61, #60

    (666) 0x456c38 LDR	X24, [X19, X16]

    (666) 0x456c3c CMP	X24, X0

    (666) 0x456c40 B.EQ	456c54

    (666) 0x456c44 LDR	X24, [X8, X22]

    (666) 0x456c48 STR	X21, [X24, X2,LSL #3]

    (666) 0x456c4c ADD	X2, X2, #1

    (666) 0x456c50 STR	X0, [X19, X16]

    (666) 0x456c54 LDR	X16, [X1, #8]

    (666) 0x456c58 UBFM	X1, X16, #61, #60

    (666) 0x456c5c LDR	X21, [X19, X1]

    (666) 0x456c60 CMP	X21, X0

    (666) 0x456c64 B.EQ	456c78

    (666) 0x456c68 LDR	X24, [X8, X22]

    (666) 0x456c6c STR	X16, [X24, X2,LSL #3]

    (666) 0x456c70 ADD	X2, X2, #1

    (666) 0x456c74 STR	X0, [X19, X1]

    (666) 0x456c78 LDR	X21, [X13, #8]

    (666) 0x456c7c ADD	X1, X13, #24

    (666) 0x456c80 UBFM	X16, X21, #61, #60

    (666) 0x456c84 LDR	X24, [X19, X16]

    (666) 0x456c88 CMP	X24, X0

    (666) 0x456c8c B.EQ	456ca0

    (666) 0x456c90 LDR	X24, [X8, X22]

    (666) 0x456c94 STR	X21, [X24, X2,LSL #3]

    (666) 0x456c98 ADD	X2, X2, #1

    (666) 0x456c9c STR	X0, [X19, X16]

    (666) 0x456ca0 LDR	X16, [X13, #16]

    (666) 0x456ca4 UBFM	X13, X16, #61, #60

    (666) 0x456ca8 LDR	X21, [X19, X13]

    (666) 0x456cac CMP	X21, X0

    (666) 0x456cb0 B.EQ	456cc4

    (666) 0x456cb4 LDR	X24, [X8, X22]

    (666) 0x456cb8 STR	X16, [X24, X2,LSL #3]

    (666) 0x456cbc ADD	X2, X2, #1

    (666) 0x456cc0 STR	X0, [X19, X13]

    (666) 0x456cc4 CMP	X1, X5

    (666) 0x456cc8 B.NE	456c2c

  (665) 0x456ccc LDR	X13, [X6]

  (665) 0x456cd0 ADD	X3, X3, #1

  (665) 0x456cd4 CMP	X3, X13

  (665) 0x456cd8 B.LT	4569a4

(662) 0x456cdc HINT	#0

(662) 0x456ce0 LDR	X6, [SP, #128]

(662) 0x456ce4 ORR	X24, XZR, X28

(662) 0x456ce8 ORN	X6, XZR, X6

(662) 0x456cec LDR	X1, [X11, X15]

(662) 0x456cf0 ADD	X15, X11, X14

(662) 0x456cf4 LDR	X3, [X11, X14]

(662) 0x456cf8 CMP	X3, X1

(662) 0x456cfc B.LE	456e20

(662) 0x456d00 LDP	X21, X28, [SP, #112]

(662) 0x456d04 B	456d14

  (663) 0x456d08 ADD	X1, X1, #1

  (663) 0x456d0c CMP	X1, X3

  (663) 0x456d10 B.GE	456e20

  (663) 0x456d14 LDR	X0, [X26, X1,LSL #3]

  (663) 0x456d18 UBFM	X14, X0, #61, #60

  (663) 0x456d1c LDR	X5, [X24, X14]

  (663) 0x456d20 CMP	X5, X7

  (663) 0x456d24 B.NE	456d08

  (663) 0x456d28 ADD	X16, X21, X14

  (663) 0x456d2c LDR	X0, [X17, X14]

  (663) 0x456d30 LDR	X13, [X16, #8]

  (663) 0x456d34 ADD	X5, X0, X13

  (663) 0x456d38 CMP	X0, X5

  (663) 0x456d3c B.GE	456d08

  (663) 0x456d40 LDR	X16, [X28, X22]

  (663) 0x456d44 UBFM	X14, X0, #61, #60

  (663) 0x456d48 ADD	X5, X16, X5,LSL #3

  (663) 0x456d4c ADD	X0, X16, X0,LSL #3

  (663) 0x456d50 SUB	X3, X5, X0

  (663) 0x456d54 SUB	X13, X3, #8

  (663) 0x456d58 UBFM	X3, X13, #3, #63

  (663) 0x456d5c ADD	X13, X3, #1

  (663) 0x456d60 ANDS	X3, X13, #0x3

  (663) 0x456d64 B.EQ	456ee8

  (663) 0x456d68 CMP	X3, #1

  (663) 0x456d6c B.EQ	456dd0

  (663) 0x456d70 CMP	X3, #2

  (663) 0x456d74 B.EQ	456da4

  (663) 0x456d78 LDR	X16, [X16, X14]

  (663) 0x456d7c TBNZ	X16, #63, 45702c

  (663) 0x456d80 UBFM	X13, X16, #61, #60

  (663) 0x456d84 LDR	X14, [X19, X13]

  (663) 0x456d88 CMP	X14, X6

  (663) 0x456d8c B.EQ	456da0

  (663) 0x456d90 LDR	X3, [X8, X22]

  (663) 0x456d94 STR	X16, [X3, X2,LSL #3]

  (663) 0x456d98 ADD	X2, X2, #1

  (663) 0x456d9c STR	X6, [X19, X13]

  (663) 0x456da0 ADD	X0, X0, #8

  (663) 0x456da4 LDR	X3, [X0]

  (663) 0x456da8 TBNZ	X3, #63, 457000

  (663) 0x456dac UBFM	X13, X3, #61, #60

  (663) 0x456db0 LDR	X14, [X19, X13]

  (663) 0x456db4 CMP	X14, X6

  (663) 0x456db8 B.EQ	456dcc

  (663) 0x456dbc LDR	X16, [X8, X22]

  (663) 0x456dc0 STR	X3, [X16, X2,LSL #3]

  (663) 0x456dc4 ADD	X2, X2, #1

  (663) 0x456dc8 STR	X6, [X19, X13]

  (663) 0x456dcc ADD	X0, X0, #8

  (663) 0x456dd0 LDR	X16, [X0]

  (663) 0x456dd4 TBNZ	X16, #63, 456fd4

  (663) 0x456dd8 UBFM	X13, X16, #61, #60

  (663) 0x456ddc LDR	X14, [X19, X13]

  (663) 0x456de0 CMP	X14, X6

  (663) 0x456de4 B.EQ	456df8

  (663) 0x456de8 LDR	X3, [X8, X22]

  (663) 0x456dec STR	X16, [X3, X2,LSL #3]

  (663) 0x456df0 ADD	X2, X2, #1

  (663) 0x456df4 STR	X6, [X19, X13]

  (663) 0x456df8 ADD	X0, X0, #8

  (663) 0x456dfc CMP	X0, X5

  (663) 0x456e00 B.NE	456ee8

  (663) 0x456e04 LDR	X3, [X15]

  (663) 0x456e08 ADD	X1, X1, #1

  (663) 0x456e0c CMP	X1, X3

  (663) 0x456e10 B.LT	456d14

(662) 0x456e14 HINT	#0

(662) 0x456e18 HINT	#0

(662) 0x456e1c HINT	#0

(662) 0x456e20 ADD	X9, X9, #1

(662) 0x456e24 CMP	X30, X9

(662) 0x456e28 B.GT	456960

0x456e2c ORR	X0, XZR, X20

0x456e30 BL	5294c0

0x456e34 LDR	X27, [SP, #200]

0x456e38 LDR	X23, [SP, #192]

0x456e3c LDR	X26, [SP, #216]

0x456e40 CMP	X27, #0

0x456e44 CCMP	X23, X26, #4, #0

0x456e48 B.NE	457058

0x456e4c LDP	X21, X22, [SP, #32]

0x456e50 ORR	X0, XZR, X19

0x456e54 LDP	X23, X24, [SP, #48]

0x456e58 LDP	X19, X20, [SP, #16]

0x456e5c LDP	X25, X26, [SP, #64]

0x456e60 LDP	X27, X28, [SP, #80]

0x456e64 LDP	X29, X30, [SP], #288

0x456e68 B	5294c0

    (664) 0x456e6c UBFM	X13, X16, #61, #60

    (664) 0x456e70 LDR	X14, [X19, X13]

    (664) 0x456e74 CMP	X14, X6

    (664) 0x456e78 B.EQ	456e8c

    (664) 0x456e7c LDR	X3, [X8, X22]

    (664) 0x456e80 STR	X16, [X3, X2,LSL #3]

    (664) 0x456e84 ADD	X2, X2, #1

    (664) 0x456e88 STR	X6, [X19, X13]

    (664) 0x456e8c LDR	X3, [X0, #8]

    (664) 0x456e90 TBNZ	X3, #63, 456f4c

    (664) 0x456e94 UBFM	X13, X3, #61, #60

    (664) 0x456e98 LDR	X14, [X19, X13]

    (664) 0x456e9c CMP	X14, X6

    (664) 0x456ea0 B.EQ	456eb4

    (664) 0x456ea4 LDR	X16, [X8, X22]

    (664) 0x456ea8 STR	X3, [X16, X2,LSL #3]

    (664) 0x456eac ADD	X2, X2, #1

    (664) 0x456eb0 STR	X6, [X19, X13]

    (664) 0x456eb4 LDR	X16, [X0, #16]

    (664) 0x456eb8 TBNZ	X16, #63, 456f7c

    (664) 0x456ebc UBFM	X13, X16, #61, #60

    (664) 0x456ec0 LDR	X14, [X19, X13]

    (664) 0x456ec4 CMP	X14, X6

    (664) 0x456ec8 B.EQ	456edc

    (664) 0x456ecc LDR	X3, [X8, X22]

    (664) 0x456ed0 STR	X16, [X3, X2,LSL #3]

    (664) 0x456ed4 ADD	X2, X2, #1

    (664) 0x456ed8 STR	X6, [X19, X13]

    (664) 0x456edc ADD	X0, X0, #24

    (664) 0x456ee0 CMP	X0, X5

    (664) 0x456ee4 B.EQ	456e04

    (664) 0x456ee8 LDR	X3, [X0]

    (664) 0x456eec TBNZ	X3, #63, 456fa8

    (664) 0x456ef0 UBFM	X13, X3, #61, #60

    (664) 0x456ef4 LDR	X14, [X19, X13]

    (664) 0x456ef8 CMP	X14, X6

    (664) 0x456efc B.EQ	456f10

    (664) 0x456f00 LDR	X16, [X8, X22]

    (664) 0x456f04 STR	X3, [X16, X2,LSL #3]

    (664) 0x456f08 ADD	X2, X2, #1

    (664) 0x456f0c STR	X6, [X19, X13]

    (664) 0x456f10 LDR	X16, [X0, #8]

    (664) 0x456f14 ADD	X0, X0, #8

    (664) 0x456f18 TBZ	X16, #63, 456e6c

    (664) 0x456f1c ORN	X13, XZR, X16

    (664) 0x456f20 UBFM	X13, X13, #61, #60

    (664) 0x456f24 LDR	X14, [X20, X13]

    (664) 0x456f28 CMP	X14, X6

    (664) 0x456f2c B.EQ	456e8c

    (664) 0x456f30 LDR	X14, [X10, X22]

    (664) 0x456f34 ORN	X16, XZR, X16

    (664) 0x456f38 STR	X16, [X14, X4,LSL #3]

    (664) 0x456f3c ADD	X4, X4, #1

    (664) 0x456f40 STR	X6, [X20, X13]

    (664) 0x456f44 LDR	X3, [X0, #8]

    (664) 0x456f48 TBZ	X3, #63, 456e94

    (664) 0x456f4c ORN	X13, XZR, X3

    (664) 0x456f50 UBFM	X16, X13, #61, #60

    (664) 0x456f54 LDR	X14, [X20, X16]

    (664) 0x456f58 CMP	X14, X6

    (664) 0x456f5c B.EQ	456eb4

    (664) 0x456f60 LDR	X13, [X10, X22]

    (664) 0x456f64 ORN	X3, XZR, X3

    (664) 0x456f68 STR	X3, [X13, X4,LSL #3]

    (664) 0x456f6c ADD	X4, X4, #1

    (664) 0x456f70 STR	X6, [X20, X16]

    (664) 0x456f74 LDR	X16, [X0, #16]

    (664) 0x456f78 TBZ	X16, #63, 456ebc

    (664) 0x456f7c ORN	X13, XZR, X16

    (664) 0x456f80 UBFM	X13, X13, #61, #60

    (664) 0x456f84 LDR	X14, [X20, X13]

    (664) 0x456f88 CMP	X14, X6

    (664) 0x456f8c B.EQ	456edc

    (664) 0x456f90 LDR	X14, [X10, X22]

    (664) 0x456f94 ORN	X16, XZR, X16

    (664) 0x456f98 STR	X16, [X14, X4,LSL #3]

    (664) 0x456f9c ADD	X4, X4, #1

    (664) 0x456fa0 STR	X6, [X20, X13]

    (664) 0x456fa4 B	456edc

    (664) 0x456fa8 ORN	X13, XZR, X3

    (664) 0x456fac UBFM	X16, X13, #61, #60

    (664) 0x456fb0 LDR	X14, [X20, X16]

    (664) 0x456fb4 CMP	X14, X6

    (664) 0x456fb8 B.EQ	456f10

    (664) 0x456fbc LDR	X13, [X10, X22]

    (664) 0x456fc0 ORN	X3, XZR, X3

    (664) 0x456fc4 STR	X3, [X13, X4,LSL #3]

    (664) 0x456fc8 ADD	X4, X4, #1

    (664) 0x456fcc STR	X6, [X20, X16]

    (664) 0x456fd0 B	456f10

  (663) 0x456fd4 ORN	X13, XZR, X16

  (663) 0x456fd8 UBFM	X13, X13, #61, #60

  (663) 0x456fdc LDR	X14, [X20, X13]

  (663) 0x456fe0 CMP	X14, X6

  (663) 0x456fe4 B.EQ	456df8

  (663) 0x456fe8 LDR	X14, [X10, X22]

  (663) 0x456fec ORN	X16, XZR, X16

  (663) 0x456ff0 STR	X16, [X14, X4,LSL #3]

  (663) 0x456ff4 ADD	X4, X4, #1

  (663) 0x456ff8 STR	X6, [X20, X13]

  (663) 0x456ffc B	456df8

  (663) 0x457000 ORN	X13, XZR, X3

  (663) 0x457004 UBFM	X16, X13, #61, #60

  (663) 0x457008 LDR	X14, [X20, X16]

  (663) 0x45700c CMP	X14, X6

  (663) 0x457010 B.EQ	456dcc

  (663) 0x457014 LDR	X13, [X10, X22]

  (663) 0x457018 ORN	X3, XZR, X3

  (663) 0x45701c STR	X3, [X13, X4,LSL #3]

  (663) 0x457020 ADD	X4, X4, #1

  (663) 0x457024 STR	X6, [X20, X16]

  (663) 0x457028 B	456dcc

  (663) 0x45702c ORN	X13, XZR, X16

  (663) 0x457030 UBFM	X13, X13, #61, #60

  (663) 0x457034 LDR	X14, [X20, X13]

  (663) 0x457038 CMP	X14, X6

  (663) 0x45703c B.EQ	456da0

  (663) 0x457040 LDR	X14, [X10, X22]

  (663) 0x457044 ORN	X16, XZR, X16

  (663) 0x457048 STR	X16, [X14, X4,LSL #3]

  (663) 0x45704c ADD	X4, X4, #1

  (663) 0x457050 STR	X6, [X20, X13]

  (663) 0x457054 B	456da0

0x457058 LDP	X19, X20, [SP, #16]

0x45705c LDP	X21, X22, [SP, #32]

0x457060 LDP	X23, X24, [SP, #48]

0x457064 LDP	X25, X26, [SP, #64]

0x457068 LDP	X27, X28, [SP, #80]

0x45706c LDP	X29, X30, [SP], #288

0x457070 RET

0x457074 MOVZ	X1, #8

0x457078 ORR	X28, XZR, X0

0x45707c STR	X13, [SP, #96]

0x457080 STR	X14, [SP, #128]

0x457084 STR	X4, [SP, #144]

0x457088 STP	X8, X10, [SP, #224]

0x45708c STP	X18, X11, [SP, #240]

0x457090 STP	X12, X9, [SP, #256]

0x457094 STR	X3, [SP, #272]

0x457098 BL	529428

0x45709c CMP	X28, #0

0x4570a0 LDR	X13, [SP, #96]

0x4570a4 ORR	X19, XZR, X0

0x4570a8 LDP	X8, X10, [SP, #224]

0x4570ac LDP	X18, X11, [SP, #240]

0x4570b0 LDP	X12, X9, [SP, #256]

0x4570b4 LDR	X14, [SP, #128]

0x4570b8 LDR	X4, [SP, #144]

0x4570bc LDR	X3, [SP, #272]

0x4570c0 B.LE	455e2c

0x4570c4 UBFM	X2, X28, #61, #60

0x4570c8 MOVZ	W1, #255

0x4570cc BL	410340

0x4570d0 LDR	X13, [SP, #96]

0x4570d4 LDP	X8, X10, [SP, #224]

0x4570d8 LDP	X18, X11, [SP, #240]

0x4570dc LDP	X12, X9, [SP, #256]

0x4570e0 LDR	X14, [SP, #128]

0x4570e4 LDR	X4, [SP, #144]

0x4570e8 LDR	X3, [SP, #272]

0x4570ec B	455e2c

0x4570f0 ORR	X28, XZR, X30

0x4570f4 MOVZ	X1, #8

0x4570f8 STR	X13, [SP, #96]

0x4570fc ORR	X0, XZR, X30

0x457100 STR	X14, [SP, #128]

0x457104 STR	X4, [SP, #144]

0x457108 STP	X8, X10, [SP, #224]

0x45710c STP	X18, X11, [SP, #240]

0x457110 STP	X12, X9, [SP, #256]

0x457114 STR	X3, [SP, #272]

0x457118 B	457098

0x45711c LDR	X5, [SP, #104]

0x457120 ORR	X7, XZR, X15

0x457124 LDR	X1, [SP, #136]

0x457128 B	456834

0x45712c LDR	X1, [SP, #104]

0x457130 LDR	X15, [X3]

0x457134 LDR	X6, [SP, #136]

0x457138 LDR	X16, [X1, X0,LSL #3]

0x45713c ADD	X0, X0, #1

0x457140 ADD	X7, X18, X16,LSL #3

0x457144 ADD	X5, X6, X16,LSL #3

0x457148 LDR	X30, [X7]

0x45714c ADD	X4, X30, X15

0x457150 STR	X4, [X7]

0x457154 LDR	X17, [X2]

0x457158 LDR	X15, [X5]

0x45715c ADD	X1, X15, X17

0x457160 STR	X1, [X5]

0x457164 B	4567ac

0x457168 MOVZ	X1, #8

0x45716c ORR	X0, XZR, X28

0x457170 STR	X5, [SP, #96]

0x457174 STR	X13, [SP, #128]

0x457178 STP	X14, X7, [SP, #144]

0x45717c STP	X8, X10, [SP, #224]

0x457180 BL	529428

0x457184 LDR	X18, [SP, #96]

0x457188 STR	X0, [X18, X22]

0x45718c BL	410120

0x457190 LDR	X8, [SP, #96]

0x457194 LDP	X15, X11, [SP, #144]

0x457198 LDP	X12, X9, [SP, #224]

0x45719c LDR	X10, [SP, #128]

0x4571a0 B	4564d8

0x4571a4 BL	410120

0x4571a8 B	456e2c

0x4571ac STR	X5, [SP, #96]

0x4571b0 STR	X13, [SP, #128]

0x4571b4 STP	X14, X7, [SP, #144]

0x4571b8 STP	X8, X10, [SP, #224]

0x4571bc B	4564c4

Coverage (%)	Name	Source Location	Module
►98.47+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.53+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	par_multi_interp.c:891-1134
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:891,900-927,939-970,976-999,1008-1034,1040-1125,1132-1134.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 34% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 91.17 to 27.67 cycles (3.30x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:916
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1048
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:921
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1050
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1132
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:900
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:901
unknown: 10 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:918
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:923
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	417
nb uops	412
loop length	1668
used w registers	1
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	207

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	51.50 cycles
front end	51.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	22.50	22.50	28.00	28.00	28.00	28.00	0.00	0.00	0.00	0.00	91.17	90.83	91.00	54.50	54.50
cycles	22.50	22.50	28.00	28.00	28.00	28.00	0.00	0.00	0.00	0.00	91.17	90.83	91.00	54.50	54.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	51.50
Dispatch	91.17
DIV/SQRT	5.00-20.00
Overall L1	91.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	34%
load	42%
store	33%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 91.17 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 455cac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #736]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X1, X18, [X3, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X8, [X3, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X26, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X10, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X3, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X3, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X3, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X3, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X20, X7, [X3, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X14, X13, [X3, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X28, [X3, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X24, [X3, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X14, X7, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X3, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X15, [X3, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X3, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X22, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X16, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 52c0a0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 52c080 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X11, X20, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X12, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X1, X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MUL X8, X18, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X2, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X4, X2, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X3, X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X18, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LE 455e0c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X18, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410340 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X4, X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X18, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X30, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4570f0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1444>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 457074 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x13c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X15, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X7, X16, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45637c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X30, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X4, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X13, X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X17, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X17, 4566e8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X18, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [X18], #504	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [X28], #504	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X18, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X13, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X2, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 456418 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x76c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X6, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X13, X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X3, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X7, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X18, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X15, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X28, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X15, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X15, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X0, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X14, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [X13, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X3, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X30, [X15, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X2, [X15, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X18, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X14, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X0, [X13, X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X28, 457168 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x14bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X1, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4571ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X5, X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 456920 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X28, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [X13, X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [X14, X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45644c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X28, X28, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X14, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X13, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4571a4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x14f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X1, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X30, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X1, X17, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X5, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X7, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4568ec <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X1, 45711c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4567e4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45712c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X18, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X7, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X16, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X17, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X30, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4568ec <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X7, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X8, X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X13, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X14, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X0, X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X3, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X28, X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 456e2c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 5294c0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X26, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X23, X26, #4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 457058 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x13ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 5294c0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LE 455e2c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410340 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 455e2c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 457098 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x13ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X7, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 456834 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X18, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X6, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X30, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 4567ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X14, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X18, X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 4564d8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x82c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 456e2c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X14, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 4564c4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x818>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	par_multi_interp.c:891-1134
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:916
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1048
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:921
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1050
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1132
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:900
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:901
unknown: 10 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:918
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:923
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	417
nb uops	412
loop length	1668
used w registers	1
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	207

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	51.50 cycles
front end	51.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	22.50	22.50	28.00	28.00	28.00	28.00	0.00	0.00	0.00	0.00	91.17	90.83	91.00	54.50	54.50
cycles	22.50	22.50	28.00	28.00	28.00	28.00	0.00	0.00	0.00	0.00	91.17	90.83	91.00	54.50	54.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	51.50
Dispatch	91.17
DIV/SQRT	5.00-20.00
Overall L1	91.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	34%
load	42%
store	33%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 91.17 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 455cac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #736]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X1, X18, [X3, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X8, [X3, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X26, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X10, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X3, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X3, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X3, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X3, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X20, X7, [X3, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X14, X13, [X3, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X28, [X3, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X24, [X3, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X14, X7, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X3, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X15, [X3, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X3, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X22, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X16, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 52c0a0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 52c080 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X11, X20, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X12, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X1, X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MUL X8, X18, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X2, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X4, X2, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X3, X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X18, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LE 455e0c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X18, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410340 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X4, X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X18, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X30, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4570f0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1444>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 457074 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x13c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X15, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X7, X16, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45637c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X30, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X4, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X13, X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X17, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X17, 4566e8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X18, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [X18], #504	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [X28], #504	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X18, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X13, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X2, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 456418 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x76c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X6, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X13, X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X3, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X7, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X18, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X15, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X28, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X15, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X15, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X0, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X14, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [X13, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X3, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X30, [X15, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X2, [X15, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X18, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X14, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X0, [X13, X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X28, 457168 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x14bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X1, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4571ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X5, X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 456920 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X28, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [X13, X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [X14, X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45644c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X28, X28, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X14, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X13, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4571a4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x14f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X1, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X30, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X1, X17, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X5, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X7, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4568ec <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X1, 45711c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4567e4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45712c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X18, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X7, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X16, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X17, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X30, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4568ec <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X7, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X8, X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X13, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X14, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X0, X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X3, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X28, X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 456e2c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 5294c0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X26, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X23, X26, #4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 457058 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x13ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 5294c0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LE 455e2c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410340 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 455e2c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 457098 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x13ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X7, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 456834 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X18, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X6, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X30, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 4567ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X14, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X18, X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 4564d8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x82c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 456e2c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X14, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 4564c4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x818>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.5–	1.19	0.50
▼Loop 662 - par_multi_interp.c:1072-1125 - exec–	0.04	0.01
▼Loop 665 - par_multi_interp.c:1075-1099 - exec–	0.55	0.17
○Loop 667 - par_multi_interp.c:1082-1088 - exec	0.00	0.00
○Loop 666 - par_multi_interp.c:1093-1099 - exec	0.00	0.00
▼Loop 663 - par_multi_interp.c:1104-1125 - exec–	0.00	0.00
○Loop 664 - par_multi_interp.c:1111-1125 - exec	0.00	0.00
▼Loop 670 - par_multi_interp.c:939-999 - exec–	0.04	0.01
▼Loop 673 - par_multi_interp.c:944-970 - exec–	0.53	0.16
○Loop 675 - par_multi_interp.c:951-958 - exec	0.00	0.00
○Loop 674 - par_multi_interp.c:963-970 - exec	0.00	0.00
▼Loop 671 - par_multi_interp.c:976-999 - exec–	0.00	0.00
○Loop 672 - par_multi_interp.c:983-999 - exec	0.00	0.00
○Loop 668 - par_multi_interp.c:1030-1034 - exec	0.03	0.01
○Loop 669 - par_multi_interp.c:1017-1020 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code