OV - exec - Function hypre_ParMatmul._omp

	Function: hypre_ParMatmul._omp_fn.3	Module: exec	Source: par_csr_matop.c:829-995 [...]	Coverage (incl. loops): 0.88% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 829 - 995

--------------------------------------------------------------------------------

829: #pragma omp parallel

830: #endif

831:    {

832:     HYPRE_Int *B_marker = NULL;

[...]

840:     ii = hypre_GetThreadNum();

841:     num_threads = hypre_NumActiveThreads();

842:     size = num_rows_diag_A/num_threads;

843:     rest = num_rows_diag_A - size*num_threads;

844:     if (ii < rest)

845:     {

846:        ns = ii*size+ii;

847:        ne = (ii+1)*size+ii+1;

848:     }

849:     else

850:     {

851:        ns = ii*size+rest;

852:        ne = (ii+1)*size+rest;

853:     }

854:     jj_count_diag = C_diag_i[ns];

855:     jj_count_offd = C_offd_i[ns];

856:     if (num_cols_diag_B || num_cols_offd_C)

857:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

858:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

859:       B_marker[i1] = -1;

[...]

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

[...]

995:     hypre_TFree(B_marker);

0x4e7c00 STP	X29, X30, [SP, #704]!

0x4e7c04 ORR	X2, XZR, X0

0x4e7c08 ADD	X29, SP, #0

0x4e7c0c STP	X19, X20, [SP, #16]

0x4e7c10 STP	X21, X22, [SP, #32]

0x4e7c14 STP	X23, X24, [SP, #48]

0x4e7c18 STP	X25, X26, [SP, #64]

0x4e7c1c STP	X27, X28, [SP, #80]

0x4e7c20 LDP	X25, X14, [X2, #48]

0x4e7c24 LDP	X21, X7, [X2, #80]

0x4e7c28 LDP	X22, X27, [X2, #64]

0x4e7c2c LDR	X0, [X0]

0x4e7c30 LDR	X15, [X2, #16]

0x4e7c34 STP	X7, X14, [SP, #208]

0x4e7c38 LDR	X1, [X2, #8]

0x4e7c3c STR	D15, [SP, #96]

0x4e7c40 LDR	X3, [X2, #24]

0x4e7c44 STR	X0, [SP, #192]

0x4e7c48 LDR	X4, [X2, #32]

0x4e7c4c STR	X1, [SP, #120]

0x4e7c50 LDR	X5, [X2, #40]

0x4e7c54 STR	X15, [SP, #224]

0x4e7c58 LDR	X6, [X2, #96]

0x4e7c5c STR	X4, [SP, #112]

0x4e7c60 STR	X3, [SP, #288]

0x4e7c64 STR	X5, [SP, #280]

0x4e7c68 STR	X6, [SP, #184]

0x4e7c6c LDP	X8, X26, [X2, #104]

0x4e7c70 LDP	X9, X10, [X2, #120]

0x4e7c74 LDP	X28, X18, [X2, #208]

0x4e7c78 LDP	X24, X23, [X2, #152]

0x4e7c7c STR	X9, [SP, #176]

0x4e7c80 LDR	X11, [X2, #176]

0x4e7c84 STR	X8, [SP, #200]

0x4e7c88 LDR	X19, [X2, #136]

0x4e7c8c LDR	X12, [X2, #192]

0x4e7c90 LDR	D15, [X2, #248]

0x4e7c94 STP	X2, X18, [SP, #128]

0x4e7c98 STP	X11, X10, [SP, #160]

0x4e7c9c LDR	X13, [X2, #200]

0x4e7ca0 STR	X12, [SP, #144]

0x4e7ca4 LDR	X16, [X2, #224]

0x4e7ca8 LDR	X17, [X2, #232]

0x4e7cac STR	X13, [SP, #272]

0x4e7cb0 LDR	X20, [X2, #240]

0x4e7cb4 STR	X16, [SP, #264]

0x4e7cb8 STR	X17, [SP, #256]

0x4e7cbc STR	X20, [SP, #152]

0x4e7cc0 BL	52c0a0

0x4e7cc4 ORR	X20, XZR, X0

0x4e7cc8 BL	52c080

0x4e7ccc ORR	X2, XZR, X0

0x4e7cd0 SDIV	X0, X25, X0

0x4e7cd4 LDR	X3, [SP, #144]

0x4e7cd8 LDP	X12, X18, [SP, #128]

0x4e7cdc LDP	X4, X5, [SP, #160]

0x4e7ce0 LDP	X6, X7, [SP, #200]

0x4e7ce4 MSUB	X25, X0, X2, X25

0x4e7ce8 LDP	X14, X15, [SP, #216]

0x4e7cec MUL	X1, X20, X0

0x4e7cf0 CMP	X20, X25

0x4e7cf4 ADD	X9, X0, X1

0x4e7cf8 B.GE	4e8144

0x4e7cfc ADD	X30, X20, X9

0x4e7d00 ADD	X8, X20, X1

0x4e7d04 ADD	X13, X30, #1

0x4e7d08 LDR	X11, [X12, #184]

0x4e7d0c UBFM	X9, X8, #61, #60

0x4e7d10 LDR	X10, [X12, #144]

0x4e7d14 LDR	X16, [X12, #168]

0x4e7d18 LDR	X17, [X11]

0x4e7d1c LDR	X20, [X10]

0x4e7d20 LDR	X2, [X16]

0x4e7d24 ORR	X0, X26, X17

0x4e7d28 LDR	X20, [X20, X9]

0x4e7d2c LDR	X25, [X2, X9]

0x4e7d30 CBNZ	X0, 4e80c8

0x4e7d34 MOVZ	X0, #0

0x4e7d38 LDR	X1, [SP, #112]

0x4e7d3c LDR	X17, [SP, #120]

0x4e7d40 ADD	X12, X1, X9

0x4e7d44 ADD	X10, X17, X9

0x4e7d48 CMP	X8, X13

0x4e7d4c B.GE	4e80a8

0x4e7d50 STR	X4, [SP, #112]

0x4e7d54 ORR	X16, XZR, X15

0x4e7d58 STP	X23, X12, [SP, #136]

0x4e7d5c LDR	X23, [SP, #152]

0x4e7d60 STP	X13, X14, [SP, #160]

0x4e7d64 STR	X5, [SP, #200]

0x4e7d68 STP	X18, X28, [SP, #296]

0x4e7d6c STR	X3, [SP, #312]

0x4e7d70 CBNZ	X23, 4e7e48

  (2659) 0x4e7d74 LDR	X18, [SP, #168]

  (2659) 0x4e7d78 ORR	X2, XZR, X20

  (2659) 0x4e7d7c ORR	X9, XZR, X25

  (2659) 0x4e7d80 CBNZ	X18, 4e7e68

  (2659) 0x4e7d84 LDP	X12, X4, [X10]

  (2659) 0x4e7d88 CMP	X12, X4

  (2659) 0x4e7d8c B.GE	4e7e18

  (2659) 0x4e7d90 LDP	X17, X18, [SP, #176]

  (2659) 0x4e7d94 LDP	X13, X11, [SP, #192]

  (2659) 0x4e7d98 STR	X8, [SP, #120]

  (2659) 0x4e7d9c HINT	#0

    (2664) 0x4e7da0 LDR	X23, [X16, X12,LSL #3]

    (2664) 0x4e7da4 LDR	D28, [X13, X12,LSL #3]

    (2664) 0x4e7da8 UBFM	X5, X23, #61, #60

    (2664) 0x4e7dac ADD	X8, X5, #8

    (2664) 0x4e7db0 LDR	X1, [X27, X5]

    (2664) 0x4e7db4 ADD	X15, X27, X8

    (2664) 0x4e7db8 LDR	X14, [X27, X8]

    (2664) 0x4e7dbc CMP	X1, X14

    (2664) 0x4e7dc0 B.GE	4e7e00

      (2666) 0x4e7dc4 LDR	X4, [X21, X1,LSL #3]

      (2666) 0x4e7dc8 UBFM	X28, X2, #61, #60

      (2666) 0x4e7dcc LDR	D6, [X22, X1,LSL #3]

      (2666) 0x4e7dd0 UBFM	X23, X4, #61, #60

      (2666) 0x4e7dd4 LDR	X3, [X0, X23]

      (2666) 0x4e7dd8 FMUL	D7, D28, D6

      (2666) 0x4e7ddc UBFM	X30, X3, #61, #60

      (2666) 0x4e7de0 CMP	X20, X3

      (2666) 0x4e7de4 B.GT	4e7fa4

      (2666) 0x4e7de8 LDR	D16, [X19, X30]

      (2666) 0x4e7dec ADD	X1, X1, #1

      (2666) 0x4e7df0 FADD	D17, D16, D7

      (2666) 0x4e7df4 STR	D17, [X19, X30]

      (2666) 0x4e7df8 CMP	X1, X14

      (2666) 0x4e7dfc B.LT	4e7dc4

    (2664) 0x4e7e00 CBNZ	X17, 4e7fc8

    (2664) 0x4e7e04 LDR	X4, [X10, #8]

    (2664) 0x4e7e08 ADD	X12, X12, #1

    (2664) 0x4e7e0c CMP	X4, X12

    (2664) 0x4e7e10 B.GT	4e7da0

  (2659) 0x4e7e14 LDR	X8, [SP, #120]

  (2659) 0x4e7e18 ADD	X8, X8, #1

  (2659) 0x4e7e1c ADD	X10, X10, #8

  (2659) 0x4e7e20 LDR	X20, [SP, #144]

  (2659) 0x4e7e24 LDR	X17, [SP, #160]

  (2659) 0x4e7e28 ADD	X25, X20, #8

  (2659) 0x4e7e2c STR	X25, [SP, #144]

  (2659) 0x4e7e30 CMP	X17, X8

  (2659) 0x4e7e34 B.EQ	4e80a8

  (2659) 0x4e7e38 LDR	X23, [SP, #152]

  (2659) 0x4e7e3c ORR	X25, XZR, X9

  (2659) 0x4e7e40 ORR	X20, XZR, X2

  (2659) 0x4e7e44 CBZ	X23, 4e7d74

(2663) 0x4e7e48 UBFM	X28, X20, #61, #60

(2663) 0x4e7e4c STR	X20, [X0, X8,LSL #3]

(2663) 0x4e7e50 ADD	X2, X20, #1

(2663) 0x4e7e54 LDR	X18, [SP, #168]

(2663) 0x4e7e58 ORR	X9, XZR, X25

(2663) 0x4e7e5c STR	D15, [X19, X28]

(2663) 0x4e7e60 STR	X8, [X24, X28]

(2663) 0x4e7e64 CBZ	X18, 4e7d84

  (2659) 0x4e7e68 LDR	X5, [SP, #144]

  (2659) 0x4e7e6c LDP	X13, X3, [X5]

  (2659) 0x4e7e70 CMP	X13, X3

  (2659) 0x4e7e74 B.GE	4e7d84

  (2659) 0x4e7e78 LDR	X4, [SP, #112]

  (2659) 0x4e7e7c LDP	X14, X15, [SP, #272]

  (2659) 0x4e7e80 LDP	X18, X28, [SP, #296]

  (2659) 0x4e7e84 STP	X22, X16, [SP, #240]

  (2659) 0x4e7e88 ORR	X22, XZR, X10

  (2659) 0x4e7e8c LDR	X23, [SP, #136]

  (2659) 0x4e7e90 STP	X21, X27, [SP, #224]

  (2659) 0x4e7e94 ORR	X21, XZR, X5

  (2659) 0x4e7e98 ORR	X27, XZR, X8

  (2659) 0x4e7e9c LDR	X17, [SP, #256]

  (2659) 0x4e7ea0 STP	X6, X7, [SP, #208]

  (2659) 0x4e7ea4 LDR	X10, [SP, #264]

  (2659) 0x4e7ea8 LDR	X16, [SP, #288]

  (2659) 0x4e7eac LDR	X3, [SP, #312]

    (2660) 0x4e7eb0 LDR	X6, [X15, X13,LSL #3]

    (2660) 0x4e7eb4 LDR	D31, [X16, X13,LSL #3]

    (2660) 0x4e7eb8 UBFM	X7, X6, #61, #60

    (2660) 0x4e7ebc ADD	X8, X7, #8

    (2660) 0x4e7ec0 LDR	X1, [X10, X7]

    (2660) 0x4e7ec4 ADD	X12, X10, X8

    (2660) 0x4e7ec8 LDR	X11, [X10, X8]

    (2660) 0x4e7ecc CMP	X1, X11

    (2660) 0x4e7ed0 B.GE	4e7f24

    (2660) 0x4e7ed4 STP	X10, X28, [SP, #120]

    (2660) 0x4e7ed8 HINT	#0

    (2660) 0x4e7edc HINT	#0

      (2662) 0x4e7ee0 UBFM	X28, X9, #61, #60

      (2662) 0x4e7ee4 LDR	X10, [X17, X1,LSL #3]

      (2662) 0x4e7ee8 LDR	D1, [X18, X1,LSL #3]

      (2662) 0x4e7eec ADD	X30, X26, X10

      (2662) 0x4e7ef0 UBFM	X5, X30, #61, #60

      (2662) 0x4e7ef4 LDR	X6, [X0, X5]

      (2662) 0x4e7ef8 FMUL	D2, D31, D1

      (2662) 0x4e7efc UBFM	X30, X6, #61, #60

      (2662) 0x4e7f00 CMP	X25, X6

      (2662) 0x4e7f04 B.GT	4e8084

      (2662) 0x4e7f08 LDR	D0, [X23, X30]

      (2662) 0x4e7f0c ADD	X1, X1, #1

      (2662) 0x4e7f10 FADD	D3, D0, D2

      (2662) 0x4e7f14 STR	D3, [X23, X30]

      (2662) 0x4e7f18 CMP	X1, X11

      (2662) 0x4e7f1c B.LT	4e7ee0

    (2660) 0x4e7f20 LDP	X10, X28, [SP, #120]

    (2660) 0x4e7f24 ADD	X12, X14, X8

    (2660) 0x4e7f28 LDR	X1, [X14, X7]

    (2660) 0x4e7f2c LDR	X30, [X14, X8]

    (2660) 0x4e7f30 CMP	X1, X30

    (2660) 0x4e7f34 B.GE	4e7f7c

    (2660) 0x4e7f38 HINT	#0

    (2660) 0x4e7f3c HINT	#0

      (2661) 0x4e7f40 LDR	X6, [X28, X1,LSL #3]

      (2661) 0x4e7f44 UBFM	X8, X2, #61, #60

      (2661) 0x4e7f48 LDR	D30, [X3, X1,LSL #3]

      (2661) 0x4e7f4c UBFM	X7, X6, #61, #60

      (2661) 0x4e7f50 LDR	X5, [X0, X7]

      (2661) 0x4e7f54 FMUL	D4, D31, D30

      (2661) 0x4e7f58 UBFM	X11, X5, #61, #60

      (2661) 0x4e7f5c CMP	X20, X5

      (2661) 0x4e7f60 B.GT	4e8050

      (2661) 0x4e7f64 LDR	D29, [X19, X11]

      (2661) 0x4e7f68 ADD	X1, X1, #1

      (2661) 0x4e7f6c FADD	D5, D29, D4

      (2661) 0x4e7f70 STR	D5, [X19, X11]

      (2661) 0x4e7f74 CMP	X1, X30

      (2661) 0x4e7f78 B.LT	4e7f40

    (2660) 0x4e7f7c LDR	X12, [X21, #8]

    (2660) 0x4e7f80 ADD	X13, X13, #1

    (2660) 0x4e7f84 CMP	X12, X13

    (2660) 0x4e7f88 B.GT	4e7eb0

  (2659) 0x4e7f8c ORR	X8, XZR, X27

  (2659) 0x4e7f90 ORR	X10, XZR, X22

  (2659) 0x4e7f94 LDP	X6, X7, [SP, #208]

  (2659) 0x4e7f98 LDP	X21, X27, [SP, #224]

  (2659) 0x4e7f9c LDP	X22, X16, [SP, #240]

  (2659) 0x4e7fa0 B	4e7d84

      (2666) 0x4e7fa4 STR	X2, [X0, X23]

      (2666) 0x4e7fa8 ADD	X1, X1, #1

      (2666) 0x4e7fac ADD	X2, X2, #1

      (2666) 0x4e7fb0 STR	D7, [X19, X28]

      (2666) 0x4e7fb4 STR	X4, [X24, X28]

      (2666) 0x4e7fb8 LDR	X14, [X15]

      (2666) 0x4e7fbc CMP	X14, X1

      (2666) 0x4e7fc0 B.GT	4e7dc4

    (2664) 0x4e7fc4 CBZ	X17, 4e7e04

    (2664) 0x4e7fc8 LDR	X1, [X18, X5]

    (2664) 0x4e7fcc ADD	X4, X18, X8

    (2664) 0x4e7fd0 LDR	X30, [X18, X8]

    (2664) 0x4e7fd4 CMP	X1, X30

    (2664) 0x4e7fd8 B.GE	4e7e04

    (2664) 0x4e7fdc LDR	X28, [SP, #136]

      (2665) 0x4e7fe0 UBFM	X23, X9, #61, #60

      (2665) 0x4e7fe4 LDR	X5, [X6, X1,LSL #3]

      (2665) 0x4e7fe8 LDR	D27, [X7, X1,LSL #3]

      (2665) 0x4e7fec LDR	X8, [X11, X5,LSL #3]

      (2665) 0x4e7ff0 FMUL	D18, D28, D27

      (2665) 0x4e7ff4 ADD	X15, X26, X8

      (2665) 0x4e7ff8 UBFM	X3, X15, #61, #60

      (2665) 0x4e7ffc LDR	X14, [X0, X3]

      (2665) 0x4e8000 UBFM	X5, X14, #61, #60

      (2665) 0x4e8004 CMP	X25, X14

      (2665) 0x4e8008 B.GT	4e8028

      (2665) 0x4e800c LDR	D26, [X28, X5]

      (2665) 0x4e8010 ADD	X1, X1, #1

      (2665) 0x4e8014 FADD	D19, D26, D18

      (2665) 0x4e8018 STR	D19, [X28, X5]

      (2665) 0x4e801c CMP	X1, X30

      (2665) 0x4e8020 B.LT	4e7fe0

    (2664) 0x4e8024 B	4e7e04

      (2665) 0x4e8028 LDR	X30, [SP, #112]

      (2665) 0x4e802c ADD	X1, X1, #1

      (2665) 0x4e8030 STR	X9, [X0, X3]

      (2665) 0x4e8034 ADD	X9, X9, #1

      (2665) 0x4e8038 STR	D18, [X28, X23]

      (2665) 0x4e803c STR	X8, [X30, X23]

      (2665) 0x4e8040 LDR	X30, [X4]

      (2665) 0x4e8044 CMP	X30, X1

      (2665) 0x4e8048 B.GT	4e7fe0

    (2664) 0x4e804c B	4e7e04

      (2661) 0x4e8050 STR	X2, [X0, X7]

      (2661) 0x4e8054 ADD	X1, X1, #1

      (2661) 0x4e8058 ADD	X2, X2, #1

      (2661) 0x4e805c STR	D4, [X19, X8]

      (2661) 0x4e8060 STR	X6, [X24, X8]

      (2661) 0x4e8064 LDR	X30, [X12]

      (2661) 0x4e8068 CMP	X30, X1

      (2661) 0x4e806c B.GT	4e7f40

    (2660) 0x4e8070 LDR	X12, [X21, #8]

    (2660) 0x4e8074 ADD	X13, X13, #1

    (2660) 0x4e8078 CMP	X12, X13

    (2660) 0x4e807c B.GT	4e7eb0

  (2659) 0x4e8080 B	4e7f8c

      (2662) 0x4e8084 STR	X9, [X0, X5]

      (2662) 0x4e8088 ADD	X1, X1, #1

      (2662) 0x4e808c ADD	X9, X9, #1

      (2662) 0x4e8090 STR	D2, [X23, X28]

      (2662) 0x4e8094 STR	X10, [X4, X28]

      (2662) 0x4e8098 LDR	X11, [X12]

      (2662) 0x4e809c CMP	X11, X1

      (2662) 0x4e80a0 B.GT	4e7ee0

    (2660) 0x4e80a4 B	4e7f20

0x4e80a8 LDR	D15, [SP, #96]

0x4e80ac LDP	X19, X20, [SP, #16]

0x4e80b0 LDP	X21, X22, [SP, #32]

0x4e80b4 LDP	X23, X24, [SP, #48]

0x4e80b8 LDP	X25, X26, [SP, #64]

0x4e80bc LDP	X27, X28, [SP, #80]

0x4e80c0 LDP	X29, X30, [SP], #320

0x4e80c4 B	5294c0

0x4e80c8 MOVZ	X1, #8

0x4e80cc ADD	X0, X26, X17

0x4e80d0 STP	X13, X18, [SP, #128]

0x4e80d4 STR	X3, [SP, #144]

0x4e80d8 STP	X4, X5, [SP, #160]

0x4e80dc STP	X6, X7, [SP, #200]

0x4e80e0 STP	X14, X15, [SP, #216]

0x4e80e4 STP	X9, X8, [SP, #232]

0x4e80e8 STR	X12, [SP, #248]

0x4e80ec BL	529428

0x4e80f0 LDR	X10, [SP, #248]

0x4e80f4 MOVZ	X1, #0

0x4e80f8 MOVN	X12, #0

0x4e80fc LDP	X13, X18, [SP, #128]

0x4e8100 LDP	X4, X5, [SP, #160]

0x4e8104 LDP	X6, X7, [SP, #200]

0x4e8108 LDP	X14, X15, [SP, #216]

0x4e810c LDP	X9, X8, [SP, #232]

0x4e8110 LDR	X11, [X10, #184]

0x4e8114 LDR	X3, [SP, #144]

0x4e8118 LDR	X2, [X11]

0x4e811c ADD	X10, X26, X2

0x4e8120 CMP	X10, #0

0x4e8124 B.LE	4e7d38

(2667) 0x4e8128 STR	X12, [X0, X1,LSL #3]

(2667) 0x4e812c ADD	X1, X1, #1

(2667) 0x4e8130 LDR	X30, [X11]

(2667) 0x4e8134 ADD	X16, X26, X30

(2667) 0x4e8138 CMP	X16, X1

(2667) 0x4e813c B.GT	4e8128

0x4e8140 B	4e7d38

0x4e8144 ADD	X8, X25, X1

0x4e8148 ADD	X13, X25, X9

0x4e814c B	4e7d08

Coverage (%)	Name	Source Location	Module
►98.69+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.31+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_ParMatmul	par_csr_matop.c:998	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	par_csr_matop.c:829-995
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:829-832,840-859,865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989,995.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 30.50 to 3.50 cycles (8.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 35% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 30.50 to 10.25 cycles (2.98x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:857
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:840
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:841

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	129
nb uops	129
loop length	516
used w registers	0
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	59

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.13 cycles
front end	16.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	7.75	7.75	7.75	7.75	0.50	0.50	0.00	0.00	30.50	30.17	30.33	18.00	18.00
cycles	5.50	5.50	7.75	7.75	7.75	7.75	0.50	0.50	0.00	0.00	30.50	30.17	30.33	18.00	18.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	16.13
Dispatch	30.50
DIV/SQRT	5.00-20.00
Overall L1	30.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	35%
load	37%
store	36%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 30.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4e7c00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #704]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X25, X14, [X2, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X7, [X2, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X27, [X2, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X2, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X7, X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [X2, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X3, [X2, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X2, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X2, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X2, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X3, [SP, #288]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X26, [X2, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X10, [X2, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X18, [X2, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [X2, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [X2, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X2, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X2, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D15, [X2, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STP X2, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X13, [X2, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X2, #224]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X2, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X2, #240]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X17, [SP, #256]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X20, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 52c0a0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
BL 52c080 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X0, X25, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X12, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB X25, X0, X2, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MUL X1, X20, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP X20, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X9, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.GE 4e8144 <hypre_ParMatmul._omp_fn.3+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X20, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X20, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X12, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X12, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X20, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, X26, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X20, [X20, X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X2, X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 4e80c8 <hypre_ParMatmul._omp_fn.3+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X12, X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X17, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4e80a8 <hypre_ParMatmul._omp_fn.3+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X16, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X23, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X23, [SP, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X13, X14, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X18, X28, [SP, #296]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X23, 4e7e48 <hypre_ParMatmul._omp_fn.3+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #320	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 5294c0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X26, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVN X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP X13, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X11, [X10, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4e7d38 <hypre_ParMatmul._omp_fn.3+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e7d38 <hypre_ParMatmul._omp_fn.3+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X25, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X25, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 4e7d08 <hypre_ParMatmul._omp_fn.3+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	par_csr_matop.c:829-995
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 30.50 to 3.50 cycles (8.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:857
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:840
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:841

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	129
nb uops	129
loop length	516
used w registers	0
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	59

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.13 cycles
front end	16.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	7.75	7.75	7.75	7.75	0.50	0.50	0.00	0.00	30.50	30.17	30.33	18.00	18.00
cycles	5.50	5.50	7.75	7.75	7.75	7.75	0.50	0.50	0.00	0.00	30.50	30.17	30.33	18.00	18.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	16.13
Dispatch	30.50
DIV/SQRT	5.00-20.00
Overall L1	30.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	35%
load	37%
store	36%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 30.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4e7c00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #704]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X25, X14, [X2, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X7, [X2, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X27, [X2, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X2, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X7, X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [X2, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X3, [X2, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X2, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X2, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X2, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X3, [SP, #288]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X26, [X2, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X10, [X2, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X18, [X2, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [X2, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [X2, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X2, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X2, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D15, [X2, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STP X2, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X13, [X2, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X2, #224]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X2, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X2, #240]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X17, [SP, #256]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X20, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 52c0a0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
BL 52c080 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X0, X25, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X12, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB X25, X0, X2, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MUL X1, X20, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP X20, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X9, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.GE 4e8144 <hypre_ParMatmul._omp_fn.3+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X20, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X20, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X12, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X12, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X20, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, X26, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X20, [X20, X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X2, X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 4e80c8 <hypre_ParMatmul._omp_fn.3+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X12, X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X17, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4e80a8 <hypre_ParMatmul._omp_fn.3+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X16, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X23, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X23, [SP, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X13, X14, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X18, X28, [SP, #296]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X23, 4e7e48 <hypre_ParMatmul._omp_fn.3+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #320	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 5294c0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X26, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVN X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP X13, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X11, [X10, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4e7d38 <hypre_ParMatmul._omp_fn.3+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e7d38 <hypre_ParMatmul._omp_fn.3+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X25, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X25, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 4e7d08 <hypre_ParMatmul._omp_fn.3+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul._omp_fn.3–	0.88	0.37
○Loop 2667 - par_csr_matop.c:858-859 - exec	0.01	0.01
▼Loop 2663 - par_csr_matop.c:865-989 - exec–	0.00	0.00
▼Loop 2659 - par_csr_matop.c:865-989 - exec–	0.01	0.01
▼Loop 2664 - par_csr_matop.c:937-989 - exec–	0.18	0.06
○Loop 2666 - par_csr_matop.c:946-965 - exec	0.68	0.21
○Loop 2665 - par_csr_matop.c:970-989 - exec	0.00	0.00
▼Loop 2660 - par_csr_matop.c:888-928 - exec–	0.00	0.00
○Loop 2661 - par_csr_matop.c:917-928 - exec	0.00	0.00
○Loop 2662 - par_csr_matop.c:897-915 - exec	0.00	0.00

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Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code