OV - exec - Function hypre_CSRMatrixTranspose._omp

	Function: hypre_CSRMatrixTranspose._omp_fn.0	Module: exec	Source: csr_matop.c:380-560 [...]	Coverage (incl. loops): 0.10% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 380 - 560

--------------------------------------------------------------------------------

380:   return idx%dim1*dim2 + idx/dim1;

[...]

463: #pragma omp parallel

464: #endif

465:    {

466:    HYPRE_Int num_threads = hypre_NumActiveThreads();

467:    HYPRE_Int my_thread_num = hypre_GetThreadNum();

468:

469:    HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

470:    HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

471:    hypre_assert(iBegin <= iEnd);

472:    hypre_assert(iBegin >= 0 && iBegin <= num_rowsA);

473:    hypre_assert(iEnd >= 0 && iEnd <= num_rowsA);

474:

475:    HYPRE_Int i, j;

476:    memset(bucket + my_thread_num*num_colsA, 0, sizeof(HYPRE_Int)*num_colsA);

[...]

483:    for (j = A_i[iBegin]; j < A_i[iEnd]; ++j) {

484:      HYPRE_Int idx = A_j[j];

485:      bucket[my_thread_num*num_colsA + idx]++;

[...]

493: #pragma omp barrier

494: #endif

495:

496:    for (i = my_thread_num*num_colsA + 1; i < (my_thread_num + 1)*num_colsA; ++i) {

497:      HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

498:      HYPRE_Int transpose_i_minus_1 = transpose_idx(i - 1, num_threads, num_colsA);

499:

500:      bucket[transpose_i] += bucket[transpose_i_minus_1];

501:    }

502:

503: #ifdef HYPRE_USING_OPENMP

504: #pragma omp barrier

505: #pragma omp master

506: #endif

507:    {

508:      for (i = 1; i < num_threads; ++i) {

509:        HYPRE_Int j0 = num_colsA*i - 1, j1 = num_colsA*(i + 1) - 1;

510:        HYPRE_Int transpose_j0 = transpose_idx(j0, num_threads, num_colsA);

511:        HYPRE_Int transpose_j1 = transpose_idx(j1, num_threads, num_colsA);

512:

513:        bucket[transpose_j1] += bucket[transpose_j0];

514:      }

515:    }

516: #ifdef HYPRE_USING_OPENMP

517: #pragma omp barrier

518: #endif

519:

520:    if (my_thread_num > 0) {

521:      HYPRE_Int transpose_i0 = transpose_idx(num_colsA*my_thread_num - 1, num_threads, num_colsA);

522:      HYPRE_Int offset = bucket[transpose_i0];

523:

524:      for (i = my_thread_num*num_colsA; i < (my_thread_num + 1)*num_colsA - 1; ++i) {

525:        HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

526:

527:        bucket[transpose_i] += offset;

528:      }

529:    }

530:

531: #ifdef HYPRE_USING_OPENMP

532: #pragma omp barrier

[...]

539:    if (data) {

540:       for (i = iEnd - 1; i >= iBegin; --i) {

541:         for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) {

542:           HYPRE_Int idx = A_j[j];

543:           --bucket[my_thread_num*num_colsA + idx];

544:

545:           HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx];

546:

547:           AT_data[offset] = A_data[j];

548:           AT_j[offset] = i;

549:         }

550:       }

551:    }

552:    else {

553:       for (i = iEnd - 1; i >= iBegin; --i) {

554:         for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) {

555:           HYPRE_Int idx = A_j[j];

556:           --bucket[my_thread_num*num_colsA + idx];

557:

558:           HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx];

559:

560:           AT_j[offset] = i;

0x5171a0 STP	X29, X30, [SP, #896]!

0x5171a4 ADD	X29, SP, #0

0x5171a8 STP	X19, X20, [SP, #16]

0x5171ac STP	X21, X22, [SP, #32]

0x5171b0 STP	X23, X24, [SP, #48]

0x5171b4 STP	X25, X26, [SP, #64]

0x5171b8 STP	X27, X28, [SP, #80]

0x5171bc LDP	X19, X1, [X0]

0x5171c0 LDP	X28, X22, [X0, #16]

0x5171c4 LDP	X23, X21, [X0, #32]

0x5171c8 LDP	X27, X26, [X0, #48]

0x5171cc LDP	X24, X20, [X0, #64]

0x5171d0 STR	X1, [SP, #120]

0x5171d4 BL	52c080

0x5171d8 ORR	X25, XZR, X0

0x5171dc BL	52c0a0

0x5171e0 ORR	X2, XZR, X0

0x5171e4 ORR	X0, XZR, X19

0x5171e8 STR	X2, [SP, #104]

0x5171ec BL	51c564

0x5171f0 ORR	X3, XZR, X0

0x5171f4 ORR	X0, XZR, X19

0x5171f8 STR	X3, [SP, #96]

0x5171fc BL	51c608

0x517200 ORR	X19, XZR, X0

0x517204 LDR	X0, [SP, #96]

0x517208 CMP	X0, X19

0x51720c B.GT	5177a0

0x517210 LDR	X8, [SP, #96]

0x517214 CMP	X8, #0

0x517218 CCMP	X21, X8, #1, #10

0x51721c B.LT	5177e4

0x517220 CMP	X19, #0

0x517224 CCMP	X21, X19, #1, #10

0x517228 B.LT	517824

0x51722c LDR	X16, [SP, #104]

0x517230 UBFM	X2, X27, #61, #60

0x517234 MOVZ	W1, #0

0x517238 MUL	X21, X27, X16

0x51723c ADD	X0, X20, X21,LSL #3

0x517240 BL	410340

0x517244 LDR	X1, [SP, #96]

0x517248 ADD	X3, X22, X19,LSL #3

0x51724c LDR	X0, [X22, X19,LSL #3]

0x517250 LDR	X2, [X22, X1,LSL #3]

0x517254 CMP	X2, X0

0x517258 B.GE	517288

0x51725c HINT	#0

(3220) 0x517260 LDR	X17, [X23, X2,LSL #3]

(3220) 0x517264 ADD	X2, X2, #1

(3220) 0x517268 ADD	X30, X21, X17

(3220) 0x51726c UBFM	X4, X30, #61, #60

(3220) 0x517270 LDR	X5, [X20, X4]

(3220) 0x517274 ADD	X6, X5, #1

(3220) 0x517278 STR	X6, [X20, X4]

(3220) 0x51727c LDR	X7, [X3]

(3220) 0x517280 CMP	X7, X2

(3220) 0x517284 B.GT	517260

0x517288 BL	410120

0x51728c ADD	X8, X27, X21

0x517290 ADD	X0, X21, #1

0x517294 STR	X8, [SP, #112]

0x517298 CMP	X27, #1

0x51729c B.LE	51741c

0x5172a0 SUB	X9, X8, X0

0x5172a4 ANDS	X10, X9, #0x3

0x5172a8 B.EQ	517360

0x5172ac CMP	X10, #1

0x5172b0 B.EQ	517320

0x5172b4 CMP	X10, #2

0x5172b8 B.EQ	5172ec

0x5172bc SDIV	X11, X0, X25

0x5172c0 SDIV	X12, X21, X25

0x5172c4 MSUB	X13, X11, X25, X0

0x5172c8 ADD	X0, X0, #1

0x5172cc MADD	X14, X13, X27, X11

0x5172d0 MSUB	X15, X12, X25, X21

0x5172d4 ADD	X18, X20, X14,LSL #3

0x5172d8 MADD	X16, X15, X27, X12

0x5172dc LDR	X1, [X18]

0x5172e0 LDR	X3, [X20, X16,LSL #3]

0x5172e4 ADD	X17, X1, X3

0x5172e8 STR	X17, [X18]

0x5172ec SDIV	X30, X0, X25

0x5172f0 SUB	X2, X0, #1

0x5172f4 SDIV	X4, X2, X25

0x5172f8 MSUB	X5, X30, X25, X0

0x5172fc ADD	X0, X0, #1

0x517300 MADD	X6, X5, X27, X30

0x517304 MSUB	X7, X4, X25, X2

0x517308 ADD	X8, X20, X6,LSL #3

0x51730c MADD	X9, X7, X27, X4

0x517310 LDR	X11, [X8]

0x517314 LDR	X10, [X20, X9,LSL #3]

0x517318 ADD	X12, X11, X10

0x51731c STR	X12, [X8]

0x517320 SDIV	X14, X0, X25

0x517324 SUB	X13, X0, #1

0x517328 LDR	X5, [SP, #112]

0x51732c SDIV	X15, X13, X25

0x517330 MSUB	X18, X14, X25, X0

0x517334 ADD	X0, X0, #1

0x517338 MADD	X16, X18, X27, X14

0x51733c MSUB	X3, X15, X25, X13

0x517340 ADD	X1, X20, X16,LSL #3

0x517344 MADD	X17, X3, X27, X15

0x517348 LDR	X30, [X1]

0x51734c LDR	X2, [X20, X17,LSL #3]

0x517350 ADD	X4, X30, X2

0x517354 STR	X4, [X1]

0x517358 CMP	X0, X5

0x51735c B.EQ	51741c

(3219) 0x517360 SUB	X6, X0, #1

(3219) 0x517364 SDIV	X7, X0, X25

(3219) 0x517368 ADD	X15, X0, #1

(3219) 0x51736c ADD	X18, X0, #2

(3219) 0x517370 ADD	X1, X0, #3

(3219) 0x517374 ORR	X3, XZR, X18

(3219) 0x517378 SDIV	X8, X6, X25

(3219) 0x51737c SDIV	X11, X15, X25

(3219) 0x517380 MSUB	X9, X7, X25, X0

(3219) 0x517384 ADD	X0, X0, #4

(3219) 0x517388 SDIV	X12, X18, X25

(3219) 0x51738c MSUB	X10, X8, X25, X6

(3219) 0x517390 MADD	X16, X9, X27, X7

(3219) 0x517394 MSUB	X30, X11, X25, X15

(3219) 0x517398 MADD	X14, X10, X27, X8

(3219) 0x51739c UBFM	X13, X16, #61, #60

(3219) 0x5173a0 SDIV	X6, X1, X25

(3219) 0x5173a4 LDR	X17, [X20, X13]

(3219) 0x5173a8 LDR	X2, [X20, X14,LSL #3]

(3219) 0x5173ac MADD	X4, X30, X27, X11

(3219) 0x5173b0 ORR	X11, XZR, X12

(3219) 0x5173b4 MSUB	X18, X12, X25, X18

(3219) 0x5173b8 UBFM	X7, X4, #61, #60

(3219) 0x5173bc ADD	X5, X17, X2

(3219) 0x5173c0 MADD	X10, X18, X27, X12

(3219) 0x5173c4 MSUB	X2, X11, X25, X3

(3219) 0x5173c8 STR	X5, [X20, X13]

(3219) 0x5173cc LDR	X15, [X20, X16,LSL #3]

(3219) 0x5173d0 UBFM	X14, X10, #61, #60

(3219) 0x5173d4 MSUB	X16, X6, X25, X1

(3219) 0x5173d8 MADD	X1, X2, X27, X11

(3219) 0x5173dc LDR	X8, [X20, X7]

(3219) 0x5173e0 MADD	X12, X16, X27, X6

(3219) 0x5173e4 UBFM	X30, X12, #61, #60

(3219) 0x5173e8 ADD	X9, X8, X15

(3219) 0x5173ec STR	X9, [X20, X7]

(3219) 0x5173f0 LDR	X13, [X20, X4,LSL #3]

(3219) 0x5173f4 LDR	X17, [X20, X14]

(3219) 0x5173f8 LDR	X7, [SP, #112]

(3219) 0x5173fc ADD	X3, X17, X13

(3219) 0x517400 STR	X3, [X20, X14]

(3219) 0x517404 LDR	X4, [X20, X30]

(3219) 0x517408 LDR	X5, [X20, X1,LSL #3]

(3219) 0x51740c ADD	X6, X4, X5

(3219) 0x517410 STR	X6, [X20, X30]

(3219) 0x517414 CMP	X0, X7

(3219) 0x517418 B.NE	517360

0x51741c BL	410120

0x517420 BL	4101c0

0x517424 CBNZ	W0, 517560

0x517428 CMP	X25, #1

0x51742c B.LE	517560

0x517430 SUB	X15, X27, #1

0x517434 MOVZ	X0, #1

0x517438 SDIV	X18, X15, X25

0x51743c MSUB	X8, X18, X25, X15

0x517440 MADD	X11, X8, X27, X18

0x517444 LDR	X2, [X20, X11,LSL #3]

0x517448 CMP	X27, X0

0x51744c B.NE	517974

0x517450 SUB	X9, X25, #1

0x517454 ANDS	X5, X9, #0x3

0x517458 B.EQ	5174d4

0x51745c CMP	X5, X0

0x517460 B.EQ	5174ac

0x517464 CMP	X5, #2

0x517468 B.EQ	51748c

0x51746c SDIV	X6, X27, X25

0x517470 MOVZ	X0, #2

0x517474 MSUB	X3, X6, X25, X27

0x517478 ADD	X7, X6, X3

0x51747c ADD	X15, X20, X7,LSL #3

0x517480 LDR	X18, [X15]

0x517484 ADD	X2, X2, X18

0x517488 STR	X2, [X15]

0x51748c SDIV	X8, X0, X25

0x517490 MSUB	X11, X8, X25, X0

0x517494 ADD	X0, X0, #1

0x517498 ADD	X10, X8, X11

0x51749c ADD	X16, X20, X10,LSL #3

0x5174a0 LDR	X14, [X16]

0x5174a4 ADD	X2, X2, X14

0x5174a8 STR	X2, [X16]

0x5174ac SDIV	X17, X0, X25

0x5174b0 MSUB	X30, X17, X25, X0

0x5174b4 ADD	X0, X0, #1

0x5174b8 ADD	X12, X17, X30

0x5174bc ADD	X13, X20, X12,LSL #3

0x5174c0 LDR	X1, [X13]

0x5174c4 ADD	X2, X2, X1

0x5174c8 STR	X2, [X13]

0x5174cc CMP	X0, X25

0x5174d0 B.EQ	517560

(3218) 0x5174d4 SDIV	X4, X0, X25

(3218) 0x5174d8 ADD	X5, X0, #1

(3218) 0x5174dc ADD	X7, X0, #2

(3218) 0x5174e0 ADD	X6, X0, #3

(3218) 0x5174e4 SDIV	X15, X5, X25

(3218) 0x5174e8 SDIV	X10, X7, X25

(3218) 0x5174ec MSUB	X9, X4, X25, X0

(3218) 0x5174f0 ADD	X0, X0, #4

(3218) 0x5174f4 MSUB	X8, X15, X25, X5

(3218) 0x5174f8 ADD	X3, X4, X9

(3218) 0x5174fc UBFM	X18, X3, #61, #60

(3218) 0x517500 LDR	X11, [X20, X18]

(3218) 0x517504 ADD	X16, X15, X8

(3218) 0x517508 UBFM	X14, X16, #61, #60

(3218) 0x51750c MSUB	X12, X10, X25, X7

(3218) 0x517510 ADD	X1, X10, X12

(3218) 0x517514 ADD	X17, X2, X11

(3218) 0x517518 SDIV	X2, X6, X25

(3218) 0x51751c UBFM	X4, X1, #61, #60

(3218) 0x517520 STR	X17, [X20, X18]

(3218) 0x517524 LDR	X30, [X20, X14]

(3218) 0x517528 ADD	X13, X17, X30

(3218) 0x51752c MSUB	X5, X2, X25, X6

(3218) 0x517530 STR	X13, [X20, X14]

(3218) 0x517534 LDR	X6, [X20, X4]

(3218) 0x517538 ADD	X7, X2, X5

(3218) 0x51753c UBFM	X15, X7, #61, #60

(3218) 0x517540 ADD	X9, X13, X6

(3218) 0x517544 STR	X9, [X20, X4]

(3218) 0x517548 LDR	X3, [X20, X15]

(3218) 0x51754c ADD	X2, X9, X3

(3218) 0x517550 STR	X2, [X20, X15]

(3218) 0x517554 CMP	X0, X25

(3218) 0x517558 B.NE	5174d4

0x51755c HINT	#0

0x517560 BL	410120

0x517564 LDR	X0, [SP, #104]

0x517568 CMP	X0, #0

0x51756c B.LE	51768c

0x517570 SUB	X18, X21, #1

0x517574 LDR	X8, [SP, #112]

0x517578 SDIV	X11, X18, X25

0x51757c SUB	X16, X8, #1

0x517580 MSUB	X10, X11, X25, X18

0x517584 MADD	X14, X10, X27, X11

0x517588 LDR	X17, [X20, X14,LSL #3]

0x51758c CMP	X21, X16

0x517590 B.GE	51768c

0x517594 ORR	X18, XZR, X21

0x517598 CMP	X27, #1

0x51759c B.NE	51785c

0x5175a0 SUB	X27, X16, X21

0x5175a4 ANDS	X1, X27, #0x3

0x5175a8 B.EQ	517604

0x5175ac CMP	X1, #1

0x5175b0 B.EQ	5175dc

0x5175b4 CMP	X1, #2

0x5175b8 B.NE	517950

0x5175bc SDIV	X12, X18, X25

0x5175c0 MSUB	X13, X12, X25, X18

0x5175c4 ADD	X18, X18, #1

0x5175c8 ADD	X4, X12, X13

0x5175cc ADD	X5, X20, X4,LSL #3

0x5175d0 LDR	X6, [X5]

0x5175d4 ADD	X7, X6, X17

0x5175d8 STR	X7, [X5]

0x5175dc SDIV	X15, X18, X25

0x5175e0 MSUB	X9, X15, X25, X18

0x5175e4 ADD	X18, X18, #1

0x5175e8 ADD	X3, X15, X9

0x5175ec ADD	X0, X20, X3,LSL #3

0x5175f0 LDR	X27, [X0]

0x5175f4 ADD	X1, X27, X17

0x5175f8 STR	X1, [X0]

0x5175fc CMP	X16, X18

0x517600 B.EQ	51768c

(3216) 0x517604 SDIV	X8, X18, X25

(3216) 0x517608 ADD	X14, X18, #1

(3216) 0x51760c ADD	X11, X18, #2

(3216) 0x517610 ADD	X10, X18, #3

(3216) 0x517614 SDIV	X30, X14, X25

(3216) 0x517618 SDIV	X2, X11, X25

(3216) 0x51761c MSUB	X12, X8, X25, X18

(3216) 0x517620 ADD	X18, X18, #4

(3216) 0x517624 SDIV	X15, X10, X25

(3216) 0x517628 ADD	X4, X8, X12

(3216) 0x51762c UBFM	X5, X4, #61, #60

(3216) 0x517630 LDR	X6, [X20, X5]

(3216) 0x517634 MSUB	X13, X30, X25, X14

(3216) 0x517638 MSUB	X0, X2, X25, X11

(3216) 0x51763c ADD	X7, X30, X13

(3216) 0x517640 UBFM	X3, X7, #61, #60

(3216) 0x517644 ADD	X27, X2, X0

(3216) 0x517648 ADD	X9, X6, X17

(3216) 0x51764c UBFM	X8, X27, #61, #60

(3216) 0x517650 MSUB	X14, X15, X25, X10

(3216) 0x517654 STR	X9, [X20, X5]

(3216) 0x517658 LDR	X1, [X20, X3]

(3216) 0x51765c ADD	X11, X15, X14

(3216) 0x517660 UBFM	X30, X11, #61, #60

(3216) 0x517664 ADD	X10, X1, X17

(3216) 0x517668 STR	X10, [X20, X3]

(3216) 0x51766c LDR	X2, [X20, X8]

(3216) 0x517670 ADD	X12, X2, X17

(3216) 0x517674 STR	X12, [X20, X8]

(3216) 0x517678 LDR	X13, [X20, X30]

(3216) 0x51767c ADD	X4, X13, X17

(3216) 0x517680 STR	X4, [X20, X30]

(3216) 0x517684 CMP	X16, X18

(3216) 0x517688 B.NE	517604

0x51768c BL	410120

0x517690 LDR	X25, [SP, #120]

0x517694 SUB	X3, X19, #1

0x517698 CBNZ	X25, 517718

0x51769c LDR	X28, [SP, #96]

0x5176a0 CMP	X28, X3

0x5176a4 B.GT	5176fc

0x5176a8 SUB	X26, X28, #1

0x5176ac ADD	X19, X22, #8

(3213) 0x5176b0 LDR	X16, [X19, X3,LSL #3]

(3213) 0x5176b4 LDR	X17, [X22, X3,LSL #3]

(3213) 0x5176b8 SUB	X5, X16, #1

(3213) 0x5176bc CMP	X5, X17

(3213) 0x5176c0 B.LT	5176f0

  (3214) 0x5176c4 LDR	X18, [X23, X5,LSL #3]

  (3214) 0x5176c8 SUB	X5, X5, #1

  (3214) 0x5176cc ADD	X6, X21, X18

  (3214) 0x5176d0 UBFM	X7, X6, #61, #60

  (3214) 0x5176d4 LDR	X15, [X20, X7]

  (3214) 0x5176d8 SUB	X0, X15, #1

  (3214) 0x5176dc STR	X0, [X20, X7]

  (3214) 0x5176e0 STR	X3, [X24, X0,LSL #3]

  (3214) 0x5176e4 LDR	X9, [X22, X3,LSL #3]

  (3214) 0x5176e8 CMP	X9, X5

  (3214) 0x5176ec B.LE	5176c4

(3213) 0x5176f0 SUB	X3, X3, #1

(3213) 0x5176f4 CMP	X3, X26

(3213) 0x5176f8 B.NE	5176b0

0x5176fc LDP	X19, X20, [SP, #16]

0x517700 LDP	X21, X22, [SP, #32]

0x517704 LDP	X23, X24, [SP, #48]

0x517708 LDP	X25, X26, [SP, #64]

0x51770c LDP	X27, X28, [SP, #80]

0x517710 LDP	X29, X30, [SP], #128

0x517714 RET

0x517718 LDR	X27, [SP, #96]

0x51771c CMP	X27, X3

0x517720 B.GT	5176fc

0x517724 SUB	X14, X27, #1

0x517728 ADD	X8, X22, #8

(3211) 0x51772c LDR	X1, [X8, X3,LSL #3]

(3211) 0x517730 LDR	X10, [X22, X3,LSL #3]

(3211) 0x517734 SUB	X30, X1, #1

(3211) 0x517738 CMP	X30, X10

(3211) 0x51773c B.LT	517778

  (3212) 0x517740 LDR	X11, [X23, X30,LSL #3]

  (3212) 0x517744 LDR	D31, [X28, X30,LSL #3]

  (3212) 0x517748 SUB	X30, X30, #1

  (3212) 0x51774c ADD	X2, X21, X11

  (3212) 0x517750 UBFM	X12, X2, #61, #60

  (3212) 0x517754 LDR	X13, [X20, X12]

  (3212) 0x517758 SUB	X4, X13, #1

  (3212) 0x51775c UBFM	X25, X4, #61, #60

  (3212) 0x517760 STR	X4, [X20, X12]

  (3212) 0x517764 STR	D31, [X26, X25]

  (3212) 0x517768 STR	X3, [X24, X25]

  (3212) 0x51776c LDR	X19, [X22, X3,LSL #3]

  (3212) 0x517770 CMP	X19, X30

  (3212) 0x517774 B.LE	517740

(3211) 0x517778 SUB	X3, X3, #1

(3211) 0x51777c CMP	X3, X14

(3211) 0x517780 B.NE	51772c

0x517784 LDP	X19, X20, [SP, #16]

0x517788 LDP	X21, X22, [SP, #32]

0x51778c LDP	X23, X24, [SP, #48]

0x517790 LDP	X25, X26, [SP, #64]

0x517794 LDP	X27, X28, [SP, #80]

0x517798 LDP	X29, X30, [SP], #128

0x51779c RET

0x5177a0 ADRP	X4,

0x5177a4 ADRP	X5,

0x5177a8 ADRP	X6,

0x5177ac ADD	X2, X4, #656

0x5177b0 ADD	X1, X5, #2000

0x5177b4 LDR	X0, [X6, #1776]

0x5177b8 BL	529700

0x5177bc ADRP	X7,

0x5177c0 MOVZ	X3, #0

0x5177c4 ADD	X0, X7, #528

0x5177c8 MOVZ	X2, #1

0x5177cc MOVZ	X1, #471

0x5177d0 BL	52cf20

0x5177d4 LDR	X8, [SP, #96]

0x5177d8 CMP	X8, #0

0x5177dc CCMP	X21, X8, #1, #10

0x5177e0 B.GE	517220

0x5177e4 ADRP	X9,

0x5177e8 ADRP	X10,

0x5177ec ADRP	X11,

0x5177f0 ADD	X2, X9, #616

0x5177f4 ADD	X1, X10, #2000

0x5177f8 LDR	X0, [X11, #1776]

0x5177fc BL	529700

0x517800 ADRP	X12,

0x517804 MOVZ	X3, #0

0x517808 ADD	X0, X12, #528

0x51780c MOVZ	X2, #1

0x517810 MOVZ	X1, #472

0x517814 BL	52cf20

0x517818 CMP	X19, #0

0x51781c CCMP	X21, X19, #1, #10

0x517820 B.GE	51722c

0x517824 ADRP	X13,

0x517828 ADRP	X14,

0x51782c ADRP	X15,

0x517830 ADD	X2, X13, #496

0x517834 ADD	X1, X14, #2000

0x517838 LDR	X0, [X15, #1776]

0x51783c BL	529700

0x517840 ADRP	X18,

0x517844 MOVZ	X3, #0

0x517848 ADD	X0, X18, #528

0x51784c MOVZ	X2, #1

0x517850 MOVZ	X1, #473

0x517854 BL	52cf20

0x517858 B	51722c

0x51785c SUB	X2, X16, X21

0x517860 ORR	X1, XZR, X21

0x517864 ANDS	X30, X2, #0x3

0x517868 B.EQ	5178c4

0x51786c CMP	X30, #1

0x517870 B.EQ	51789c

0x517874 CMP	X30, #2

0x517878 B.NE	517a9c

0x51787c SDIV	X15, X1, X25

0x517880 MSUB	X9, X15, X25, X1

0x517884 ADD	X1, X1, #1

0x517888 MADD	X3, X9, X27, X15

0x51788c ADD	X0, X20, X3,LSL #3

0x517890 LDR	X18, [X0]

0x517894 ADD	X8, X18, X17

0x517898 STR	X8, [X0]

0x51789c SDIV	X11, X1, X25

0x5178a0 MSUB	X10, X11, X25, X1

0x5178a4 ADD	X1, X1, #1

0x5178a8 MADD	X14, X10, X27, X11

0x5178ac ADD	X30, X20, X14,LSL #3

0x5178b0 LDR	X2, [X30]

0x5178b4 ADD	X12, X2, X17

0x5178b8 STR	X12, [X30]

0x5178bc CMP	X1, X16

0x5178c0 B.EQ	51768c

(3215) 0x5178c4 SDIV	X13, X1, X25

(3215) 0x5178c8 ADD	X4, X1, #1

(3215) 0x5178cc ADD	X6, X1, #2

(3215) 0x5178d0 ADD	X5, X1, #3

(3215) 0x5178d4 SDIV	X7, X4, X25

(3215) 0x5178d8 SDIV	X15, X6, X25

(3215) 0x5178dc MSUB	X9, X13, X25, X1

(3215) 0x5178e0 ADD	X1, X1, #4

(3215) 0x5178e4 SDIV	X11, X5, X25

(3215) 0x5178e8 MADD	X18, X9, X27, X13

(3215) 0x5178ec MSUB	X3, X7, X25, X4

(3215) 0x5178f0 MSUB	X14, X15, X25, X6

(3215) 0x5178f4 UBFM	X8, X18, #61, #60

(3215) 0x5178f8 LDR	X10, [X20, X8]

(3215) 0x5178fc MADD	X0, X3, X27, X7

(3215) 0x517900 MADD	X2, X14, X27, X15

(3215) 0x517904 MSUB	X5, X11, X25, X5

(3215) 0x517908 UBFM	X30, X0, #61, #60

(3215) 0x51790c UBFM	X13, X2, #61, #60

(3215) 0x517910 ADD	X12, X10, X17

(3215) 0x517914 MADD	X7, X5, X27, X11

(3215) 0x517918 STR	X12, [X20, X8]

(3215) 0x51791c LDR	X4, [X20, X30]

(3215) 0x517920 UBFM	X9, X7, #61, #60

(3215) 0x517924 ADD	X6, X4, X17

(3215) 0x517928 STR	X6, [X20, X30]

(3215) 0x51792c LDR	X15, [X20, X13]

(3215) 0x517930 ADD	X3, X15, X17

(3215) 0x517934 STR	X3, [X20, X13]

(3215) 0x517938 LDR	X18, [X20, X9]

(3215) 0x51793c ADD	X0, X18, X17

(3215) 0x517940 STR	X0, [X20, X9]

(3215) 0x517944 CMP	X1, X16

(3215) 0x517948 B.NE	5178c4

0x51794c B	51768c

0x517950 SDIV	X8, X21, X25

0x517954 ADD	X18, X21, #1

0x517958 MSUB	X14, X8, X25, X21

0x51795c ADD	X10, X8, X14

0x517960 ADD	X11, X20, X10,LSL #3

0x517964 LDR	X30, [X11]

0x517968 ADD	X2, X30, X17

0x51796c STR	X2, [X11]

0x517970 B	5175bc

0x517974 SUB	X16, X25, X0

0x517978 UBFM	X10, X27, #63, #62

0x51797c ANDS	X14, X16, #0x3

0x517980 SUB	X9, X10, #1

0x517984 B.EQ	517a0c

0x517988 CMP	X14, #1

0x51798c B.EQ	5179e0

0x517990 CMP	X14, #2

0x517994 B.EQ	5179bc

0x517998 SDIV	X13, X9, X25

0x51799c MOVZ	X0, #2

0x5179a0 MSUB	X12, X13, X25, X9

0x5179a4 ADD	X9, X9, X27

0x5179a8 MADD	X17, X12, X27, X13

0x5179ac ADD	X30, X20, X17,LSL #3

0x5179b0 LDR	X1, [X30]

0x5179b4 ADD	X2, X2, X1

0x5179b8 STR	X2, [X30]

0x5179bc SDIV	X3, X9, X25

0x5179c0 ADD	X0, X0, #1

0x5179c4 MSUB	X4, X3, X25, X9

0x5179c8 ADD	X9, X9, X27

0x5179cc MADD	X5, X4, X27, X3

0x5179d0 ADD	X6, X20, X5,LSL #3

0x5179d4 LDR	X7, [X6]

0x5179d8 ADD	X2, X2, X7

0x5179dc STR	X2, [X6]

0x5179e0 SDIV	X15, X9, X25

0x5179e4 ADD	X0, X0, #1

0x5179e8 MSUB	X18, X15, X25, X9

0x5179ec ADD	X9, X9, X27

0x5179f0 MADD	X8, X18, X27, X15

0x5179f4 ADD	X11, X20, X8,LSL #3

0x5179f8 LDR	X10, [X11]

0x5179fc ADD	X2, X2, X10

0x517a00 STR	X2, [X11]

0x517a04 CMP	X25, X0

0x517a08 B.EQ	517560

(3217) 0x517a0c SDIV	X16, X9, X25

(3217) 0x517a10 ADD	X14, X9, X27

(3217) 0x517a14 ADD	X0, X0, #4

(3217) 0x517a18 ADD	X17, X14, X27

(3217) 0x517a1c ADD	X30, X17, X27

(3217) 0x517a20 SDIV	X12, X14, X25

(3217) 0x517a24 SDIV	X5, X17, X25

(3217) 0x517a28 MSUB	X13, X16, X25, X9

(3217) 0x517a2c ADD	X9, X30, X27

(3217) 0x517a30 SDIV	X15, X30, X25

(3217) 0x517a34 MADD	X1, X13, X27, X16

(3217) 0x517a38 MSUB	X4, X12, X25, X14

(3217) 0x517a3c MSUB	X10, X5, X25, X17

(3217) 0x517a40 UBFM	X6, X1, #61, #60

(3217) 0x517a44 LDR	X3, [X20, X6]

(3217) 0x517a48 MADD	X7, X4, X27, X12

(3217) 0x517a4c MSUB	X14, X15, X25, X30

(3217) 0x517a50 UBFM	X8, X7, #61, #60

(3217) 0x517a54 ADD	X18, X2, X3

(3217) 0x517a58 MADD	X2, X10, X27, X5

(3217) 0x517a5c MADD	X12, X14, X27, X15

(3217) 0x517a60 STR	X18, [X20, X6]

(3217) 0x517a64 LDR	X11, [X20, X8]

(3217) 0x517a68 UBFM	X17, X2, #61, #60

(3217) 0x517a6c UBFM	X13, X12, #61, #60

(3217) 0x517a70 ADD	X16, X18, X11

(3217) 0x517a74 STR	X16, [X20, X8]

(3217) 0x517a78 LDR	X30, [X20, X17]

(3217) 0x517a7c ADD	X1, X16, X30

(3217) 0x517a80 STR	X1, [X20, X17]

(3217) 0x517a84 LDR	X4, [X20, X13]

(3217) 0x517a88 ADD	X2, X1, X4

(3217) 0x517a8c STR	X2, [X20, X13]

(3217) 0x517a90 CMP	X25, X0

(3217) 0x517a94 B.NE	517a0c

0x517a98 B	517560

0x517a9c SDIV	X12, X21, X25

0x517aa0 ADD	X1, X21, #1

0x517aa4 MSUB	X13, X12, X25, X21

0x517aa8 MADD	X4, X13, X27, X12

0x517aac ADD	X5, X20, X4,LSL #3

0x517ab0 LDR	X6, [X5]

0x517ab4 ADD	X7, X6, X17

0x517ab8 STR	X7, [X5]

0x517abc B	51787c

Coverage (%)	Name	Source Location	Module
►98.47+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.53+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixTranspose	csr_matop.c:566	exec
○	hypre_ParTMatmul	par_csr_matop.c:3283	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	csr_matop.c:380-560
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,463-476,483-485,493-532,539-560.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 400.00 to 200.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 400.00 to 51.75 cycles (7.73x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CSRMatrixGetLoadBalancedPartitionBegin: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:469
hypre_CSRMatrixGetLoadBalancedPartitionEnd: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:470
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:467
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:466
hypre_error_handler: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:471
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:472
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:473
hypre_fprintf: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:471
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:472
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:473
unknown: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:476
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:493
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:504
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:505
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:517
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:532

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	349
nb uops	347
loop length	1396
used w registers	2
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	43.38 cycles
front end	43.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	29.50	29.50	56.75	56.75	56.75	56.75	0.00	0.00	0.00	0.00	26.17	25.83	26.00	12.50	12.50
cycles	29.50	29.50	56.75	56.75	56.75	56.75	0.00	0.00	0.00	0.00	26.17	25.83	26.00	12.50	12.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

100.00-400.00

Cycles summary

Front-end	43.38
Dispatch	56.75
DIV/SQRT	100.00-400.00
Overall L1	100.00-400.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	27%
load	35%
store	31%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 400.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 5171a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X22, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X26, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X20, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 52c080 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 52c0a0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 51c564 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 51c608 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 5177a0 <hypre_CSRMatrixTranspose._omp_fn.0+0x600>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X8, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 5177e4 <hypre_CSRMatrixTranspose._omp_fn.0+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X19, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 517824 <hypre_CSRMatrixTranspose._omp_fn.0+0x684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X21, X27, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X0, X20, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410340 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X22, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X22, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 517288 <hypre_CSRMatrixTranspose._omp_fn.0+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X27, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 51741c <hypre_CSRMatrixTranspose._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X9, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X10, X9, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 517360 <hypre_CSRMatrixTranspose._omp_fn.0+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 517320 <hypre_CSRMatrixTranspose._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5172ec <hypre_CSRMatrixTranspose._omp_fn.0+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X11, X0, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SDIV X12, X21, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
MSUB X13, X11, X25, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X14, X13, X27, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MSUB X15, X12, X25, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X20, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X16, X15, X27, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X17, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X17, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X30, X0, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SUB X2, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SDIV X4, X2, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
MSUB X5, X30, X25, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X6, X5, X27, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MSUB X7, X4, X25, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X8, X20, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X7, X27, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X12, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X14, X0, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SUB X13, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SDIV X15, X13, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X18, X14, X25, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X16, X18, X27, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MSUB X3, X15, X25, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X1, X20, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X17, X3, X27, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X30, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X30, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X4, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51741c <hypre_CSRMatrixTranspose._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ W0, 517560 <hypre_CSRMatrixTranspose._omp_fn.0+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 517560 <hypre_CSRMatrixTranspose._omp_fn.0+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X15, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X18, X15, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X8, X18, X25, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X11, X8, X27, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X2, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X27, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 517974 <hypre_CSRMatrixTranspose._omp_fn.0+0x7d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X9, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X5, X9, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 5174d4 <hypre_CSRMatrixTranspose._omp_fn.0+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5174ac <hypre_CSRMatrixTranspose._omp_fn.0+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51748c <hypre_CSRMatrixTranspose._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X6, X27, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MOVZ X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X3, X6, X25, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X7, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X20, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X2, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X8, X0, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X11, X8, X25, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X20, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X17, X0, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X30, X17, X25, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X17, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X20, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X0, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 517560 <hypre_CSRMatrixTranspose._omp_fn.0+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 51768c <hypre_CSRMatrixTranspose._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X18, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SDIV X11, X18, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SUB X16, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X10, X11, X25, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD X14, X10, X27, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X17, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51768c <hypre_CSRMatrixTranspose._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X18, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 51785c <hypre_CSRMatrixTranspose._omp_fn.0+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X27, X16, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X1, X27, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 517604 <hypre_CSRMatrixTranspose._omp_fn.0+0x464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5175dc <hypre_CSRMatrixTranspose._omp_fn.0+0x43c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 517950 <hypre_CSRMatrixTranspose._omp_fn.0+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X12, X18, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
MSUB X13, X12, X25, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X20, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X7, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X15, X18, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X9, X15, X25, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X20, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X1, X27, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51768c <hypre_CSRMatrixTranspose._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X3, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CBNZ X25, 517718 <hypre_CSRMatrixTranspose._omp_fn.0+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X28, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 5176fc <hypre_CSRMatrixTranspose._omp_fn.0+0x55c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X26, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X27, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 5176fc <hypre_CSRMatrixTranspose._omp_fn.0+0x55c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X14, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X4, <5437a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X5, <5427a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X6, <5707a8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X4, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X5, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X6, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X7, <5437bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X7, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #471	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X8, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.GE 517220 <hypre_CSRMatrixTranspose._omp_fn.0+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X9, <5437e4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X10, <5427e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X11, <5707ec>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X9, #616	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X10, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X11, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X12, <543800>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X12, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X19, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.GE 51722c <hypre_CSRMatrixTranspose._omp_fn.0+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X13, <543824>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X14, <542828>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X15, <57082c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X13, #496	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X14, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X15, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X18, <543840>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X18, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #473	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51722c <hypre_CSRMatrixTranspose._omp_fn.0+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X2, X16, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X30, X2, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 5178c4 <hypre_CSRMatrixTranspose._omp_fn.0+0x724>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51789c <hypre_CSRMatrixTranspose._omp_fn.0+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 517a9c <hypre_CSRMatrixTranspose._omp_fn.0+0x8fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X15, X1, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X9, X15, X25, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X3, X9, X27, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X0, X20, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X11, X1, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X10, X11, X25, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X14, X10, X27, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X30, X20, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X12, X2, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X12, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X1, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51768c <hypre_CSRMatrixTranspose._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51768c <hypre_CSRMatrixTranspose._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X8, X21, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD X18, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X14, X8, X25, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X10, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X20, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X30, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 5175bc <hypre_CSRMatrixTranspose._omp_fn.0+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X16, X25, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X10, X27, #63, #62	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X14, X16, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB X9, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 517a0c <hypre_CSRMatrixTranspose._omp_fn.0+0x86c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5179e0 <hypre_CSRMatrixTranspose._omp_fn.0+0x840>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5179bc <hypre_CSRMatrixTranspose._omp_fn.0+0x81c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X13, X9, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MOVZ X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X12, X13, X25, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X17, X12, X27, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X30, X20, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X3, X9, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X4, X3, X25, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X5, X4, X27, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X6, X20, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X15, X9, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X18, X15, X25, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X8, X18, X27, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X11, X20, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X2, X2, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X25, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 517560 <hypre_CSRMatrixTranspose._omp_fn.0+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 517560 <hypre_CSRMatrixTranspose._omp_fn.0+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X12, X21, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
ADD X1, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X13, X12, X25, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X4, X13, X27, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X5, X20, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X7, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 51787c <hypre_CSRMatrixTranspose._omp_fn.0+0x6dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	csr_matop.c:380-560
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,463-476,483-485,493-532,539-560.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 400.00 to 51.75 cycles (7.73x speedup).

CALL instructions

Detected function call instructions.

Details

hypre_CSRMatrixGetLoadBalancedPartitionBegin: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:469
hypre_CSRMatrixGetLoadBalancedPartitionEnd: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:470
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:467
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:466
hypre_error_handler: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:471
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:472
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:473
hypre_fprintf: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:471
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:472
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:473
unknown: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:476
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:493
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:504
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:505
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:517
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:532

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	349
nb uops	347
loop length	1396
used w registers	2
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	43.38 cycles
front end	43.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	29.50	29.50	56.75	56.75	56.75	56.75	0.00	0.00	0.00	0.00	26.17	25.83	26.00	12.50	12.50
cycles	29.50	29.50	56.75	56.75	56.75	56.75	0.00	0.00	0.00	0.00	26.17	25.83	26.00	12.50	12.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

100.00-400.00

Cycles summary

Front-end	43.38
Dispatch	56.75
DIV/SQRT	100.00-400.00
Overall L1	100.00-400.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	27%
load	35%
store	31%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 400.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 5171a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X22, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X26, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X20, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 52c080 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 52c0a0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 51c564 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 51c608 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 5177a0 <hypre_CSRMatrixTranspose._omp_fn.0+0x600>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X8, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 5177e4 <hypre_CSRMatrixTranspose._omp_fn.0+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X19, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 517824 <hypre_CSRMatrixTranspose._omp_fn.0+0x684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X21, X27, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X0, X20, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410340 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X22, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X22, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 517288 <hypre_CSRMatrixTranspose._omp_fn.0+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X27, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 51741c <hypre_CSRMatrixTranspose._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X9, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X10, X9, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 517360 <hypre_CSRMatrixTranspose._omp_fn.0+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 517320 <hypre_CSRMatrixTranspose._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5172ec <hypre_CSRMatrixTranspose._omp_fn.0+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X11, X0, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SDIV X12, X21, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
MSUB X13, X11, X25, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X14, X13, X27, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MSUB X15, X12, X25, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X20, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X16, X15, X27, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X17, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X17, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X30, X0, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SUB X2, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SDIV X4, X2, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
MSUB X5, X30, X25, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X6, X5, X27, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MSUB X7, X4, X25, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X8, X20, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X7, X27, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X12, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X14, X0, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SUB X13, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SDIV X15, X13, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X18, X14, X25, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X16, X18, X27, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MSUB X3, X15, X25, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X1, X20, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X17, X3, X27, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X30, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X30, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X4, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51741c <hypre_CSRMatrixTranspose._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ W0, 517560 <hypre_CSRMatrixTranspose._omp_fn.0+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 517560 <hypre_CSRMatrixTranspose._omp_fn.0+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X15, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X18, X15, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X8, X18, X25, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X11, X8, X27, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X2, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X27, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 517974 <hypre_CSRMatrixTranspose._omp_fn.0+0x7d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X9, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X5, X9, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 5174d4 <hypre_CSRMatrixTranspose._omp_fn.0+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5174ac <hypre_CSRMatrixTranspose._omp_fn.0+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51748c <hypre_CSRMatrixTranspose._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X6, X27, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MOVZ X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X3, X6, X25, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X7, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X20, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X2, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X8, X0, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X11, X8, X25, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X20, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X17, X0, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X30, X17, X25, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X17, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X20, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X0, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 517560 <hypre_CSRMatrixTranspose._omp_fn.0+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 51768c <hypre_CSRMatrixTranspose._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X18, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SDIV X11, X18, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SUB X16, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X10, X11, X25, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD X14, X10, X27, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X17, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51768c <hypre_CSRMatrixTranspose._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X18, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 51785c <hypre_CSRMatrixTranspose._omp_fn.0+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X27, X16, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X1, X27, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 517604 <hypre_CSRMatrixTranspose._omp_fn.0+0x464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5175dc <hypre_CSRMatrixTranspose._omp_fn.0+0x43c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 517950 <hypre_CSRMatrixTranspose._omp_fn.0+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X12, X18, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
MSUB X13, X12, X25, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X20, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X7, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X15, X18, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X9, X15, X25, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X20, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X1, X27, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51768c <hypre_CSRMatrixTranspose._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X3, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CBNZ X25, 517718 <hypre_CSRMatrixTranspose._omp_fn.0+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X28, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 5176fc <hypre_CSRMatrixTranspose._omp_fn.0+0x55c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X26, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X27, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 5176fc <hypre_CSRMatrixTranspose._omp_fn.0+0x55c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X14, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X4, <5437a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X5, <5427a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X6, <5707a8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X4, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X5, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X6, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X7, <5437bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X7, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #471	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X8, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.GE 517220 <hypre_CSRMatrixTranspose._omp_fn.0+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X9, <5437e4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X10, <5427e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X11, <5707ec>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X9, #616	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X10, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X11, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X12, <543800>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X12, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X19, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.GE 51722c <hypre_CSRMatrixTranspose._omp_fn.0+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X13, <543824>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X14, <542828>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X15, <57082c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X13, #496	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X14, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X15, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X18, <543840>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X18, #528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #473	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51722c <hypre_CSRMatrixTranspose._omp_fn.0+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X2, X16, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X30, X2, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 5178c4 <hypre_CSRMatrixTranspose._omp_fn.0+0x724>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51789c <hypre_CSRMatrixTranspose._omp_fn.0+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 517a9c <hypre_CSRMatrixTranspose._omp_fn.0+0x8fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X15, X1, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X9, X15, X25, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X3, X9, X27, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X0, X20, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X11, X1, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X10, X11, X25, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X14, X10, X27, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X30, X20, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X12, X2, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X12, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X1, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 51768c <hypre_CSRMatrixTranspose._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51768c <hypre_CSRMatrixTranspose._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X8, X21, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD X18, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X14, X8, X25, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X10, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X20, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X30, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 5175bc <hypre_CSRMatrixTranspose._omp_fn.0+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X16, X25, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X10, X27, #63, #62	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X14, X16, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB X9, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 517a0c <hypre_CSRMatrixTranspose._omp_fn.0+0x86c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5179e0 <hypre_CSRMatrixTranspose._omp_fn.0+0x840>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5179bc <hypre_CSRMatrixTranspose._omp_fn.0+0x81c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X13, X9, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MOVZ X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X12, X13, X25, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X17, X12, X27, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X30, X20, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X3, X9, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X4, X3, X25, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X5, X4, X27, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X6, X20, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X15, X9, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X18, X15, X25, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X8, X18, X27, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X11, X20, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X2, X2, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X25, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 517560 <hypre_CSRMatrixTranspose._omp_fn.0+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 517560 <hypre_CSRMatrixTranspose._omp_fn.0+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X12, X21, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
ADD X1, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MSUB X13, X12, X25, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X4, X13, X27, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X5, X20, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X7, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 51787c <hypre_CSRMatrixTranspose._omp_fn.0+0x6dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixTranspose._omp_fn.0–	0.10	0.04
○Loop 3215 - csr_matop.c:380-527 - exec	0.01	0.01
○Loop 3219 - csr_matop.c:380-500 - exec	0.01	0.01
○Loop 3220 - csr_matop.c:483-485 - exec	0.01	0.01
▼Loop 3211 - csr_matop.c:540-548 - exec–	0.00	0.01
○Loop 3212 - csr_matop.c:541-548 - exec	0.06	0.02
○Loop 3216 - csr_matop.c:380-527 - exec	0.00	0.00
▼Loop 3213 - csr_matop.c:553-560 - exec–	0.00	0.00
○Loop 3214 - csr_matop.c:554-560 - exec	0.00	0.00
○Loop 3218 - csr_matop.c:380-513 - exec	0.00	0.00
○Loop 3217 - csr_matop.c:380-513 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

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Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code