OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace._omp

	Function: hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6	Module: exec	Source: csr_matvec.c:243-404 [...]	Coverage (incl. loops): 17.84% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 243 - 404

--------------------------------------------------------------------------------

243: #pragma omp parallel private(i,jj,tempx)

244: #endif

245:       {

246:       HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

247:       HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

248:       hypre_assert(iBegin <= iEnd);

249:       hypre_assert(iBegin >= 0 && iBegin <= num_rows);

250:       hypre_assert(iEnd >= 0 && iEnd <= num_rows);

251:

252:       if (0 == temp)

253:       {

254:          if (1 == alpha) // JSP: a common path

255:          {

256:             for (i = iBegin; i < iEnd; i++)

257:             {

258:                tempx = 0.0;

259:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

260:                {

261:                   tempx += A_data[jj] * x_data[A_j[jj]];

262:                }

263:                y_data[i] = tempx;

264:             }

265:          } // y = A*x

266:          else if (-1 == alpha)

267:          {

268:             for (i = iBegin; i < iEnd; i++)

269:             {

270:                tempx = 0.0;

271:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

272:                {

273:                   tempx -= A_data[jj] * x_data[A_j[jj]];

274:                }

275:                y_data[i] = tempx;

276:             }

277:          } // y = -A*x

278:          else

279:          {

280:             for (i = iBegin; i < iEnd; i++)

281:             {

282:                tempx = 0.0;

283:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

284:                {

285:                   tempx += A_data[jj] * x_data[A_j[jj]];

286:                }

287:                y_data[i] = alpha*tempx;

288:             }

289:          } // y = alpha*A*x

290:       } // temp == 0

291:       else if (-1 == temp) // beta == -alpha

292:       {

293:          if (1 == alpha) // JSP: a common path

294:          {

295:             for (i = iBegin; i < iEnd; i++)

296:             {

297:                tempx = -b_data[i];

298:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

299:                {

300:                   tempx += A_data[jj] * x_data[A_j[jj]];

301:                }

302:                y_data[i] = tempx;

303:             }

304:          } // y = A*x - y

305:          else if (-1 == alpha) // JSP: a common path

306:          {

307:             for (i = iBegin; i < iEnd; i++)

308:             {

309:                tempx = b_data[i];

310:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

311:                {

312:                   tempx -= A_data[jj] * x_data[A_j[jj]];

313:                }

314:                y_data[i] = tempx;

315:             }

316:          } // y = -A*x + y

317:          else

318:          {

319:             for (i = iBegin; i < iEnd; i++)

320:             {

321:                tempx = -b_data[i];

322:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

323:                {

324:                   tempx += A_data[jj] * x_data[A_j[jj]];

325:                }

326:                y_data[i] = alpha*tempx;

327:             }

328:          } // y = alpha*(A*x - y)

329:       } // temp == -1

330:       else if (1 == temp)

331:       {

332:          if (1 == alpha) // JSP: a common path

333:          {

334:             for (i = iBegin; i < iEnd; i++)

335:             {

336:                tempx = b_data[i];

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

340:                }

341:                y_data[i] = tempx;

342:             }

343:          } // y = A*x + y

344:          else if (-1 == alpha)

345:          {

346:             for (i = iBegin; i < iEnd; i++)

347:             {

348:                tempx = -b_data[i];

349:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

350:                {

351:                   tempx -= A_data[jj] * x_data[A_j[jj]];

352:                }

353:                y_data[i] = tempx;

354:             }

355:          } // y = -A*x - y

356:          else

357:          {

358:             for (i = iBegin; i < iEnd; i++)

359:             {

360:                tempx = b_data[i];

361:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

362:                {

363:                   tempx += A_data[jj] * x_data[A_j[jj]];

364:                }

365:                y_data[i] = alpha*tempx;

[...]

371:          if (1 == alpha) // JSP: a common path

372:          {

373:             for (i = iBegin; i < iEnd; i++)

374:             {

375:                tempx = b_data[i]*temp;

376:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

377:                {

378:                   tempx += A_data[jj] * x_data[A_j[jj]];

379:                }

380:                y_data[i] = tempx;

381:             }

382:          } // y = A*x + temp*y

383:          else if (-1 == alpha)

384:          {

385:             for (i = iBegin; i < iEnd; i++)

386:             {

387:                tempx = -b_data[i]*temp;

388:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

389:                {

390:                   tempx -= A_data[jj] * x_data[A_j[jj]];

391:                }

392:                y_data[i] = tempx;

393:             }

394:          } // y = -A*x - temp*y

395:          else

396:          {

397:             for (i = iBegin; i < iEnd; i++)

398:             {

399:                tempx = b_data[i]*temp;

400:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

401:                {

402:                   tempx += A_data[jj] * x_data[A_j[jj]];

403:                }

404:                y_data[i] = alpha*tempx;

0x51d870 STP	X29, X30, [SP, #912]!

0x51d874 ORR	X1, XZR, X0

0x51d878 ADD	X29, SP, #0

0x51d87c STP	X19, X20, [SP, #16]

0x51d880 STP	X21, X22, [SP, #32]

0x51d884 STP	X23, X24, [SP, #48]

0x51d888 STP	X25, X26, [SP, #64]

0x51d88c STP	D14, D15, [SP, #96]

0x51d890 LDP	X21, X25, [X0, #8]

0x51d894 LDP	X22, X24, [X1, #24]

0x51d898 LDP	X19, X26, [X1, #48]

0x51d89c LDR	D14, [X0]

0x51d8a0 ORR	X0, XZR, X21

0x51d8a4 LDR	D15, [X1, #72]

0x51d8a8 LDR	X23, [X1, #64]

0x51d8ac STR	X27, [SP, #80]

0x51d8b0 LDR	X27, [X1, #40]

0x51d8b4 BL	51c564

0x51d8b8 ORR	X20, XZR, X0

0x51d8bc ORR	X0, XZR, X21

0x51d8c0 BL	51c608

0x51d8c4 ORR	X21, XZR, X0

0x51d8c8 CMP	X20, X0

0x51d8cc B.GT	51dbf4

0x51d8d0 CMP	X20, #0

0x51d8d4 CCMP	X27, X20, #1, #10

0x51d8d8 B.LT	51dbbc

0x51d8dc CMP	X21, #0

0x51d8e0 CCMP	X27, X21, #1, #10

0x51d8e4 B.LT	51db84

0x51d8e8 FCMP	D15, #0

0x51d8ec B.EQ	51d9a8

0x51d8f0 FMOV	D31, #-1.0000000

0x51d8f4 FCMP	D15, D31

0x51d8f8 B.NE	51dae8

0x51d8fc FMOV	D20, #1.0000000

0x51d900 FCMP	D14, D20

0x51d904 B.EQ	51dc2c

0x51d908 FCMP	D14, D31

0x51d90c B.EQ	51dee8

0x51d910 CMP	X20, X21

0x51d914 B.GE	51d988

0x51d918 ADD	X30, X22, #8

0x51d91c CNTD	X27, ALL

0x51d920 PTRUE	P2.B, ALL

(3337) 0x51d924 LDR	X4, [X22, X20,LSL #3]

(3337) 0x51d928 LDR	X2, [X30, X20,LSL #3]

(3337) 0x51d92c LDR	D22, [X26, X20,LSL #3]

(3337) 0x51d930 CMP	X4, X2

(3337) 0x51d934 B.GE	51df64

(3337) 0x51d938 ADD	X5, X25, X4,LSL #3

(3337) 0x51d93c MOVZ	X1, #0

(3337) 0x51d940 SUB	X6, X2, X4

(3337) 0x51d944 ADD	X7, X24, X4,LSL #3

(3337) 0x51d948 WHILELO	P3.D, XZR, X6

(3337) 0x51d94c DUP	Z23.D, #0

  (3338) 0x51d950 LD1D	{Z21.D}, P3/Z, [X7, X1,LSL #3]

  (3338) 0x51d954 LD1D	{Z26.D}, P3/Z, [X5, X1,LSL #3]

  (3338) 0x51d958 LD1D	{Z15.D}, P3/Z, [X19, Z21.D,LSL #3]

  (3338) 0x51d95c ADD	X1, X1, X27

  (3338) 0x51d960 FMLA	Z23.D, P3/M, Z15.D, Z26.D

  (3338) 0x51d964 WHILELO	P3.D, X1, X6

  (3338) 0x51d968 B.NE	51d950

(3337) 0x51d96c FADDV	D31, P2, Z23.D

(3337) 0x51d970 FSUB	D30, D31, S22

(3337) 0x51d974 FMUL	D1, D14, D30

(3337) 0x51d978 STR	D1, [X23, X20,LSL #3]

(3337) 0x51d97c ADD	X20, X20, #1

(3337) 0x51d980 CMP	X21, X20

(3337) 0x51d984 B.NE	51d924

0x51d988 LDR	X27, [SP, #80]

0x51d98c LDP	X19, X20, [SP, #16]

0x51d990 LDP	X21, X22, [SP, #32]

0x51d994 LDP	X23, X24, [SP, #48]

0x51d998 LDP	X25, X26, [SP, #64]

0x51d99c LDP	D14, D15, [SP, #96]

0x51d9a0 LDP	X29, X30, [SP], #112

0x51d9a4 RET

0x51d9a8 FMOV	D29, #1.0000000

0x51d9ac FCMP	D14, D29

0x51d9b0 B.NE	51da48

0x51d9b4 CMP	X20, X21

0x51d9b8 B.GE	51d988

0x51d9bc ADD	X16, X22, #8

0x51d9c0 LDR	X18, [X22, X20,LSL #3]

0x51d9c4 CNTD	X17, ALL

0x51d9c8 PTRUE	P4.B, ALL

0x51d9cc LDR	X30, [X16, X20,LSL #3]

0x51d9d0 CMP	X18, X30

0x51d9d4 B.GE	51da40

0x51d9d8 HINT	#0

0x51d9dc HINT	#0

  (3318) 0x51d9e0 ADD	X27, X25, X18,LSL #3

  (3318) 0x51d9e4 MOVZ	X5, #0

  (3318) 0x51d9e8 SUB	X4, X30, X18

  (3318) 0x51d9ec ADD	X26, X24, X18,LSL #3

  (3318) 0x51d9f0 WHILELO	P5.D, XZR, X4

  (3318) 0x51d9f4 DUP	Z14.D, #0

  (3318) 0x51d9f8 HINT	#0

  (3318) 0x51d9fc HINT	#0

    (3317) 0x51da00 LD1D	{Z3.D}, P5/Z, [X26, X5,LSL #3]

    (3317) 0x51da04 LD1D	{Z5.D}, P5/Z, [X27, X5,LSL #3]

    (3317) 0x51da08 LD1D	{Z2.D}, P5/Z, [X19, Z3.D,LSL #3]

    (3317) 0x51da0c ADD	X5, X5, X17

    (3317) 0x51da10 FMLA	Z14.D, P5/M, Z2.D, Z5.D

    (3317) 0x51da14 WHILELO	P5.D, X5, X4

    (3317) 0x51da18 B.NE	51da00

  (3318) 0x51da1c FADDV	D4, P4, Z14.D

  (3318) 0x51da20 STR	D4, [X23, X20,LSL #3]

  (3318) 0x51da24 ADD	X20, X20, #1

  (3318) 0x51da28 CMP	X21, X20

  (3318) 0x51da2c B.EQ	51d988

  (3318) 0x51da30 LDR	X18, [X22, X20,LSL #3]

  (3318) 0x51da34 LDR	X30, [X16, X20,LSL #3]

  (3318) 0x51da38 CMP	X18, X30

  (3318) 0x51da3c B.LT	51d9e0

(3319) 0x51da40 MOVI	D4, #0

(3319) 0x51da44 B	51da20

0x51da48 FMOV	D18, #-1.0000000

0x51da4c FCMP	D14, D18

0x51da50 B.NE	51dd68

0x51da54 CMP	X20, X21

0x51da58 B.GE	51d988

0x51da5c ADD	X10, X22, #8

0x51da60 LDR	X0, [X22, X20,LSL #3]

0x51da64 CNTD	X11, ALL

0x51da68 PTRUE	P2.B, ALL

0x51da6c LDR	X12, [X10, X20,LSL #3]

0x51da70 CMP	X0, X12

0x51da74 B.GE	51dae0

0x51da78 HINT	#0

0x51da7c HINT	#0

  (3315) 0x51da80 ADD	X3, X25, X0,LSL #3

  (3315) 0x51da84 MOVZ	X15, #0

  (3315) 0x51da88 SUB	X13, X12, X0

  (3315) 0x51da8c ADD	X14, X24, X0,LSL #3

  (3315) 0x51da90 WHILELO	P3.D, XZR, X13

  (3315) 0x51da94 DUP	Z26.D, #0

  (3315) 0x51da98 HINT	#0

  (3315) 0x51da9c HINT	#0

    (3314) 0x51daa0 LD1D	{Z15.D}, P3/Z, [X14, X15,LSL #3]

    (3314) 0x51daa4 LD1D	{Z30.D}, P3/Z, [X3, X15,LSL #3]

    (3314) 0x51daa8 LD1D	{Z31.D}, P3/Z, [X19, Z15.D,LSL #3]

    (3314) 0x51daac ADD	X15, X15, X11

    (3314) 0x51dab0 FMLS	Z26.D, P3/M, Z31.D, Z30.D

    (3314) 0x51dab4 WHILELO	P3.D, X15, X13

    (3314) 0x51dab8 B.NE	51daa0

  (3315) 0x51dabc FADDV	D1, P2, Z26.D

  (3315) 0x51dac0 STR	D1, [X23, X20,LSL #3]

  (3315) 0x51dac4 ADD	X20, X20, #1

  (3315) 0x51dac8 CMP	X21, X20

  (3315) 0x51dacc B.EQ	51d988

  (3315) 0x51dad0 LDR	X0, [X22, X20,LSL #3]

  (3315) 0x51dad4 LDR	X12, [X10, X20,LSL #3]

  (3315) 0x51dad8 CMP	X0, X12

  (3315) 0x51dadc B.LT	51da80

(3316) 0x51dae0 MOVI	D1, #0

(3316) 0x51dae4 B	51dac0

0x51dae8 FMOV	D30, #1.0000000

0x51daec FCMP	D15, D30

0x51daf0 B.NE	51dcd0

0x51daf4 FCMP	D14, D30

0x51daf8 B.EQ	51ddf0

0x51dafc FCMP	D14, D31

0x51db00 B.NE	51df6c

0x51db04 CMP	X20, X21

0x51db08 B.GE	51d988

0x51db0c ADD	X5, X22, #8

0x51db10 CNTD	X6, ALL

0x51db14 PTRUE	P6.B, ALL

0x51db18 HINT	#0

0x51db1c HINT	#0

(3330) 0x51db20 LDR	X7, [X22, X20,LSL #3]

(3330) 0x51db24 LDR	X8, [X5, X20,LSL #3]

(3330) 0x51db28 LDR	D4, [X26, X20,LSL #3]

(3330) 0x51db2c CMP	X7, X8

(3330) 0x51db30 B.GE	51e074

(3330) 0x51db34 ADD	X3, X25, X7,LSL #3

(3330) 0x51db38 MOVZ	X0, #0

(3330) 0x51db3c SUB	X9, X8, X7

(3330) 0x51db40 ADD	X10, X24, X7,LSL #3

(3330) 0x51db44 WHILELO	P7.D, XZR, X9

(3330) 0x51db48 DUP	Z0.D, #0

  (3331) 0x51db4c LD1D	{Z6.D}, P7/Z, [X10, X0,LSL #3]

  (3331) 0x51db50 LD1D	{Z7.D}, P7/Z, [X3, X0,LSL #3]

  (3331) 0x51db54 LD1D	{Z27.D}, P7/Z, [X19, Z6.D,LSL #3]

  (3331) 0x51db58 ADD	X0, X0, X6

  (3331) 0x51db5c FMLS	Z0.D, P7/M, Z27.D, Z7.D

  (3331) 0x51db60 WHILELO	P7.D, X0, X9

  (3331) 0x51db64 B.NE	51db4c

(3330) 0x51db68 FADDV	D16, P6, Z0.D

(3330) 0x51db6c FSUB	D17, D16, S4

(3330) 0x51db70 STR	D17, [X23, X20,LSL #3]

(3330) 0x51db74 ADD	X20, X20, #1

(3330) 0x51db78 CMP	X21, X20

(3330) 0x51db7c B.NE	51db20

0x51db80 B	51d988

0x51db84 ADRP	X9,

0x51db88 ADRP	X10,

0x51db8c ADRP	X11,

0x51db90 ADD	X2, X9, #1096

0x51db94 ADD	X1, X10, #2000

0x51db98 LDR	X0, [X11, #1776]

0x51db9c BL	529700

0x51dba0 ADRP	X12,

0x51dba4 MOVZ	X3, #0

0x51dba8 ADD	X0, X12, #1128

0x51dbac MOVZ	X2, #1

0x51dbb0 MOVZ	X1, #250

0x51dbb4 BL	52cf20

0x51dbb8 B	51d8e8

0x51dbbc ADRP	X5,

0x51dbc0 ADRP	X6,

0x51dbc4 ADRP	X7,

0x51dbc8 ADD	X2, X5, #1216

0x51dbcc ADD	X1, X6, #2000

0x51dbd0 LDR	X0, [X7, #1776]

0x51dbd4 BL	529700

0x51dbd8 ADRP	X8,

0x51dbdc MOVZ	X3, #0

0x51dbe0 ADD	X0, X8, #1128

0x51dbe4 MOVZ	X2, #1

0x51dbe8 MOVZ	X1, #249

0x51dbec BL	52cf20

0x51dbf0 B	51d8dc

0x51dbf4 ADRP	X3,

0x51dbf8 ADRP	X2,

0x51dbfc ADRP	X0,

0x51dc00 ADD	X1, X3, #2000

0x51dc04 ADD	X2, X2, #656

0x51dc08 LDR	X0, [X0, #1776]

0x51dc0c BL	529700

0x51dc10 ADRP	X4,

0x51dc14 MOVZ	X3, #0

0x51dc18 ADD	X0, X4, #1128

0x51dc1c MOVZ	X2, #1

0x51dc20 MOVZ	X1, #248

0x51dc24 BL	52cf20

0x51dc28 B	51d8d0

0x51dc2c CMP	X20, X21

0x51dc30 B.GE	51d988

0x51dc34 ADD	X14, X22, #8

0x51dc38 LDR	X16, [X22, X20,LSL #3]

0x51dc3c CNTD	X15, ALL

0x51dc40 PTRUE	P6.B, ALL

0x51dc44 LDR	X17, [X14, X20,LSL #3]

0x51dc48 LDR	D27, [X26, X20,LSL #3]

0x51dc4c CMP	X16, X17

0x51dc50 B.GE	51dcc8

0x51dc54 HINT	#0

0x51dc58 HINT	#0

0x51dc5c HINT	#0

  (3333) 0x51dc60 ADD	X18, X25, X16,LSL #3

  (3333) 0x51dc64 MOVZ	X4, #0

  (3333) 0x51dc68 SUB	X30, X17, X16

  (3333) 0x51dc6c ADD	X27, X24, X16,LSL #3

  (3333) 0x51dc70 WHILELO	P7.D, XZR, X30

  (3333) 0x51dc74 DUP	Z7.D, #0

  (3333) 0x51dc78 HINT	#0

  (3333) 0x51dc7c HINT	#0

    (3332) 0x51dc80 LD1D	{Z16.D}, P7/Z, [X27, X4,LSL #3]

    (3332) 0x51dc84 LD1D	{Z6.D}, P7/Z, [X18, X4,LSL #3]

    (3332) 0x51dc88 LD1D	{Z17.D}, P7/Z, [X19, Z16.D,LSL #3]

    (3332) 0x51dc8c ADD	X4, X4, X15

    (3332) 0x51dc90 FMLA	Z7.D, P7/M, Z17.D, Z6.D

    (3332) 0x51dc94 WHILELO	P7.D, X4, X30

    (3332) 0x51dc98 B.NE	51dc80

  (3333) 0x51dc9c FADDV	D28, P6, Z7.D

  (3333) 0x51dca0 FSUB	D25, D28, S27

  (3333) 0x51dca4 STR	D25, [X23, X20,LSL #3]

  (3333) 0x51dca8 ADD	X20, X20, #1

  (3333) 0x51dcac CMP	X21, X20

  (3333) 0x51dcb0 B.EQ	51d988

  (3333) 0x51dcb4 LDR	X16, [X22, X20,LSL #3]

  (3333) 0x51dcb8 LDR	X17, [X14, X20,LSL #3]

  (3333) 0x51dcbc LDR	D27, [X26, X20,LSL #3]

  (3333) 0x51dcc0 CMP	X16, X17

  (3333) 0x51dcc4 B.LT	51dc60

(3334) 0x51dcc8 FNEG	D25, D27

(3334) 0x51dccc B	51dca4

0x51dcd0 FCMP	D14, D30

0x51dcd4 B.EQ	51de68

0x51dcd8 FCMP	D14, D31

0x51dcdc B.NE	51dfe8

0x51dce0 CMP	X20, X21

0x51dce4 B.GE	51d988

0x51dce8 ADD	X27, X22, #8

0x51dcec CNTD	X4, ALL

0x51dcf0 PTRUE	P0.B, ALL

0x51dcf4 HINT	#0

0x51dcf8 HINT	#0

0x51dcfc HINT	#0

(3324) 0x51dd00 LDR	D27, [X26, X20,LSL #3]

(3324) 0x51dd04 LDR	X2, [X22, X20,LSL #3]

(3324) 0x51dd08 LDR	X5, [X27, X20,LSL #3]

(3324) 0x51dd0c FMUL	D16, D15, D27

(3324) 0x51dd10 CMP	X2, X5

(3324) 0x51dd14 B.GE	51e06c

(3324) 0x51dd18 ADD	X3, X25, X2,LSL #3

(3324) 0x51dd1c MOVZ	X0, #0

(3324) 0x51dd20 SUB	X6, X5, X2

(3324) 0x51dd24 ADD	X7, X24, X2,LSL #3

(3324) 0x51dd28 WHILELO	P1.D, XZR, X6

(3324) 0x51dd2c DUP	Z17.D, #0

  (3325) 0x51dd30 LD1D	{Z28.D}, P1/Z, [X7, X0,LSL #3]

  (3325) 0x51dd34 LD1D	{Z25.D}, P1/Z, [X3, X0,LSL #3]

  (3325) 0x51dd38 LD1D	{Z29.D}, P1/Z, [X19, Z28.D,LSL #3]

  (3325) 0x51dd3c ADD	X0, X0, X4

  (3325) 0x51dd40 FMLS	Z17.D, P1/M, Z29.D, Z25.D

  (3325) 0x51dd44 WHILELO	P1.D, X0, X6

  (3325) 0x51dd48 B.NE	51dd30

(3324) 0x51dd4c FADDV	D18, P0, Z17.D

(3324) 0x51dd50 FSUB	D19, D18, S16

(3324) 0x51dd54 STR	D19, [X23, X20,LSL #3]

(3324) 0x51dd58 ADD	X20, X20, #1

(3324) 0x51dd5c CMP	X21, X20

(3324) 0x51dd60 B.NE	51dd00

0x51dd64 B	51d988

0x51dd68 CMP	X20, X21

0x51dd6c B.GE	51d988

0x51dd70 ADD	X26, X22, #8

0x51dd74 LDR	X6, [X22, X20,LSL #3]

0x51dd78 CNTD	X5, ALL

0x51dd7c PTRUE	P0.B, ALL

0x51dd80 LDR	X2, [X26, X20,LSL #3]

0x51dd84 CMP	X6, X2

0x51dd88 B.GE	51dde8

  (3312) 0x51dd8c ADD	X7, X25, X6,LSL #3

  (3312) 0x51dd90 MOVZ	X1, #0

  (3312) 0x51dd94 SUB	X8, X2, X6

  (3312) 0x51dd98 ADD	X9, X24, X6,LSL #3

  (3312) 0x51dd9c WHILELO	P1.D, XZR, X8

  (3312) 0x51dda0 DUP	Z19.D, #0

    (3311) 0x51dda4 LD1D	{Z24.D}, P1/Z, [X9, X1,LSL #3]

    (3311) 0x51dda8 LD1D	{Z20.D}, P1/Z, [X7, X1,LSL #3]

    (3311) 0x51ddac LD1D	{Z22.D}, P1/Z, [X19, Z24.D,LSL #3]

    (3311) 0x51ddb0 ADD	X1, X1, X5

    (3311) 0x51ddb4 FMLA	Z19.D, P1/M, Z22.D, Z20.D

    (3311) 0x51ddb8 WHILELO	P1.D, X1, X8

    (3311) 0x51ddbc B.NE	51dda4

  (3312) 0x51ddc0 FADDV	D23, P0, Z19.D

  (3312) 0x51ddc4 FMUL	D21, D14, D23

  (3312) 0x51ddc8 STR	D21, [X23, X20,LSL #3]

  (3312) 0x51ddcc ADD	X20, X20, #1

  (3312) 0x51ddd0 CMP	X21, X20

  (3312) 0x51ddd4 B.EQ	51d988

  (3312) 0x51ddd8 LDR	X6, [X22, X20,LSL #3]

  (3312) 0x51dddc LDR	X2, [X26, X20,LSL #3]

  (3312) 0x51dde0 CMP	X6, X2

  (3312) 0x51dde4 B.LT	51dd8c

(3313) 0x51dde8 MOVI	D21, #0

(3313) 0x51ddec B	51ddc8

0x51ddf0 CMP	X20, X21

0x51ddf4 B.GE	51d988

0x51ddf8 ADD	X11, X22, #8

0x51ddfc CNTD	X12, ALL

0x51de00 PTRUE	P0.B, ALL

(3326) 0x51de04 LDR	X13, [X22, X20,LSL #3]

(3326) 0x51de08 LDR	X14, [X11, X20,LSL #3]

(3326) 0x51de0c LDR	D24, [X26, X20,LSL #3]

(3326) 0x51de10 CMP	X13, X14

(3326) 0x51de14 B.GE	51de54

(3326) 0x51de18 ADD	X15, X25, X13,LSL #3

(3326) 0x51de1c MOVZ	X18, #0

(3326) 0x51de20 SUB	X16, X14, X13

(3326) 0x51de24 ADD	X17, X24, X13,LSL #3

(3326) 0x51de28 WHILELO	P1.D, XZR, X16

(3326) 0x51de2c DUP	Z28.D, #0

  (3327) 0x51de30 LD1D	{Z25.D}, P1/Z, [X17, X18,LSL #3]

  (3327) 0x51de34 LD1D	{Z29.D}, P1/Z, [X15, X18,LSL #3]

  (3327) 0x51de38 LD1D	{Z18.D}, P1/Z, [X19, Z25.D,LSL #3]

  (3327) 0x51de3c ADD	X18, X18, X12

  (3327) 0x51de40 FMLA	Z28.D, P1/M, Z18.D, Z29.D

  (3327) 0x51de44 WHILELO	P1.D, X18, X16

  (3327) 0x51de48 B.NE	51de30

(3326) 0x51de4c FADDV	D19, P0, Z28.D

(3326) 0x51de50 FADD	D24, D24, D19

(3326) 0x51de54 STR	D24, [X23, X20,LSL #3]

(3326) 0x51de58 ADD	X20, X20, #1

(3326) 0x51de5c CMP	X21, X20

(3326) 0x51de60 B.NE	51de04

0x51de64 B	51d988

0x51de68 CMP	X20, X21

0x51de6c B.GE	51d988

0x51de70 ADD	X8, X22, #8

0x51de74 CNTD	X9, ALL

0x51de78 PTRUE	P2.B, ALL

0x51de7c HINT	#0

(3320) 0x51de80 LDR	D24, [X26, X20,LSL #3]

(3320) 0x51de84 LDR	X10, [X22, X20,LSL #3]

(3320) 0x51de88 LDR	X11, [X8, X20,LSL #3]

(3320) 0x51de8c FMUL	D14, D15, D24

(3320) 0x51de90 CMP	X10, X11

(3320) 0x51de94 B.GE	51ded4

(3320) 0x51de98 ADD	X12, X25, X10,LSL #3

(3320) 0x51de9c MOVZ	X15, #0

(3320) 0x51dea0 SUB	X13, X11, X10

(3320) 0x51dea4 ADD	X14, X24, X10,LSL #3

(3320) 0x51dea8 WHILELO	P3.D, XZR, X13

(3320) 0x51deac DUP	Z20.D, #0

  (3321) 0x51deb0 LD1D	{Z22.D}, P3/Z, [X14, X15,LSL #3]

  (3321) 0x51deb4 LD1D	{Z23.D}, P3/Z, [X12, X15,LSL #3]

  (3321) 0x51deb8 LD1D	{Z21.D}, P3/Z, [X19, Z22.D,LSL #3]

  (3321) 0x51debc ADD	X15, X15, X9

  (3321) 0x51dec0 FMLA	Z20.D, P3/M, Z21.D, Z23.D

  (3321) 0x51dec4 WHILELO	P3.D, X15, X13

  (3321) 0x51dec8 B.NE	51deb0

(3320) 0x51decc FADDV	D26, P2, Z20.D

(3320) 0x51ded0 FADD	D14, D14, D26

(3320) 0x51ded4 STR	D14, [X23, X20,LSL #3]

(3320) 0x51ded8 ADD	X20, X20, #1

(3320) 0x51dedc CMP	X21, X20

(3320) 0x51dee0 B.NE	51de80

0x51dee4 B	51d988

0x51dee8 CMP	X20, X21

0x51deec B.GE	51d988

0x51def0 ADD	X8, X22, #8

0x51def4 CNTD	X9, ALL

0x51def8 PTRUE	P4.B, ALL

0x51defc HINT	#0

(3335) 0x51df00 LDR	X10, [X22, X20,LSL #3]

(3335) 0x51df04 LDR	X0, [X8, X20,LSL #3]

(3335) 0x51df08 LDR	D0, [X26, X20,LSL #3]

(3335) 0x51df0c CMP	X10, X0

(3335) 0x51df10 B.GE	51df50

(3335) 0x51df14 ADD	X3, X25, X10,LSL #3

(3335) 0x51df18 MOVZ	X13, #0

(3335) 0x51df1c SUB	X11, X0, X10

(3335) 0x51df20 ADD	X12, X24, X10,LSL #3

(3335) 0x51df24 WHILELO	P5.D, XZR, X11

(3335) 0x51df28 DUP	Z14.D, #0

  (3336) 0x51df2c LD1D	{Z3.D}, P5/Z, [X12, X13,LSL #3]

  (3336) 0x51df30 LD1D	{Z5.D}, P5/Z, [X3, X13,LSL #3]

  (3336) 0x51df34 LD1D	{Z2.D}, P5/Z, [X19, Z3.D,LSL #3]

  (3336) 0x51df38 ADD	X13, X13, X9

  (3336) 0x51df3c FMLS	Z14.D, P5/M, Z2.D, Z5.D

  (3336) 0x51df40 WHILELO	P5.D, X13, X11

  (3336) 0x51df44 B.NE	51df2c

(3335) 0x51df48 FADDV	D4, P4, Z14.D

(3335) 0x51df4c FADD	D0, D0, D4

(3335) 0x51df50 STR	D0, [X23, X20,LSL #3]

(3335) 0x51df54 ADD	X20, X20, #1

(3335) 0x51df58 CMP	X21, X20

(3335) 0x51df5c B.NE	51df00

0x51df60 B	51d988

(3337) 0x51df64 FNEG	D30, D22

(3337) 0x51df68 B	51d974

0x51df6c CMP	X20, X21

0x51df70 B.GE	51d988

0x51df74 ADD	X16, X22, #8

0x51df78 CNTD	X17, ALL

0x51df7c PTRUE	P4.B, ALL

(3328) 0x51df80 LDR	X18, [X22, X20,LSL #3]

(3328) 0x51df84 LDR	X30, [X16, X20,LSL #3]

(3328) 0x51df88 LDR	D5, [X26, X20,LSL #3]

(3328) 0x51df8c CMP	X18, X30

(3328) 0x51df90 B.GE	51dfd0

(3328) 0x51df94 ADD	X27, X25, X18,LSL #3

(3328) 0x51df98 MOVZ	X2, #0

(3328) 0x51df9c SUB	X1, X30, X18

(3328) 0x51dfa0 ADD	X4, X24, X18,LSL #3

(3328) 0x51dfa4 WHILELO	P5.D, XZR, X1

(3328) 0x51dfa8 DUP	Z15.D, #0

  (3329) 0x51dfac LD1D	{Z31.D}, P5/Z, [X4, X2,LSL #3]

  (3329) 0x51dfb0 LD1D	{Z30.D}, P5/Z, [X27, X2,LSL #3]

  (3329) 0x51dfb4 LD1D	{Z1.D}, P5/Z, [X19, Z31.D,LSL #3]

  (3329) 0x51dfb8 ADD	X2, X2, X17

  (3329) 0x51dfbc FMLA	Z15.D, P5/M, Z1.D, Z30.D

  (3329) 0x51dfc0 WHILELO	P5.D, X2, X1

  (3329) 0x51dfc4 B.NE	51dfac

(3328) 0x51dfc8 FADDV	D3, P4, Z15.D

(3328) 0x51dfcc FADD	D5, D5, D3

(3328) 0x51dfd0 FMUL	D2, D14, D5

(3328) 0x51dfd4 STR	D2, [X23, X20,LSL #3]

(3328) 0x51dfd8 ADD	X20, X20, #1

(3328) 0x51dfdc CMP	X21, X20

(3328) 0x51dfe0 B.NE	51df80

0x51dfe4 B	51d988

0x51dfe8 CMP	X20, X21

0x51dfec B.GE	51d988

0x51dff0 ADD	X13, X22, #8

0x51dff4 CNTD	X14, ALL

0x51dff8 PTRUE	P6.B, ALL

0x51dffc HINT	#0

(3322) 0x51e000 LDR	D1, [X26, X20,LSL #3]

(3322) 0x51e004 LDR	X15, [X22, X20,LSL #3]

(3322) 0x51e008 LDR	X16, [X13, X20,LSL #3]

(3322) 0x51e00c FMUL	D6, D15, D1

(3322) 0x51e010 CMP	X15, X16

(3322) 0x51e014 B.GE	51e054

(3322) 0x51e018 ADD	X17, X25, X15,LSL #3

(3322) 0x51e01c MOVZ	X1, #0

(3322) 0x51e020 SUB	X18, X16, X15

(3322) 0x51e024 ADD	X30, X24, X15,LSL #3

(3322) 0x51e028 WHILELO	P7.D, XZR, X18

(3322) 0x51e02c DUP	Z3.D, #0

  (3323) 0x51e030 LD1D	{Z5.D}, P7/Z, [X30, X1,LSL #3]

  (3323) 0x51e034 LD1D	{Z2.D}, P7/Z, [X17, X1,LSL #3]

  (3323) 0x51e038 LD1D	{Z4.D}, P7/Z, [X19, Z5.D,LSL #3]

  (3323) 0x51e03c ADD	X1, X1, X14

  (3323) 0x51e040 FMLA	Z3.D, P7/M, Z4.D, Z2.D

  (3323) 0x51e044 WHILELO	P7.D, X1, X18

  (3323) 0x51e048 B.NE	51e030

(3322) 0x51e04c FADDV	D0, P6, Z3.D

(3322) 0x51e050 FADD	D6, D6, D0

(3322) 0x51e054 FMUL	D7, D14, D6

(3322) 0x51e058 STR	D7, [X23, X20,LSL #3]

(3322) 0x51e05c ADD	X20, X20, #1

(3322) 0x51e060 CMP	X21, X20

(3322) 0x51e064 B.NE	51e000

0x51e068 B	51d988

(3324) 0x51e06c FNEG	D19, D16

(3324) 0x51e070 B	51dd54

(3330) 0x51e074 FNEG	D17, D4

(3330) 0x51e078 B	51db70

0x51e07c HINT	#0

Coverage (%)	Name	Module
►98.43+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.50 to 12.00 cycles (2.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 25.50 to 24.50 cycles (1.04x speedup).

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

6% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CSRMatrixGetLoadBalancedPartitionBegin: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:246
hypre_CSRMatrixGetLoadBalancedPartitionEnd: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:247
hypre_error_handler: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248
hypre_fprintf: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	207
nb uops	191
loop length	828
used w registers	0
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.88 cycles
front end	23.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	24.50	24.50	25.50	25.50	25.50	25.50	11.00	2.00	2.00	2.00	11.17	10.83	11.00	3.00	3.00
cycles	24.50	24.50	25.50	25.50	25.50	25.50	11.00	2.00	2.00	2.00	11.17	10.83	11.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.88
Dispatch	25.50
Overall L1	25.50

Vectorization ratios

INT

all	2%
load	6%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	6%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	37%
load	31%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	43%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	35%
load	31%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 51d870

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP X21, X25, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X24, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X26, [X1, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D14, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D15, [X1, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X23, [X1, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [X1, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 51c564 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 51c608 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 51dbf4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X27, X20, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 51dbbc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X27, X21, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 51db84 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D15, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 51d9a8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D15, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51dae8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D20, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D14, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 51dc2c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 51dee8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X27, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P2.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D29, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D14, D29	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51da48 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P4.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X30, [X16, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51da40 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
FMOV D18, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D14, D18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51dd68 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P2.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X12, [X10, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51dae0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
FMOV D30, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D15, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51dcd0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 51ddf0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x580>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51df6c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
HINT #0																			N/A
HINT #0																			N/A
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X9, <543b84>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X10, <542b88>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X11, <570b8c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X9, #1096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X10, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X11, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X12, <543ba0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X12, #1128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #250	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51d8e8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, <543bbc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X6, <542bc0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X7, <570bc4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X5, #1216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X6, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X7, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, <543bd8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X8, #1128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #249	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51d8dc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, <542bf4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, <543bf8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <570bfc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X3, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X0, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X4, <543c10>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X4, #1128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51d8d0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X17, [X14, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D27, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51dcc8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x458>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
FCMP D14, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 51de68 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51dfe8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x778>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X2, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X6, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51dde8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P2.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
HINT #0																			N/A
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P4.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
HINT #0																			N/A
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P4.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
HINT #0																			N/A
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

6% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CSRMatrixGetLoadBalancedPartitionBegin: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:246
hypre_CSRMatrixGetLoadBalancedPartitionEnd: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:247
hypre_error_handler: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248
hypre_fprintf: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	207
nb uops	191
loop length	828
used w registers	0
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.88 cycles
front end	23.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	24.50	24.50	25.50	25.50	25.50	25.50	11.00	2.00	2.00	2.00	11.17	10.83	11.00	3.00	3.00
cycles	24.50	24.50	25.50	25.50	25.50	25.50	11.00	2.00	2.00	2.00	11.17	10.83	11.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.88
Dispatch	25.50
Overall L1	25.50

Vectorization ratios

INT

all	2%
load	6%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	6%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	37%
load	31%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	43%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	35%
load	31%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 51d870

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP X21, X25, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X24, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X26, [X1, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D14, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D15, [X1, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X23, [X1, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [X1, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 51c564 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 51c608 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 51dbf4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X27, X20, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 51dbbc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X27, X21, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.LT 51db84 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D15, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 51d9a8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D15, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51dae8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D20, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D14, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 51dc2c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 51dee8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X27, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P2.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D29, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D14, D29	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51da48 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P4.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X30, [X16, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51da40 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
FMOV D18, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D14, D18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51dd68 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P2.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X12, [X10, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51dae0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
FMOV D30, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D15, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51dcd0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 51ddf0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x580>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51df6c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
HINT #0																			N/A
HINT #0																			N/A
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X9, <543b84>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X10, <542b88>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X11, <570b8c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X9, #1096	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X10, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X11, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X12, <543ba0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X12, #1128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #250	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51d8e8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, <543bbc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X6, <542bc0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X7, <570bc4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X5, #1216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X6, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X7, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, <543bd8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X8, #1128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #249	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51d8dc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, <542bf4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, <543bf8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <570bfc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X3, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X0, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X4, <543c10>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X4, #1128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51d8d0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X17, [X14, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D27, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51dcc8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x458>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
FCMP D14, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 51de68 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 51dfe8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x778>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X22, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X2, [X26, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X6, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51dde8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P2.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
HINT #0																			N/A
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P4.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
HINT #0																			N/A
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P4.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
HINT #0																			N/A
B 51d988 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6–	17.84	7.43
▼Loop 3335 - csr_matvec.c:307-314 - exec–	0.11	0.03
○Loop 3336 - csr_matvec.c:310-312 - exec	8.87	2.76
▼Loop 3326 - csr_matvec.c:334-341 - exec–	0.08	0.02
○Loop 3327 - csr_matvec.c:337-339 - exec	0.85	0.26
▼Loop 3324 - csr_matvec.c:385-397 - exec–	0.00	0.00
○Loop 3325 - csr_matvec.c:388-390 - exec	0.00	0.00
▼Loop 3316 - csr_matvec.c:268-275 - exec–	0.00	0.00
▼Loop 3315 - csr_matvec.c:268-275 - exec–	0.00	0.00
○Loop 3314 - csr_matvec.c:271-273 - exec	0.00	0.00
▼Loop 3330 - csr_matvec.c:346-353 - exec–	0.00	0.00
○Loop 3331 - csr_matvec.c:349-351 - exec	0.00	0.00
▼Loop 3322 - csr_matvec.c:397-404 - exec–	0.00	0.00
○Loop 3323 - csr_matvec.c:400-402 - exec	0.00	0.00
▼Loop 3313 - csr_matvec.c:280-287 - exec–	0.00	0.00
▼Loop 3312 - csr_matvec.c:280-287 - exec–	0.00	0.00
○Loop 3311 - csr_matvec.c:283-285 - exec	0.00	0.00
▼Loop 3334 - csr_matvec.c:295-302 - exec–	0.00	0.00
▼Loop 3333 - csr_matvec.c:295-302 - exec–	0.00	0.00
○Loop 3332 - csr_matvec.c:298-300 - exec	0.00	0.00
▼Loop 3320 - csr_matvec.c:373-380 - exec–	0.00	0.00
○Loop 3321 - csr_matvec.c:376-378 - exec	0.00	0.00
▼Loop 3319 - csr_matvec.c:256-263 - exec–	0.00	0.00
▼Loop 3318 - csr_matvec.c:256-263 - exec–	0.09	0.03
○Loop 3317 - csr_matvec.c:259-261 - exec	7.85	2.45
▼Loop 3328 - csr_matvec.c:358-365 - exec–	0.00	0.00
○Loop 3329 - csr_matvec.c:361-363 - exec	0.00	0.00
▼Loop 3337 - csr_matvec.c:319-326 - exec–	0.00	0.00
○Loop 3338 - csr_matvec.c:322-324 - exec	0.00	0.00

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Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code