OV - exec - Function hypre_CSRMatrixMatvecT._omp

	Function: hypre_CSRMatrixMatvecT._omp_fn.3	Module: exec	Source: csr_matvec.c:554-579 [...]	Coverage (incl. loops): 0.88% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 554 - 579

--------------------------------------------------------------------------------

554: #pragma omp parallel private(i,jj,j,my_thread_num,offset)

555: #endif

556:          {

557:             my_thread_num = hypre_GetThreadNum();

558:             offset =  y_size*my_thread_num;

[...]

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

[...]

577:                for (j = 0; j < num_threads; j++)

578:                {

579:                   y_data[i] += y_data_expand[j*y_size + i];

0x51e850 STP	X29, X30, [SP, #912]!

0x51e854 ADD	X29, SP, #0

0x51e858 STP	X19, X20, [SP, #16]

0x51e85c STP	X21, X22, [SP, #32]

0x51e860 STP	X23, X24, [SP, #48]

0x51e864 STP	X25, X26, [SP, #64]

0x51e868 STP	X27, X28, [SP, #80]

0x51e86c LDP	X28, X7, [X0]

0x51e870 LDP	X27, X20, [X0, #16]

0x51e874 LDP	X25, X23, [X0, #32]

0x51e878 LDP	X22, X19, [X0, #48]

0x51e87c STR	X7, [SP, #104]

0x51e880 LDR	X26, [X0, #64]

0x51e884 BL	52c0a0

0x51e888 ORR	X24, XZR, X0

0x51e88c BL	4101b0

0x51e890 SBFM	X21, X0, #0, #31

0x51e894 BL	4101c0

0x51e898 SDIV	X12, X20, X21

0x51e89c SBFM	X0, X0, #0, #31

0x51e8a0 LDR	X14, [SP, #104]

0x51e8a4 MSUB	X2, X12, X21, X20

0x51e8a8 CMP	X0, X2

0x51e8ac B.LT	51ebe0

0x51e8b0 MADD	X2, X12, X0, X2

0x51e8b4 ADD	X15, X12, X2

0x51e8b8 CMP	X2, X15

0x51e8bc B.GE	51ea0c

0x51e8c0 MUL	X16, X22, X24

0x51e8c4 ADD	X13, X14, #8

(3344) 0x51e8c8 LDR	X1, [X14, X2,LSL #3]

(3344) 0x51e8cc LDR	X11, [X13, X2,LSL #3]

(3344) 0x51e8d0 CMP	X1, X11

(3344) 0x51e8d4 B.GE	51ea00

(3344) 0x51e8d8 SUB	X3, X11, X1

(3344) 0x51e8dc ANDS	X4, X3, #0x3

(3344) 0x51e8e0 B.EQ	51e968

(3344) 0x51e8e4 CMP	X4, #1

(3344) 0x51e8e8 B.EQ	51e93c

(3344) 0x51e8ec CMP	X4, #2

(3344) 0x51e8f0 B.EQ	51e918

(3344) 0x51e8f4 LDR	X5, [X27, X1,LSL #3]

(3344) 0x51e8f8 LDR	D31, [X28, X1,LSL #3]

(3344) 0x51e8fc ADD	X1, X1, #1

(3344) 0x51e900 LDR	D30, [X25, X2,LSL #3]

(3344) 0x51e904 ADD	X6, X16, X5

(3344) 0x51e908 UBFM	X8, X6, #61, #60

(3344) 0x51e90c LDR	D29, [X19, X8]

(3344) 0x51e910 FMADD	D0, D31, D30, D29

(3344) 0x51e914 STR	D0, [X19, X8]

(3344) 0x51e918 LDR	X9, [X27, X1,LSL #3]

(3344) 0x51e91c LDR	D28, [X28, X1,LSL #3]

(3344) 0x51e920 ADD	X1, X1, #1

(3344) 0x51e924 LDR	D27, [X25, X2,LSL #3]

(3344) 0x51e928 ADD	X10, X16, X9

(3344) 0x51e92c UBFM	X17, X10, #61, #60

(3344) 0x51e930 LDR	D26, [X19, X17]

(3344) 0x51e934 FMADD	D1, D28, D27, D26

(3344) 0x51e938 STR	D1, [X19, X17]

(3344) 0x51e93c LDR	X18, [X27, X1,LSL #3]

(3344) 0x51e940 LDR	D25, [X28, X1,LSL #3]

(3344) 0x51e944 ADD	X1, X1, #1

(3344) 0x51e948 LDR	D24, [X25, X2,LSL #3]

(3344) 0x51e94c ADD	X30, X16, X18

(3344) 0x51e950 UBFM	X7, X30, #61, #60

(3344) 0x51e954 LDR	D23, [X19, X7]

(3344) 0x51e958 FMADD	D2, D25, D24, D23

(3344) 0x51e95c STR	D2, [X19, X7]

(3344) 0x51e960 CMP	X1, X11

(3344) 0x51e964 B.EQ	51ea00

  (3345) 0x51e968 LDR	X20, [X27, X1,LSL #3]

  (3345) 0x51e96c ADD	X24, X1, #1

  (3345) 0x51e970 ADD	X12, X1, #3

  (3345) 0x51e974 ADD	X8, X1, #2

  (3345) 0x51e978 LDR	D5, [X28, X1,LSL #3]

  (3345) 0x51e97c ADD	X1, X1, #4

  (3345) 0x51e980 LDR	D4, [X25, X2,LSL #3]

  (3345) 0x51e984 ADD	X3, X16, X20

  (3345) 0x51e988 UBFM	X6, X3, #61, #60

  (3345) 0x51e98c LDR	X5, [X27, X24,LSL #3]

  (3345) 0x51e990 LDR	D3, [X19, X6]

  (3345) 0x51e994 LDR	X4, [X27, X8,LSL #3]

  (3345) 0x51e998 ADD	X9, X16, X5

  (3345) 0x51e99c UBFM	X10, X9, #61, #60

  (3345) 0x51e9a0 LDR	X17, [X27, X12,LSL #3]

  (3345) 0x51e9a4 FMADD	D6, D5, D4, D3

  (3345) 0x51e9a8 ADD	X18, X16, X4

  (3345) 0x51e9ac UBFM	X30, X18, #61, #60

  (3345) 0x51e9b0 ADD	X7, X16, X17

  (3345) 0x51e9b4 UBFM	X20, X7, #61, #60

  (3345) 0x51e9b8 STR	D6, [X19, X6]

  (3345) 0x51e9bc LDR	D16, [X28, X24,LSL #3]

  (3345) 0x51e9c0 LDR	D7, [X25, X2,LSL #3]

  (3345) 0x51e9c4 LDR	D17, [X19, X10]

  (3345) 0x51e9c8 FMADD	D18, D16, D7, D17

  (3345) 0x51e9cc STR	D18, [X19, X10]

  (3345) 0x51e9d0 LDR	D19, [X28, X8,LSL #3]

  (3345) 0x51e9d4 LDR	D20, [X25, X2,LSL #3]

  (3345) 0x51e9d8 LDR	D21, [X19, X30]

  (3345) 0x51e9dc FMADD	D22, D19, D20, D21

  (3345) 0x51e9e0 STR	D22, [X19, X30]

  (3345) 0x51e9e4 LDR	D31, [X28, X12,LSL #3]

  (3345) 0x51e9e8 LDR	D30, [X25, X2,LSL #3]

  (3345) 0x51e9ec LDR	D29, [X19, X20]

  (3345) 0x51e9f0 FMADD	D0, D31, D30, D29

  (3345) 0x51e9f4 STR	D0, [X19, X20]

  (3345) 0x51e9f8 CMP	X1, X11

  (3345) 0x51e9fc B.NE	51e968

(3344) 0x51ea00 ADD	X2, X2, #1

(3344) 0x51ea04 CMP	X15, X2

(3344) 0x51ea08 B.NE	51e8c8

0x51ea0c STR	X0, [SP, #104]

0x51ea10 BL	410120

0x51ea14 SDIV	X27, X22, X21

0x51ea18 LDR	X28, [SP, #104]

0x51ea1c MSUB	X25, X27, X21, X22

0x51ea20 CMP	X28, X25

0x51ea24 B.LT	51ebd4

0x51ea28 MADD	X1, X27, X28, X25

0x51ea2c ADD	X21, X27, X1

0x51ea30 CMP	X1, X21

0x51ea34 B.GE	51ebb8

0x51ea38 CMP	X26, #0

0x51ea3c B.LE	51ebb8

0x51ea40 ADD	X19, X19, X1,LSL #3

0x51ea44 UBFM	X22, X22, #61, #60

(3343) 0x51ea48 ANDS	X0, X26, #0x7

(3343) 0x51ea4c LDR	D2, [X23, X1,LSL #3]

(3343) 0x51ea50 ORR	X15, XZR, X19

(3343) 0x51ea54 MOVZ	X14, #0

(3343) 0x51ea58 B.EQ	51eb20

(3343) 0x51ea5c CMP	X0, #1

(3343) 0x51ea60 B.EQ	51eb04

(3343) 0x51ea64 CMP	X0, #2

(3343) 0x51ea68 B.EQ	51eaf0

(3343) 0x51ea6c CMP	X0, #3

(3343) 0x51ea70 B.EQ	51eadc

(3343) 0x51ea74 CMP	X0, #4

(3343) 0x51ea78 B.EQ	51eac8

(3343) 0x51ea7c CMP	X0, #5

(3343) 0x51ea80 B.EQ	51eab4

(3343) 0x51ea84 CMP	X0, #6

(3343) 0x51ea88 B.EQ	51eaa0

(3343) 0x51ea8c LDR	D28, [X19]

(3343) 0x51ea90 MOVZ	X14, #1

(3343) 0x51ea94 ADD	X15, X19, X22

(3343) 0x51ea98 FADD	D2, D2, D28

(3343) 0x51ea9c STR	D2, [X23, X1,LSL #3]

(3343) 0x51eaa0 LDR	D27, [X15]

(3343) 0x51eaa4 ADD	X14, X14, #1

(3343) 0x51eaa8 ADD	X15, X15, X22

(3343) 0x51eaac FADD	D2, D2, D27

(3343) 0x51eab0 STR	D2, [X23, X1,LSL #3]

(3343) 0x51eab4 LDR	D26, [X15]

(3343) 0x51eab8 ADD	X14, X14, #1

(3343) 0x51eabc ADD	X15, X15, X22

(3343) 0x51eac0 FADD	D2, D2, D26

(3343) 0x51eac4 STR	D2, [X23, X1,LSL #3]

(3343) 0x51eac8 LDR	D1, [X15]

(3343) 0x51eacc ADD	X14, X14, #1

(3343) 0x51ead0 ADD	X15, X15, X22

(3343) 0x51ead4 FADD	D2, D2, D1

(3343) 0x51ead8 STR	D2, [X23, X1,LSL #3]

(3343) 0x51eadc LDR	D25, [X15]

(3343) 0x51eae0 ADD	X14, X14, #1

(3343) 0x51eae4 ADD	X15, X15, X22

(3343) 0x51eae8 FADD	D2, D2, D25

(3343) 0x51eaec STR	D2, [X23, X1,LSL #3]

(3343) 0x51eaf0 LDR	D24, [X15]

(3343) 0x51eaf4 ADD	X14, X14, #1

(3343) 0x51eaf8 ADD	X15, X15, X22

(3343) 0x51eafc FADD	D2, D2, D24

(3343) 0x51eb00 STR	D2, [X23, X1,LSL #3]

(3343) 0x51eb04 LDR	D23, [X15]

(3343) 0x51eb08 ADD	X14, X14, #1

(3343) 0x51eb0c ADD	X15, X15, X22

(3343) 0x51eb10 FADD	D2, D2, D23

(3343) 0x51eb14 STR	D2, [X23, X1,LSL #3]

(3343) 0x51eb18 CMP	X26, X14

(3343) 0x51eb1c B.EQ	51eba8

  (3342) 0x51eb20 LDR	D5, [X15]

  (3342) 0x51eb24 ADD	X16, X15, X22

  (3342) 0x51eb28 ADD	X13, X15, X22,LSL #1

  (3342) 0x51eb2c ADD	X14, X14, #8

  (3342) 0x51eb30 ADD	X11, X13, X22

  (3342) 0x51eb34 ADD	X24, X13, X22,LSL #1

  (3342) 0x51eb38 ADD	X12, X24, X22

  (3342) 0x51eb3c ADD	X8, X24, X22,LSL #1

  (3342) 0x51eb40 FADD	D4, D2, D5

  (3342) 0x51eb44 STR	D4, [X23, X1,LSL #3]

  (3342) 0x51eb48 LDR	D3, [X15, X22]

  (3342) 0x51eb4c ADD	X15, X8, X22,LSL #1

  (3342) 0x51eb50 FADD	D6, D4, D3

  (3342) 0x51eb54 STR	D6, [X23, X1,LSL #3]

  (3342) 0x51eb58 LDR	D16, [X16, X22]

  (3342) 0x51eb5c FADD	D7, D6, D16

  (3342) 0x51eb60 STR	D7, [X23, X1,LSL #3]

  (3342) 0x51eb64 LDR	D17, [X13, X22]

  (3342) 0x51eb68 FADD	D18, D7, D17

  (3342) 0x51eb6c STR	D18, [X23, X1,LSL #3]

  (3342) 0x51eb70 LDR	D19, [X11, X22]

  (3342) 0x51eb74 FADD	D20, D18, D19

  (3342) 0x51eb78 STR	D20, [X23, X1,LSL #3]

  (3342) 0x51eb7c LDR	D21, [X24, X22]

  (3342) 0x51eb80 FADD	D22, D20, D21

  (3342) 0x51eb84 STR	D22, [X23, X1,LSL #3]

  (3342) 0x51eb88 LDR	D31, [X12, X22]

  (3342) 0x51eb8c FADD	D30, D22, D31

  (3342) 0x51eb90 STR	D30, [X23, X1,LSL #3]

  (3342) 0x51eb94 LDR	D29, [X8, X22]

  (3342) 0x51eb98 FADD	D2, D30, D29

  (3342) 0x51eb9c STR	D2, [X23, X1,LSL #3]

  (3342) 0x51eba0 CMP	X26, X14

  (3342) 0x51eba4 B.NE	51eb20

(3343) 0x51eba8 ADD	X1, X1, #1

(3343) 0x51ebac ADD	X19, X19, #8

(3343) 0x51ebb0 CMP	X21, X1

(3343) 0x51ebb4 B.NE	51ea48

0x51ebb8 LDP	X19, X20, [SP, #16]

0x51ebbc LDP	X21, X22, [SP, #32]

0x51ebc0 LDP	X23, X24, [SP, #48]

0x51ebc4 LDP	X25, X26, [SP, #64]

0x51ebc8 LDP	X27, X28, [SP, #80]

0x51ebcc LDP	X29, X30, [SP], #112

0x51ebd0 B	410120

0x51ebd4 ADD	X27, X27, #1

0x51ebd8 MOVZ	X25, #0

0x51ebdc B	51ea28

0x51ebe0 ADD	X12, X12, #1

0x51ebe4 MOVZ	X2, #0

0x51ebe8 B	51e8b0

Coverage (%)	Name	Source Location	Module
►98.37+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMatvecT	csr_matvec.c:554	exec
○	hypre_ParCSRMatrixMatvecT	par_csr_matvec.c:439	exec
○	hypre_BoomerAMGCycle	par_cycle.c:435	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 36% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 40.00 to 30.00 cycles (1.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 7.00 cycles (5.71x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557
unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	58
nb uops	58
loop length	232
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.25 cycles
front end	7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00
cycles	6.00	6.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	7.25
Dispatch	7.50
DIV/SQRT	10.00-40.00
Overall L1	10.00-40.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	36%
load	44%
store	43%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 51e850

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X7, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X20, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X23, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X7, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 52c0a0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X21, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X12, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X0, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X2, X12, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 51ebe0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X2, X12, X0, X2	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X15, X12, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51ea0c <hypre_CSRMatrixMatvecT._omp_fn.3+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X16, X22, X24	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X13, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X0, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X27, X22, X21	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X28, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X25, X27, X21, X22	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X28, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 51ebd4 <hypre_CSRMatrixMatvecT._omp_fn.3+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X27, X28, X25	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X21, X27, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51ebb8 <hypre_CSRMatrixMatvecT._omp_fn.3+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 51ebb8 <hypre_CSRMatrixMatvecT._omp_fn.3+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X19, X19, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X22, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 410120 <@plt_start@+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B 51ea28 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B 51e8b0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 7.00 cycles (5.71x speedup).

CALL instructions

Detected function call instructions.

Details

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557
unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	58
nb uops	58
loop length	232
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.25 cycles
front end	7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00
cycles	6.00	6.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	7.25
Dispatch	7.50
DIV/SQRT	10.00-40.00
Overall L1	10.00-40.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	36%
load	44%
store	43%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 51e850

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X7, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X20, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X23, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X7, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 52c0a0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X21, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X12, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X0, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X2, X12, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 51ebe0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X2, X12, X0, X2	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X15, X12, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51ea0c <hypre_CSRMatrixMatvecT._omp_fn.3+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X16, X22, X24	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X13, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X0, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X27, X22, X21	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X28, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB X25, X27, X21, X22	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X28, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 51ebd4 <hypre_CSRMatrixMatvecT._omp_fn.3+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X27, X28, X25	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X21, X27, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51ebb8 <hypre_CSRMatrixMatvecT._omp_fn.3+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 51ebb8 <hypre_CSRMatrixMatvecT._omp_fn.3+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X19, X19, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X22, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 410120 <@plt_start@+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B 51ea28 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B 51e8b0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecT._omp_fn.3–	0.88	0.37
▼Loop 3344 - csr_matvec.c:564-567 - exec–	0.63	0.20
○Loop 3345 - csr_matvec.c:564-567 - exec	0.13	0.04
▼Loop 3343 - csr_matvec.c:577-579 - exec–	0.00	0.00
○Loop 3342 - csr_matvec.c:577-579 - exec	0.12	0.04

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code