OV - exec - Function hypre_SeqVectorScale._omp

	Function: hypre_SeqVectorScale._omp_fn.0	Module: exec	Source: vector.c:413-416	Coverage (incl. loops): 0.26% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 413 - 416

--------------------------------------------------------------------------------

413: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

414: #endif

415:    for (i = 0; i < size; i++)

416:       y_data[i] *= alpha;

0x5219a4 STP	X29, X30, [SP, #976]!

0x5219a8 ADD	X29, SP, #0

0x5219ac STP	X19, X20, [SP, #16]

0x5219b0 ORR	X20, XZR, X0

0x5219b4 STR	X21, [SP, #32]

0x5219b8 LDR	X21, [X0, #16]

0x5219bc BL	4101b0

0x5219c0 SBFM	X19, X0, #0, #31

0x5219c4 BL	4101c0

0x5219c8 SBFM	X2, X0, #0, #31

0x5219cc SDIV	X3, X21, X19

0x5219d0 MSUB	X1, X3, X19, X21

0x5219d4 CMP	X2, X1

0x5219d8 B.LT	521bd0

0x5219dc MADD	X7, X3, X2, X1

0x5219e0 ADD	X0, X3, X7

0x5219e4 CMP	X7, X0

0x5219e8 B.GE	521bc0

0x5219ec LDR	X5, [X20, #8]

0x5219f0 SUB	X4, X3, #1

0x5219f4 STR	D15, [SP, #40]

0x5219f8 LDR	D15, [X20]

0x5219fc CMP	X4, #2

0x521a00 B.LS	521bfc

0x521a04 UBFM	X8, X3, #2, #63

0x521a08 ADD	X15, X5, X7,LSL #3

0x521a0c DUP	V31.2D, V15.D[0]

0x521a10 UBFM	X9, X8, #59, #58

0x521a14 SUB	X10, X9, #32

0x521a18 ADD	X11, X15, X8,LSL #5

0x521a1c UBFM	X12, X10, #5, #63

0x521a20 ADD	X13, X12, #1

0x521a24 ANDS	X14, X13, #0x7

0x521a28 B.EQ	521af0

0x521a2c CMP	X14, #1

0x521a30 B.EQ	521ad4

0x521a34 CMP	X14, #2

0x521a38 B.EQ	521ac0

0x521a3c CMP	X14, #3

0x521a40 B.EQ	521aac

0x521a44 CMP	X14, #4

0x521a48 B.EQ	521a98

0x521a4c CMP	X14, #5

0x521a50 B.EQ	521a84

0x521a54 CMP	X14, #6

0x521a58 B.EQ	521a70

0x521a5c LDP	Q3, Q4, [X15]

0x521a60 ADD	X15, X15, #32

0x521a64 FMUL	V0.2D, V3.2D, V31.2D

0x521a68 FMUL	V1.2D, V4.2D, V31.2D

0x521a6c STP	Q0, Q1, [X15, #2016]

0x521a70 LDP	Q5, Q2, [X15]

0x521a74 ADD	X15, X15, #32

0x521a78 FMUL	V6.2D, V5.2D, V31.2D

0x521a7c FMUL	V7.2D, V2.2D, V31.2D

0x521a80 STP	Q6, Q7, [X15, #2016]

0x521a84 LDP	Q29, Q16, [X15]

0x521a88 ADD	X15, X15, #32

0x521a8c FMUL	V17.2D, V29.2D, V31.2D

0x521a90 FMUL	V18.2D, V16.2D, V31.2D

0x521a94 STP	Q17, Q18, [X15, #2016]

0x521a98 LDP	Q28, Q30, [X15]

0x521a9c ADD	X15, X15, #32

0x521aa0 FMUL	V19.2D, V28.2D, V31.2D

0x521aa4 FMUL	V20.2D, V30.2D, V31.2D

0x521aa8 STP	Q19, Q20, [X15, #2016]

0x521aac LDP	Q26, Q27, [X15]

0x521ab0 ADD	X15, X15, #32

0x521ab4 FMUL	V21.2D, V26.2D, V31.2D

0x521ab8 FMUL	V22.2D, V27.2D, V31.2D

0x521abc STP	Q21, Q22, [X15, #2016]

0x521ac0 LDP	Q24, Q25, [X15]

0x521ac4 ADD	X15, X15, #32

0x521ac8 FMUL	V23.2D, V24.2D, V31.2D

0x521acc FMUL	V3.2D, V25.2D, V31.2D

0x521ad0 STP	Q23, Q3, [X15, #2016]

0x521ad4 LDP	Q4, Q0, [X15]

0x521ad8 ADD	X15, X15, #32

0x521adc FMUL	V1.2D, V4.2D, V31.2D

0x521ae0 FMUL	V5.2D, V0.2D, V31.2D

0x521ae4 STP	Q1, Q5, [X15, #2016]

0x521ae8 CMP	X15, X11

0x521aec B.EQ	521b84

(3380) 0x521af0 LDP	Q28, Q26, [X15]

(3380) 0x521af4 ORR	X16, XZR, X15

(3380) 0x521af8 LDP	Q18, Q19, [X15, #32]

(3380) 0x521afc LDP	Q16, Q17, [X15, #64]

(3380) 0x521b00 LDP	Q6, Q7, [X15, #96]

(3380) 0x521b04 LDP	Q27, Q22, [X15, #128]

(3380) 0x521b08 FMUL	V20.2D, V28.2D, V31.2D

(3380) 0x521b0c LDP	Q2, Q24, [X15, #160]

(3380) 0x521b10 FMUL	V21.2D, V26.2D, V31.2D

(3380) 0x521b14 LDP	Q25, Q23, [X15, #192]

(3380) 0x521b18 FMUL	V28.2D, V18.2D, V31.2D

(3380) 0x521b1c LDP	Q29, Q30, [X15, #224]

(3380) 0x521b20 ADD	X15, X15, #256

(3380) 0x521b24 FMUL	V26.2D, V19.2D, V31.2D

(3380) 0x521b28 FMUL	V18.2D, V16.2D, V31.2D

(3380) 0x521b2c FMUL	V19.2D, V17.2D, V31.2D

(3380) 0x521b30 FMUL	V16.2D, V6.2D, V31.2D

(3380) 0x521b34 FMUL	V17.2D, V7.2D, V31.2D

(3380) 0x521b38 FMUL	V4.2D, V27.2D, V31.2D

(3380) 0x521b3c FMUL	V5.2D, V22.2D, V31.2D

(3380) 0x521b40 FMUL	V6.2D, V2.2D, V31.2D

(3380) 0x521b44 FMUL	V3.2D, V24.2D, V31.2D

(3380) 0x521b48 FMUL	V0.2D, V25.2D, V31.2D

(3380) 0x521b4c FMUL	V1.2D, V23.2D, V31.2D

(3380) 0x521b50 FMUL	V7.2D, V29.2D, V31.2D

(3380) 0x521b54 FMUL	V27.2D, V30.2D, V31.2D

(3380) 0x521b58 STP	Q20, Q21, [X15, #1792]

(3380) 0x521b5c STP	Q28, Q26, [X15, #1824]

(3380) 0x521b60 STP	Q18, Q19, [X15, #1856]

(3380) 0x521b64 STP	Q16, Q17, [X15, #1888]

(3380) 0x521b68 STP	Q4, Q5, [X15, #1920]

(3380) 0x521b6c STP	Q6, Q3, [X15, #1952]

(3380) 0x521b70 STP	Q0, Q1, [X15, #1984]

(3380) 0x521b74 STUR	Q7, [X15, #480]

(3380) 0x521b78 STR	Q27, [X16, #240]

(3380) 0x521b7c CMP	X15, X11

(3380) 0x521b80 B.NE	521af0

0x521b84 AND	X6, X3, #0x0

0x521b88 CMP	X3, X6

0x521b8c B.EQ	521bbc

0x521b90 ADD	X17, X7, X6

0x521b94 SUB	X18, X3, X6

0x521b98 DUP	Z15.D, Z15.D[0]

0x521b9c WHILELO	P7.D, XZR, X18

0x521ba0 ADD	X30, X5, X17,LSL #3

0x521ba4 LD1D	{Z31.D}, P7/Z, [X5, X17,LSL #3]

0x521ba8 FMUL	Z22.D, Z31.D, Z15.D

0x521bac ST1D	{Z22.D}, P7, [X30, MUL VL]

0x521bb0 CNTD	X20, ALL

0x521bb4 WHILELO	P0.D, X20, X18

0x521bb8 B.NE	521bdc

0x521bbc LDR	D15, [SP, #40]

0x521bc0 LDP	X19, X20, [SP, #16]

0x521bc4 LDR	X21, [SP, #32]

0x521bc8 LDP	X29, X30, [SP], #48

0x521bcc RET

0x521bd0 ADD	X3, X3, #1

0x521bd4 MOVZ	X1, #0

0x521bd8 B	5219dc

0x521bdc LDR	X21, [SP, #32]

0x521be0 LD1D	{Z2.D}, P0/Z, [X30, #1, MUL VL]

0x521be4 FMUL	Z24.D, Z2.D, Z15.D

0x521be8 ST1D	{Z24.D}, P0, [X30, #1, MUL VL]

0x521bec LDP	X19, X20, [SP, #16]

0x521bf0 LDR	D15, [SP, #40]

0x521bf4 LDP	X29, X30, [SP], #48

0x521bf8 RET

0x521bfc MOVZ	X6, #0

0x521c00 B	521b90

Coverage (%)	Name	Source Location	Module
►98.45+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.55+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_SeqVectorScale	vector.c:413	exec
○	hypre_PCGSolve	pcg.c:709	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	vector.c:413-416
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413-416.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is poorly vectorized. Only 54% of vector register length is used (average across all VPU instructions).

Details

48% of VPU instructions are used in vector version (process two or more data elements in vector registers):

60% of VPU loads are used in vector version.
69% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
9% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 14.25 cycles (1.40x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413

Matching between your function (in the source code) and the binary function

The binary function is composed of 36 FP arithmetical operations:

36: multiply

The binary function is loading 64 bytes. The binary function is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	115
loop length	460
used w registers	0
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	23
used v registers	25
used z registers	5
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.38 cycles
front end	14.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.50	9.50	12.00	12.00	12.00	12.00	7.00	7.00	7.00	7.00	11.17	10.83	11.00	1.50	1.50
cycles	9.50	9.50	12.00	12.00	12.00	12.00	7.00	7.00	7.00	7.00	11.17	10.83	11.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	14.38
Dispatch	12.00
DIV/SQRT	5.00-20.00
Overall L1	14.38-20.00

Vectorization ratios

INT

all	34%
load	60%
store	69%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	9%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	48%
load	60%
store	69%
mul	100%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

INT

all	53%
load	70%
store	80%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
other	36%

all	56%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	56%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	54%
load	70%
store	80%
mul	56%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	36%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 5219a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X2, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X1, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 521bd0 <hypre_SeqVectorScale._omp_fn.0+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X7, X3, X2, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X0, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 521bc0 <hypre_SeqVectorScale._omp_fn.0+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X4, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR D15, [SP, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D15, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 521bfc <hypre_SeqVectorScale._omp_fn.0+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X8, X3, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X15, X5, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V31.2D, V15.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X9, X8, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, X9, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X15, X8,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X12, X10, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X14, X13, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521af0 <hypre_SeqVectorScale._omp_fn.0+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521ad4 <hypre_SeqVectorScale._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521ac0 <hypre_SeqVectorScale._omp_fn.0+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521aac <hypre_SeqVectorScale._omp_fn.0+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521a98 <hypre_SeqVectorScale._omp_fn.0+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521a84 <hypre_SeqVectorScale._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521a70 <hypre_SeqVectorScale._omp_fn.0+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q3, Q4, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V0.2D, V3.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V1.2D, V4.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q0, Q1, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q5, Q2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V6.2D, V5.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V7.2D, V2.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q6, Q7, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q29, Q16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V17.2D, V29.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V18.2D, V16.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q17, Q18, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q28, Q30, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V19.2D, V28.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V20.2D, V30.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q19, Q20, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q26, Q27, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V21.2D, V26.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V22.2D, V27.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q21, Q22, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q24, Q25, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V23.2D, V24.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V3.2D, V25.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q23, Q3, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q4, Q0, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V1.2D, V4.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V5.2D, V0.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q1, Q5, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X15, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521b84 <hypre_SeqVectorScale._omp_fn.0+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X6, X3, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521bbc <hypre_SeqVectorScale._omp_fn.0+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X7, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X18, X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z15.D, Z15.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P7.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X30, X5, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z31.D}, P7/Z, [X5, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FMUL Z22.D, Z31.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z22.D}, P7, [X30, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X20, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P0.D, X20, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B.NE 521bdc <hypre_SeqVectorScale._omp_fn.0+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 5219dc <hypre_SeqVectorScale._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LD1D {Z2.D}, P0/Z, [X30, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FMUL Z24.D, Z2.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z24.D}, P0, [X30, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 521b90 <hypre_SeqVectorScale._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	vector.c:413-416
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413-416.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is poorly vectorized. Only 54% of vector register length is used (average across all VPU instructions).

Details

48% of VPU instructions are used in vector version (process two or more data elements in vector registers):

60% of VPU loads are used in vector version.
69% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
9% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 14.25 cycles (1.40x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413

Matching between your function (in the source code) and the binary function

The binary function is composed of 36 FP arithmetical operations:

36: multiply

The binary function is loading 64 bytes. The binary function is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	115
loop length	460
used w registers	0
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	23
used v registers	25
used z registers	5
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.38 cycles
front end	14.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.50	9.50	12.00	12.00	12.00	12.00	7.00	7.00	7.00	7.00	11.17	10.83	11.00	1.50	1.50
cycles	9.50	9.50	12.00	12.00	12.00	12.00	7.00	7.00	7.00	7.00	11.17	10.83	11.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	14.38
Dispatch	12.00
DIV/SQRT	5.00-20.00
Overall L1	14.38-20.00

Vectorization ratios

INT

all	34%
load	60%
store	69%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	9%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	48%
load	60%
store	69%
mul	100%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

INT

all	53%
load	70%
store	80%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
other	36%

all	56%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	56%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	54%
load	70%
store	80%
mul	56%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	36%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 5219a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X2, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X1, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 521bd0 <hypre_SeqVectorScale._omp_fn.0+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X7, X3, X2, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X0, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 521bc0 <hypre_SeqVectorScale._omp_fn.0+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X4, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR D15, [SP, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D15, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 521bfc <hypre_SeqVectorScale._omp_fn.0+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X8, X3, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X15, X5, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V31.2D, V15.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X9, X8, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, X9, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X15, X8,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X12, X10, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X14, X13, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521af0 <hypre_SeqVectorScale._omp_fn.0+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521ad4 <hypre_SeqVectorScale._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521ac0 <hypre_SeqVectorScale._omp_fn.0+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521aac <hypre_SeqVectorScale._omp_fn.0+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521a98 <hypre_SeqVectorScale._omp_fn.0+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521a84 <hypre_SeqVectorScale._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521a70 <hypre_SeqVectorScale._omp_fn.0+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q3, Q4, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V0.2D, V3.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V1.2D, V4.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q0, Q1, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q5, Q2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V6.2D, V5.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V7.2D, V2.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q6, Q7, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q29, Q16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V17.2D, V29.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V18.2D, V16.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q17, Q18, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q28, Q30, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V19.2D, V28.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V20.2D, V30.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q19, Q20, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q26, Q27, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V21.2D, V26.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V22.2D, V27.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q21, Q22, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q24, Q25, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V23.2D, V24.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V3.2D, V25.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q23, Q3, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q4, Q0, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X15, X15, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V1.2D, V4.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V5.2D, V0.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q1, Q5, [X15, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X15, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521b84 <hypre_SeqVectorScale._omp_fn.0+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X6, X3, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 521bbc <hypre_SeqVectorScale._omp_fn.0+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X7, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X18, X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z15.D, Z15.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P7.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X30, X5, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z31.D}, P7/Z, [X5, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FMUL Z22.D, Z31.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z22.D}, P7, [X30, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X20, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P0.D, X20, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B.NE 521bdc <hypre_SeqVectorScale._omp_fn.0+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 5219dc <hypre_SeqVectorScale._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LD1D {Z2.D}, P0/Z, [X30, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FMUL Z24.D, Z2.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z24.D}, P0, [X30, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 521b90 <hypre_SeqVectorScale._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorScale._omp_fn.0–	0.26	0.11
○Loop 3380 - vector.c:416-416 - exec	0.26	0.08

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CALL instructions

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Matching between your function (in the source code) and the binary function

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Cycles summary

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Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code