OV - exec - Loop 110

	Loop Id: 110	Module: exec	Source: par_coarsen.c:2354-2381	Coverage: 0.05%

0x426fd0 ADD	X3, X3, #8

0x426fd4 CMP	X16, X3

0x426fd8 B.EQ	4270b4

0x426fdc LDR	X12, [X3]

0x426fe0 UBFM	X17, X12, #61, #60

0x426fe4 LDR	D30, [X2, X17]

0x426fe8 FCMPE	D30, D31

0x426fec B.LS	426fd0

0x426ff0 ADD	X18, X17, #8

0x426ff4 LDR	X20, [X14, X17]

0x426ff8 ADD	X30, X14, X18

0x426ffc LDR	X21, [X14, X18]

0x427000 CMP	X20, X21

0x427004 B.LT	427024

0x427008 B	427054

  (112) 0x42700c B.GE	427018

  (112) 0x427010 STR	XZR, [X11, X17]

  (112) 0x427014 LDR	X21, [X30]

  (112) 0x427018 ADD	X20, X20, #1

  (112) 0x42701c CMP	X20, X21

  (112) 0x427020 B.GE	427054

  (112) 0x427024 LDR	X19, [X9, X20,LSL #3]

  (112) 0x427028 UBFM	X0, X19, #61, #60

  (112) 0x42702c LDR	D0, [X2, X0]

  (112) 0x427030 FCMPE	D0, D31

  (112) 0x427034 B.LS	427018

  (112) 0x427038 FCMPE	D30, D0

  (112) 0x42703c B.LS	42700c

  (112) 0x427040 STR	XZR, [X11, X0]

  (112) 0x427044 ADD	X20, X20, #1

  (112) 0x427048 LDR	X21, [X30]

  (112) 0x42704c CMP	X20, X21

  (112) 0x427050 B.LT	427024

0x427054 LDR	X6, [X13, X17]

0x427058 ADD	X10, X13, X18

0x42705c LDR	X5, [X13, X18]

0x427060 CMP	X6, X5

0x427064 B.LT	42708c

0x427068 B	426fd0

  (111) 0x42706c B.GE	427080

  (111) 0x427070 STR	XZR, [X11, X17]

  (111) 0x427074 LDR	X5, [X10]

  (111) 0x427078 HINT	#0

  (111) 0x42707c HINT	#0

  (111) 0x427080 ADD	X6, X6, #1

  (111) 0x427084 CMP	X6, X5

  (111) 0x427088 B.GE	426fd0

  (111) 0x42708c LDR	X1, [X8, X6,LSL #3]

  (111) 0x427090 ADD	X4, X7, X1

  (111) 0x427094 LDR	D29, [X2, X4,LSL #3]

  (111) 0x427098 FCMPE	D29, D31

  (111) 0x42709c B.LS	427080

  (111) 0x4270a0 FCMPE	D30, D29

  (111) 0x4270a4 B.LS	42706c

  (111) 0x4270a8 STR	XZR, [X15, X1,LSL #3]

  (111) 0x4270ac LDR	X5, [X10]

  (111) 0x4270b0 B	427080

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2354 - 2381

--------------------------------------------------------------------------------

2354: #pragma omp parallel for private(ig, i, jS, j, jj) HYPRE_SMP_SCHEDULE

2355: #endif

2356:         for (ig = 0; ig < graph_size; ig++)

2357:         {

2358:            i = graph_array[ig];

2359:            if (measure_array[i] > 1)

2360:            {

2361:               for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2362:               {

2363:                  j = S_diag_j[jS];

2364:                  if (measure_array[j] > 1)

2365:                  {

2366:                     if (measure_array[i] > measure_array[j])

2367:                        CF_marker[j] = 0;

2368:                     else if (measure_array[j] > measure_array[i])

2369:                        CF_marker[i] = 0;

2370:                  }

2371:               } /* for each local neighbor j of i */

2372:               for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2373:               {

2374:                  jj = S_offd_j[jS];

2375:                  j = num_variables+jj;

2376:                  if (measure_array[j] > 1)

2377:                  {

2378:                     if (measure_array[i] > measure_array[j])

2379:                        CF_marker_offd[jj] = 0;

2380:                     else if (measure_array[j] > measure_array[i])

2381:                        CF_marker[i] = 0;

Coverage (%)	Name	Module
►99.06+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.6
Source	par_coarsen.c:2354-2354,par_coarsen.c:2359-2361,par_coarsen.c:2372-2372
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.75
Front-end cycles	2.63
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.6
Source	par_coarsen.c:2354-2354,par_coarsen.c:2359-2361,par_coarsen.c:2372-2372
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.75
Front-end cycles	2.63
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.6
Source file and lines	par_coarsen.c:2354-2381
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354,2359-2361,2372.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=26
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 26 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	21
nb uops	21
loop length	84
used w registers	0
used x registers	14
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.63 cycles
front end	2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	2.00	2.00	2.00	2.00	1.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	3.00	3.00	2.00	2.00	2.00	2.00	1.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.63
Dispatch	3.00
Overall L1	3.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 426fdc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	Latency	Recip. throughput	Vectorization
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP X16, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4270b4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
UBFM X17, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LDR D30, [X2, X17]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCMPE D30, D31	1	0	0	0	0	0	0	1	0	0	0	2	1	scal (25.0%)
B.LS 426fd0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LDR X20, [X14, X17]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X30, X14, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
LDR X21, [X14, X18]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (25.0%)
B.LT 427024 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427054 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X13, X17]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X10, X13, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
LDR X5, [X13, X18]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
B.LT 42708c <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
B 426fd0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.6
Source file and lines	par_coarsen.c:2354-2381
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=26
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	21
nb uops	21
loop length	84
used w registers	0
used x registers	14
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.63 cycles
front end	2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	2.00	2.00	2.00	2.00	1.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	3.00	3.00	2.00	2.00	2.00	2.00	1.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.63
Dispatch	3.00
Overall L1	3.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 426fdc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	Latency	Recip. throughput	Vectorization
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP X16, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4270b4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
UBFM X17, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LDR D30, [X2, X17]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCMPE D30, D31	1	0	0	0	0	0	0	1	0	0	0	2	1	scal (25.0%)
B.LS 426fd0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LDR X20, [X14, X17]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X30, X14, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
LDR X21, [X14, X18]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (25.0%)
B.LT 427024 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427054 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X13, X17]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X10, X13, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
LDR X5, [X13, X18]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
B.LT 42708c <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
B 426fd0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code