OV - exec - Loop 114

	Loop Id: 114	Module: exec	Source: par_coarsen.c:2332-2334	Coverage: 0.06%

0x4274b8 LDR	X12, [X0]    [4]

0x4274bc UBFM	X13, X12, #61, #60

0x4274c0 LDR	D6, [X9, X13]    [2]

0x4274c4 FCMPE	D6, D31

0x4274c8 B.LS	4274d0

0x4274cc STR	X5, [X4, X13]    [1]

0x4274d0 LDR	X14, [X0, #8]    [4]

0x4274d4 ADD	X0, X0, #8

0x4274d8 UBFM	X15, X14, #61, #60

0x4274dc LDR	D5, [X9, X15]    [2]

0x4274e0 FCMPE	D5, D31

0x4274e4 B.LS	4274ec

0x4274e8 STR	X5, [X4, X15]    [1]

0x4274ec LDR	X16, [X0, #8]    [3]

0x4274f0 UBFM	X17, X16, #61, #60

0x4274f4 LDR	D4, [X9, X17]    [2]

0x4274f8 FCMPE	D4, D31

0x4274fc B.LS	427504

0x427500 STR	X5, [X4, X17]    [1]

0x427504 LDR	X18, [X0, #16]    [3]

0x427508 UBFM	X30, X18, #61, #60

0x42750c LDR	D3, [X9, X30]    [2]

0x427510 FCMPE	D3, D31

0x427514 B.LS	42751c

0x427518 STR	X5, [X4, X30]    [1]

0x42751c LDR	X20, [X0, #24]    [3]

0x427520 UBFM	X21, X20, #61, #60

0x427524 LDR	D2, [X9, X21]    [2]

0x427528 FCMPE	D2, D31

0x42752c B.LS	427534

0x427530 STR	X5, [X4, X21]    [1]

0x427534 LDR	X19, [X0, #32]    [3]

0x427538 UBFM	X1, X19, #61, #60

0x42753c LDR	D1, [X9, X1]    [2]

0x427540 FCMPE	D1, D31

0x427544 B.LS	42754c

0x427548 STR	X5, [X4, X1]    [1]

0x42754c LDR	X3, [X0, #40]    [3]

0x427550 UBFM	X2, X3, #61, #60

0x427554 LDR	D0, [X9, X2]    [2]

0x427558 FCMPE	D0, D31

0x42755c B.LS	427564

0x427560 STR	X5, [X4, X2]    [1]

0x427564 LDR	X7, [X0, #48]    [3]

0x427568 UBFM	X8, X7, #61, #60

0x42756c LDR	D30, [X9, X8]    [2]

0x427570 FCMPE	D30, D31

0x427574 B.LS	42757c

0x427578 STR	X5, [X4, X8]    [1]

0x42757c ADD	X0, X0, #56

0x427580 CMP	X10, X0

0x427584 B.NE	4274b8

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2332 - 2334

--------------------------------------------------------------------------------

2332:            if (measure_array[i] > 1)

2333:            {

2334:               CF_marker[i] = 1;

Coverage (%)	Name	Source Location	Module
►98.64+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.36+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2338	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P6, P10, P11, P12,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.4
Source	par_coarsen.c:2332-2334
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.00
Front-end cycles	6.50
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	8.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	52.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P6, P10, P11, P12,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.4
Source	par_coarsen.c:2332-2334
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.00
Front-end cycles	6.50
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	8.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	52.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.4
Source file and lines	par_coarsen.c:2332-2334
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332-2334.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 256 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.00 to 2.67 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	52
nb uops	52
loop length	208
used w registers	0
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	9
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	2.75	2.75	2.75	2.75	8.00	0.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00
cycles	4.50	4.50	2.75	2.75	2.75	2.75	8.00	0.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Dispatch	8.00
Overall L1	8.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4274b8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X12, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X13, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X9, X13]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D6, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 4274d0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X13]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X9, X15]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D5, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 4274ec <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X15]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X17, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X9, X17]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D4, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 427504 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X17]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [X0, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X30, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X9, X30]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D3, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 42751c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X30]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X0, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X21, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X9, X21]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D2, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 427534 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X21]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X0, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X1, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D1, [X9, X1]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D1, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 42754c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X1]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X0, #40]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X2, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X9, X2]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D0, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 427564 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X2]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [X0, #48]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X8, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X9, X8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D30, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 42757c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x23c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X8]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
B.NE 4274b8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.4
Source file and lines	par_coarsen.c:2332-2334
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.00 to 2.67 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	52
nb uops	52
loop length	208
used w registers	0
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	9
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	2.75	2.75	2.75	2.75	8.00	0.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00
cycles	4.50	4.50	2.75	2.75	2.75	2.75	8.00	0.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Dispatch	8.00
Overall L1	8.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4274b8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X12, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X13, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X9, X13]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D6, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 4274d0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X13]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X9, X15]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D5, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 4274ec <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X15]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X17, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X9, X17]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D4, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 427504 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X17]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [X0, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X30, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X9, X30]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D3, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 42751c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X30]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X0, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X21, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X9, X21]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D2, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 427534 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X21]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X0, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X1, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D1, [X9, X1]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D1, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 42754c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X1]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X0, #40]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X2, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X9, X2]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D0, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 427564 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X2]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [X0, #48]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X8, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X9, X8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D30, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
B.LS 42757c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x23c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [X4, X8]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
B.NE 4274b8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code