OV - exec - Loop 2299

	Loop Id: 2299	Module: exec	Source: ams.c:3662-3682 [...]	Coverage: 0.98%

0x4c95c8 ADD	X1, X1, #1

0x4c95cc CMP	X30, X1

0x4c95d0 B.EQ	4c96a8

0x4c95d4 LDR	X5, [X11, X1,LSL #3]

0x4c95d8 UBFM	X3, X5, #61, #60

0x4c95dc ADD	X6, X10, X5,LSL #3

0x4c95e0 LDR	D6, [X10, X3]

0x4c95e4 FCMP	D31, D6

0x4c95e8 B.EQ	4c95c8

0x4c95ec LDR	X2, [X17, X1,LSL #3]

0x4c95f0 LDR	D0, [X14, X1,LSL #3]

0x4c95f4 CMP	X5, X2

0x4c95f8 B.GE	4c9634

0x4c95fc MOVZ	X0, #0

0x4c9600 ADD	X19, X21, X3

0x4c9604 DUP	Z2.D, #0

0x4c9608 SUB	X7, X2, X5

0x4c960c WHILELO	P7.D, XZR, X7

  (2301) 0x4c9610 LD1D	{Z5.D}, P7/Z, [X19, X0,LSL #3]

  (2301) 0x4c9614 LD1D	{Z4.D}, P7/Z, [X6, X0,LSL #3]

  (2301) 0x4c9618 LD1D	{Z3.D}, P7/Z, [X9, Z5.D,LSL #3]

  (2301) 0x4c961c ADD	X0, X0, X4

  (2301) 0x4c9620 FMLS	Z2.D, P7/M, Z3.D, Z4.D

  (2301) 0x4c9624 WHILELO	P7.D, X0, X7

  (2301) 0x4c9628 B.NE	4c9610

0x4c962c FADDV	D1, P6, Z2.D

0x4c9630 FADD	D0, D0, D1

0x4c9634 LDR	X3, [X13, X1,LSL #3]

0x4c9638 LDR	X6, [X16, X1,LSL #3]

0x4c963c CMP	X3, X6

0x4c9640 B.GE	4c9684

0x4c9644 ADD	X5, X18, X3,LSL #3

0x4c9648 MOVZ	X7, #0

0x4c964c SUB	X2, X6, X3

0x4c9650 ADD	X19, X20, X3,LSL #3

0x4c9654 WHILELO	P0.D, XZR, X2

0x4c9658 DUP	Z7.D, #0

0x4c965c HINT	#0

  (2300) 0x4c9660 LD1D	{Z25.D}, P0/Z, [X5, X7,LSL #3]

  (2300) 0x4c9664 LD1D	{Z29.D}, P0/Z, [X19, X7,LSL #3]

  (2300) 0x4c9668 LD1D	{Z27.D}, P0/Z, [X8, Z25.D,LSL #3]

  (2300) 0x4c966c ADD	X7, X7, X4

  (2300) 0x4c9670 FMLS	Z7.D, P0/M, Z27.D, Z29.D

  (2300) 0x4c9674 WHILELO	P0.D, X7, X2

  (2300) 0x4c9678 B.NE	4c9660

0x4c967c FADDV	D16, P6, Z7.D

0x4c9680 FADD	D0, D0, D16

0x4c9684 LDR	D26, [X15, X1,LSL #3]

0x4c9688 FMUL	D17, D30, D0

0x4c968c LDR	D28, [X12, X1,LSL #3]

0x4c9690 FDIV	D18, D17, D26

0x4c9694 FADD	D19, D28, D18

0x4c9698 STR	D19, [X12, X1,LSL #3]

0x4c969c ADD	X1, X1, #1

0x4c96a0 CMP	X30, X1

0x4c96a4 B.NE	4c95d4

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

[...]

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

Coverage (%)	Name	Source Location	Module
►98.32+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.61+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_ParCSRRelaxThreads	ams.c:3662	exec
○	hypre_BoomerAMGCycle	par_cycle.c:394	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.05
CQA speedup if FP arith vectorized	1.10
CQA speedup if fully vectorized	1.84
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source	ams.c:3662-3662,ams.c:3669-3672,ams.c:3677-3677,ams.c:3682-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.13
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	2.78
Front-end cycles	5.13
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	4.25
P6 cycles	3.25
P7 cycles	3.25
P8 cycles	3.25
P9 cycles	3.25
P10 cycles	3.17
P11 cycles	2.83
P12 cycles	3.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	41.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.54
Nb FLOP add-sub	11.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	6.90
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	18.18
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.66
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	38.64
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	19.53

Metric	Value
CQA speedup if no scalar integer	2.05
CQA speedup if FP arith vectorized	1.10
CQA speedup if fully vectorized	1.84
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source	ams.c:3662-3662,ams.c:3669-3672,ams.c:3677-3677,ams.c:3682-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.13
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	2.78
Front-end cycles	5.13
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	4.25
P6 cycles	3.25
P7 cycles	3.25
P8 cycles	3.25
P9 cycles	3.25
P10 cycles	3.17
P11 cycles	2.83
P12 cycles	3.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	41.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.54
Nb FLOP add-sub	11.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	6.90
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	18.18
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.66
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	38.64
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	19.53

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source file and lines	ams.c:3662-3682
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3672,3677,3682.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.13 to 2.50 cycles (2.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 5.13 to 2.78 cycles (1.84x speedup).

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
18% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 13 FP arithmetical operations:

11: addition or subtraction
1: multiply
1: divide

The binary loop does not load or store any data.

General properties

nb instructions	42
nb uops	41
loop length	168
used w registers	0
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	11
used q registers	0
used v registers	0
used z registers	2
nb stack references	0
ADD-SUB / MUL ratio	5.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.13 cycles
front end	5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.25	4.25	4.25	4.25	3.25	3.25	3.25	3.25	3.17	2.83	3.00	0.00	0.00
cycles	2.50	2.50	4.25	4.25	4.25	4.25	3.25	3.25	3.25	3.25	3.17	2.83	3.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	5.13
Dispatch	4.25
DIV/SQRT	1.75-3.50
Overall L1	5.13

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	6%
load	0%
store	0%
mul	0%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	22%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	43%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	55%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	28%
load	25%
store	25%
mul	25%
add-sub	38%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.13 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.13 to 4.25 cycles (1.21x speedup).

ASM code

In the binary file, the address of the loop is: 4c95d4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4c96a8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X3, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X10, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D6, [X10, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMP D31, D6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 4c95c8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D0, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X5, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4c9634 <hypre_ParCSRRelaxThreads._omp_fn.1+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X21, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z2.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X7, X2, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELO P7.D, XZR, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
FADDV D1, P6, Z2.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2	vect (100.0%)
FADD D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X3, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4c9684 <hypre_ParCSRRelaxThreads._omp_fn.1+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X18, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X2, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X20, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELO P0.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
DUP Z7.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
HINT #0																			N/A
FADDV D16, P6, Z7.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2	vect (100.0%)
FADD D0, D0, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D26, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D17, D30, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D28, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FDIV D18, D17, D26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FADD D19, D28, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D19, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 4c95d4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source file and lines	ams.c:3662-3682
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.13 to 2.50 cycles (2.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
18% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 13 FP arithmetical operations:

11: addition or subtraction
1: multiply
1: divide

The binary loop does not load or store any data.

General properties

nb instructions	42
nb uops	41
loop length	168
used w registers	0
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	11
used q registers	0
used v registers	0
used z registers	2
nb stack references	0
ADD-SUB / MUL ratio	5.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.13 cycles
front end	5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.25	4.25	4.25	4.25	3.25	3.25	3.25	3.25	3.17	2.83	3.00	0.00	0.00
cycles	2.50	2.50	4.25	4.25	4.25	4.25	3.25	3.25	3.25	3.25	3.17	2.83	3.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	5.13
Dispatch	4.25
DIV/SQRT	1.75-3.50
Overall L1	5.13

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	6%
load	0%
store	0%
mul	0%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	22%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	43%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	55%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	28%
load	25%
store	25%
mul	25%
add-sub	38%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.13 cycles.

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4c95d4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4c96a8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X3, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X10, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D6, [X10, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMP D31, D6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 4c95c8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D0, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X5, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4c9634 <hypre_ParCSRRelaxThreads._omp_fn.1+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X21, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z2.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X7, X2, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELO P7.D, XZR, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
FADDV D1, P6, Z2.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2	vect (100.0%)
FADD D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X3, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4c9684 <hypre_ParCSRRelaxThreads._omp_fn.1+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X18, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X2, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X20, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELO P0.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
DUP Z7.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
HINT #0																			N/A
FADDV D16, P6, Z7.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2	vect (100.0%)
FADD D0, D0, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D26, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D17, D30, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D28, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FDIV D18, D17, D26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FADD D19, D28, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D19, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 4c95d4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code