OV - exec - Loop 2654

0x4e7028 LDR	X25, [X6, X17,LSL #3]

0x4e702c UBFM	X18, X25, #61, #60

0x4e7030 ADD	X30, X18, #8

0x4e7034 LDR	X12, [X23, X18]

0x4e7038 ADD	X25, X23, X30

0x4e703c LDR	X16, [X23, X30]

0x4e7040 CMP	X12, X16

0x4e7044 B.GE	4e7084

0x4e7048 ORR	X13, XZR, X5

0x4e704c STR	X0, [SP, #104]

  (2657) 0x4e7050 LDR	X0, [X21, X12,LSL #3]

  (2657) 0x4e7054 UBFM	X5, X0, #61, #60

  (2657) 0x4e7058 LDR	X0, [X19, X5]

  (2657) 0x4e705c CMP	X20, X0

  (2657) 0x4e7060 B.LE	4e71b0

  (2657) 0x4e7064 STR	X3, [X19, X5]

  (2657) 0x4e7068 ADD	X12, X12, #1

  (2657) 0x4e706c ADD	X3, X3, #1

  (2657) 0x4e7070 LDR	X16, [X25]

  (2657) 0x4e7074 CMP	X16, X12

  (2657) 0x4e7078 B.GT	4e7050

0x4e707c LDR	X0, [SP, #104]

0x4e7080 ORR	X5, XZR, X13

0x4e7084 CBNZ	X5, 4e71f8

0x4e7088 LDR	X18, [X28, X15]

0x4e708c ADD	X17, X17, #1

0x4e7090 CMP	X18, X17

0x4e7094 B.GT	4e7028

  (2657) 0x4e71b0 ADD	X12, X12, #1

  (2657) 0x4e71b4 CMP	X12, X16

  (2657) 0x4e71b8 B.LT	4e7050

0x4e71bc LDR	X0, [SP, #104]

0x4e71c0 ORR	X5, XZR, X13

0x4e71c4 B	4e7084

0x4e71f8 LDR	X13, [X9, X18]

0x4e71fc ADD	X18, X9, X30

0x4e7200 LDR	X25, [X9, X30]

0x4e7204 CMP	X13, X25

0x4e7208 B.GE	4e7088

  (2655) 0x4e720c LDR	X30, [X27, X13,LSL #3]

  (2655) 0x4e7210 LDR	X12, [X24, X30,LSL #3]

  (2655) 0x4e7214 ADD	X16, X22, X12

  (2655) 0x4e7218 UBFM	X30, X16, #61, #60

  (2655) 0x4e721c LDR	X12, [X19, X30]

  (2655) 0x4e7220 CMP	X14, X12

  (2655) 0x4e7224 B.LE	4e725c

  (2656) 0x4e7228 STR	X11, [X19, X30]

  (2656) 0x4e722c ADD	X13, X13, #1

  (2656) 0x4e7230 ADD	X11, X11, #1

  (2656) 0x4e7234 LDR	X25, [X18]

  (2656) 0x4e7238 CMP	X25, X13

  (2656) 0x4e723c B.LE	4e7088

  (2656) 0x4e7240 LDR	X30, [X27, X13,LSL #3]

  (2656) 0x4e7244 LDR	X12, [X24, X30,LSL #3]

  (2656) 0x4e7248 ADD	X16, X22, X12

  (2656) 0x4e724c UBFM	X30, X16, #61, #60

  (2656) 0x4e7250 LDR	X12, [X19, X30]

  (2656) 0x4e7254 CMP	X14, X12

  (2656) 0x4e7258 B.GT	4e7228

  (2655) 0x4e725c ADD	X13, X13, #1

  (2655) 0x4e7260 CMP	X25, X13

  (2655) 0x4e7264 B.GT	4e720c

0x4e7268 B	4e7088

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 187 - 231

--------------------------------------------------------------------------------

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

Coverage (%)	Name	Source Location	Module
►98.07+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.93+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_ParMatmul_RowSizes	par_csr_matop.c:102	exec
○	hypre_ParMatmul	par_csr_matop.c:811	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:187-187,par_csr_matop.c:195-195,par_csr_matop.c:216-218
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.25
CQA cycles if no scalar integer	3.25
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	0.81
Front-end cycles	3.25
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.17
P11 cycles	2.83
P12 cycles	3.00
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:187-187,par_csr_matop.c:195-195,par_csr_matop.c:216-218
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.25
CQA cycles if no scalar integer	3.25
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	0.81
Front-end cycles	3.25
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.17
P11 cycles	2.83
P12 cycles	3.00
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:187-231
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:187,195,205-208,216-220,228-231.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:187,195,216-218.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 15 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.25 to 0.81 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	26
nb uops	26
loop length	104
used w registers	0
used x registers	15
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50
cycles	3.00	3.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.25
Dispatch	3.17
Overall L1	3.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.25 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 4e7028

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X25, [X6, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X18, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X30, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X23, X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X25, X23, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X23, X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4e7084 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X13, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X5, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CBNZ X5, 4e71f8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X28, X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 4e7028 <hypre_ParMatmul_RowSizes._omp_fn.0+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X5, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B 4e7084 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X9, X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X9, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X25, [X9, X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GE 4e7088 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e7088 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:187-231
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:187,195,205-208,216-220,228-231.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:187,195,216-218.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 15 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.25 to 0.81 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	26
nb uops	26
loop length	104
used w registers	0
used x registers	15
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50
cycles	3.00	3.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.25
Dispatch	3.17
Overall L1	3.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.25 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 4e7028

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X25, [X6, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X18, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X30, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X23, X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X25, X23, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X23, X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4e7084 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X13, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X5, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CBNZ X5, 4e71f8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X28, X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 4e7028 <hypre_ParMatmul_RowSizes._omp_fn.0+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X5, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B 4e7084 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X9, X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X9, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X25, [X9, X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GE 4e7088 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e7088 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code