OV - exec - Loop 3042

	Loop Id: 3042	Module: exec	Source: IJMatrix_parcsr.c:3383-3484 [...]	Coverage: 0.13%

0x505e00 LDR	X1, [X28, X21,LSL #3]

0x505e04 CMP	X8, X1

0x505e08 CCMP	X7, X1, #1, #13

0x505e0c B.GE	505fd4

0x505e10 LDR	X0, [X18, X13]

0x505e14 CMP	X2, X0

0x505e18 B.LE	505f6c

0x505e1c SUB	X25, X2, X0

0x505e20 ANDS	X25, X25, #0x7

0x505e24 B.EQ	505ed0

0x505e28 CMP	X25, #1

0x505e2c B.EQ	505eb8

0x505e30 CMP	X25, #2

0x505e34 B.EQ	505ea8

0x505e38 CMP	X25, #3

0x505e3c B.EQ	505e98

0x505e40 CMP	X25, #4

0x505e44 B.EQ	505e88

0x505e48 CMP	X25, #5

0x505e4c B.EQ	505e78

0x505e50 CMP	X25, #6

0x505e54 B.EQ	505e68

0x505e58 LDR	X25, [X23, X0,LSL #3]

0x505e5c CMP	X1, X25

0x505e60 B.EQ	506470

0x505e64 ADD	X0, X0, #1

0x505e68 LDR	X25, [X23, X0,LSL #3]

0x505e6c CMP	X1, X25

0x505e70 B.EQ	506470

0x505e74 ADD	X0, X0, #1

0x505e78 LDR	X25, [X23, X0,LSL #3]

0x505e7c CMP	X1, X25

0x505e80 B.EQ	506470

0x505e84 ADD	X0, X0, #1

0x505e88 LDR	X25, [X23, X0,LSL #3]

0x505e8c CMP	X1, X25

0x505e90 B.EQ	506470

0x505e94 ADD	X0, X0, #1

0x505e98 LDR	X25, [X23, X0,LSL #3]

0x505e9c CMP	X1, X25

0x505ea0 B.EQ	506470

0x505ea4 ADD	X0, X0, #1

0x505ea8 LDR	X25, [X23, X0,LSL #3]

0x505eac CMP	X1, X25

0x505eb0 B.EQ	506470

0x505eb4 ADD	X0, X0, #1

0x505eb8 LDR	X25, [X23, X0,LSL #3]

0x505ebc CMP	X1, X25

0x505ec0 B.EQ	506470

0x505ec4 ADD	X0, X0, #1

0x505ec8 CMP	X2, X0

0x505ecc B.EQ	505f6c

0x505ed0 ORR	X25, XZR, X9

0x505ed4 STR	X3, [SP, #112]

  (3044) 0x505ed8 LDR	X9, [X23, X0,LSL #3]

  (3044) 0x505edc CMP	X1, X9

  (3044) 0x505ee0 B.EQ	506468

  (3044) 0x505ee4 ADD	X0, X0, #1

  (3044) 0x505ee8 LDR	X3, [X23, X0,LSL #3]

  (3044) 0x505eec ORR	X9, XZR, X0

  (3044) 0x505ef0 CMP	X1, X3

  (3044) 0x505ef4 B.EQ	506468

  (3044) 0x505ef8 ADD	X0, X0, #1

  (3044) 0x505efc LDR	X3, [X23, X0,LSL #3]

  (3044) 0x505f00 CMP	X1, X3

  (3044) 0x505f04 B.EQ	506468

  (3044) 0x505f08 ADD	X0, X9, #2

  (3044) 0x505f0c LDR	X3, [X23, X0,LSL #3]

  (3044) 0x505f10 CMP	X1, X3

  (3044) 0x505f14 B.EQ	506468

  (3044) 0x505f18 ADD	X0, X9, #3

  (3044) 0x505f1c LDR	X3, [X23, X0,LSL #3]

  (3044) 0x505f20 CMP	X1, X3

  (3044) 0x505f24 B.EQ	506468

  (3044) 0x505f28 ADD	X0, X9, #4

  (3044) 0x505f2c LDR	X3, [X23, X0,LSL #3]

  (3044) 0x505f30 CMP	X1, X3

  (3044) 0x505f34 B.EQ	506468

  (3044) 0x505f38 ADD	X0, X9, #5

  (3044) 0x505f3c LDR	X3, [X23, X0,LSL #3]

  (3044) 0x505f40 CMP	X1, X3

  (3044) 0x505f44 B.EQ	506468

  (3044) 0x505f48 ADD	X0, X9, #6

  (3044) 0x505f4c LDR	X3, [X23, X0,LSL #3]

  (3044) 0x505f50 CMP	X1, X3

  (3044) 0x505f54 B.EQ	506468

  (3044) 0x505f58 ADD	X0, X9, #7

  (3044) 0x505f5c CMP	X2, X0

  (3044) 0x505f60 B.NE	505ed8

0x505f64 LDR	X3, [SP, #112]

0x505f68 ORR	X9, XZR, X25

0x505f6c CMP	X30, X14

0x505f70 B.LE	5068e4

0x505f74 LDR	D1, [X26, X21,LSL #3]

0x505f78 UBFM	X25, X14, #61, #60

0x505f7c ADD	X14, X14, #1

0x505f80 STR	X1, [X23, X25]

0x505f84 STR	D1, [X5, X25]

0x505f88 ADD	X21, X21, #1

0x505f8c CMP	X21, X16

0x505f90 B.NE	505e00

0x505fd4 LDR	X0, [X10, X13]

0x505fd8 CMP	X3, X0

0x505fdc B.LE	506130

0x505fe0 SUB	X25, X3, X0

0x505fe4 ANDS	X25, X25, #0x7

0x505fe8 B.EQ	506094

0x505fec CMP	X25, #1

0x505ff0 B.EQ	50607c

0x505ff4 CMP	X25, #2

0x505ff8 B.EQ	50606c

0x505ffc CMP	X25, #3

0x506000 B.EQ	50605c

0x506004 CMP	X25, #4

0x506008 B.EQ	50604c

0x50600c CMP	X25, #5

0x506010 B.EQ	50603c

0x506014 CMP	X25, #6

0x506018 B.EQ	50602c

0x50601c LDR	X25, [X24, X0,LSL #3]

0x506020 CMP	X1, X25

0x506024 B.EQ	506484

0x506028 ADD	X0, X0, #1

0x50602c LDR	X25, [X24, X0,LSL #3]

0x506030 CMP	X1, X25

0x506034 B.EQ	506484

0x506038 ADD	X0, X0, #1

0x50603c LDR	X25, [X24, X0,LSL #3]

0x506040 CMP	X1, X25

0x506044 B.EQ	506484

0x506048 ADD	X0, X0, #1

0x50604c LDR	X25, [X24, X0,LSL #3]

0x506050 CMP	X1, X25

0x506054 B.EQ	506484

0x506058 ADD	X0, X0, #1

0x50605c LDR	X25, [X24, X0,LSL #3]

0x506060 CMP	X1, X25

0x506064 B.EQ	506484

0x506068 ADD	X0, X0, #1

0x50606c LDR	X25, [X24, X0,LSL #3]

0x506070 CMP	X1, X25

0x506074 B.EQ	506484

0x506078 ADD	X0, X0, #1

0x50607c LDR	X25, [X24, X0,LSL #3]

0x506080 CMP	X1, X25

0x506084 B.EQ	506484

0x506088 ADD	X0, X0, #1

0x50608c CMP	X3, X0

0x506090 B.EQ	506130

0x506094 ORR	X25, XZR, X9

0x506098 STR	X2, [SP, #112]

  (3043) 0x50609c LDR	X9, [X24, X0,LSL #3]

  (3043) 0x5060a0 CMP	X1, X9

  (3043) 0x5060a4 B.EQ	50647c

  (3043) 0x5060a8 ADD	X0, X0, #1

  (3043) 0x5060ac LDR	X2, [X24, X0,LSL #3]

  (3043) 0x5060b0 ORR	X9, XZR, X0

  (3043) 0x5060b4 CMP	X1, X2

  (3043) 0x5060b8 B.EQ	50647c

  (3043) 0x5060bc ADD	X0, X0, #1

  (3043) 0x5060c0 LDR	X2, [X24, X0,LSL #3]

  (3043) 0x5060c4 CMP	X1, X2

  (3043) 0x5060c8 B.EQ	50647c

  (3043) 0x5060cc ADD	X0, X9, #2

  (3043) 0x5060d0 LDR	X2, [X24, X0,LSL #3]

  (3043) 0x5060d4 CMP	X1, X2

  (3043) 0x5060d8 B.EQ	50647c

  (3043) 0x5060dc ADD	X0, X9, #3

  (3043) 0x5060e0 LDR	X2, [X24, X0,LSL #3]

  (3043) 0x5060e4 CMP	X1, X2

  (3043) 0x5060e8 B.EQ	50647c

  (3043) 0x5060ec ADD	X0, X9, #4

  (3043) 0x5060f0 LDR	X2, [X24, X0,LSL #3]

  (3043) 0x5060f4 CMP	X1, X2

  (3043) 0x5060f8 B.EQ	50647c

  (3043) 0x5060fc ADD	X0, X9, #5

  (3043) 0x506100 LDR	X2, [X24, X0,LSL #3]

  (3043) 0x506104 CMP	X1, X2

  (3043) 0x506108 B.EQ	50647c

  (3043) 0x50610c ADD	X0, X9, #6

  (3043) 0x506110 LDR	X2, [X24, X0,LSL #3]

  (3043) 0x506114 CMP	X1, X2

  (3043) 0x506118 B.EQ	50647c

  (3043) 0x50611c ADD	X0, X9, #7

  (3043) 0x506120 CMP	X3, X0

  (3043) 0x506124 B.NE	50609c

0x506128 LDR	X2, [SP, #112]

0x50612c ORR	X9, XZR, X25

0x506130 CMP	X17, X15

0x506134 B.LE	5069b8

0x506138 LDR	D31, [X26, X21,LSL #3]

0x50613c UBFM	X0, X15, #61, #60

0x506140 ADD	X15, X15, #1

0x506144 STR	X1, [X24, X0]

0x506148 STR	D31, [X12, X0]

0x50614c B	505f88

0x506468 LDR	X3, [SP, #112]

0x50646c ORR	X9, XZR, X25

0x506470 LDR	D2, [X26, X21,LSL #3]

0x506474 STR	D2, [X5, X0,LSL #3]

0x506478 B	505f88

0x50647c LDR	X2, [SP, #112]

0x506480 ORR	X9, XZR, X25

0x506484 LDR	D0, [X26, X21,LSL #3]

0x506488 STR	D0, [X12, X0,LSL #3]

0x50648c B	505f88

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3383 - 3484

--------------------------------------------------------------------------------

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

3391: 		           {

3392:                               offd_data[j] = values[indx];

3393: 		              not_found = 0;

3394: 		              break;

3395: 		           }

3396: 	                }

3397: 	                if (not_found)

3398: 	                {

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

[...]

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

3425: 		           {

3426:                               diag_data[j] = values[indx];

3427: 		              not_found = 0;

3428: 		              break;

3429: 		           }

3430: 	                }

3431: 	                if (not_found)

3432: 	                {

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

[...]

3454: 	             indx++;

[...]

3484: 	                         offproc_cnt[my_thread_num]++;

Coverage (%)	Name	Source Location	Module
►98.13+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.87+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_IJMatrixSetValuesOMPParC[...]	IJMatrix_parcsr.c:3509	exec
○	BuildIJLaplacian27pt	amg.c:2267	exec
○	main	amg.c:274	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	7.31
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	P0, P1,
Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:3383-3385,IJMatrix_parcsr.c:3388-3392,IJMatrix_parcsr.c:3397-3402,IJMatrix_parcsr.c:3422-3426,IJMatrix_parcsr.c:3431-3436,IJMatrix_parcsr.c:3454-3454,IJMatrix_parcsr.c:3484-3484
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.50
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	19.50
CQA cycles if fully vectorized	4.88
Front-end cycles	17.00
P0 cycles	19.50
P1 cycles	19.50
P2 cycles	16.00
P3 cycles	16.00
P4 cycles	16.00
P5 cycles	16.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	11.00
P13 cycles	2.00
P14 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	136.00
Nb uops	136.00
Nb loads	NA
Nb stores	8.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	7.31
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	P0, P1,
Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:3383-3385,IJMatrix_parcsr.c:3388-3392,IJMatrix_parcsr.c:3397-3402,IJMatrix_parcsr.c:3422-3426,IJMatrix_parcsr.c:3431-3436,IJMatrix_parcsr.c:3454-3454,IJMatrix_parcsr.c:3484-3484
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.50
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	19.50
CQA cycles if fully vectorized	4.88
Front-end cycles	17.00
P0 cycles	19.50
P1 cycles	19.50
P2 cycles	16.00
P3 cycles	16.00
P4 cycles	16.00
P5 cycles	16.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	11.00
P13 cycles	2.00
P14 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	136.00
Nb uops	136.00
Nb loads	NA
Nb stores	8.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:3383-3484
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3383-3402,3422-3436,3454,3484.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3383-3385,3388-3392,3397-3402,3422-3426,3431-3436,3454,3484.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 216 paths individually, rerun with max-paths=216
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 216 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.50 to 2.67 cycles (7.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 19.50 to 4.87 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	136
nb uops	136
loop length	544
used w registers	0
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	4
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	19.50	19.50	16.00	16.00	16.00	16.00	2.00	2.00	0.00	0.00	11.00	11.00	11.00	2.00	2.00
cycles	19.50	19.50	16.00	16.00	16.00	16.00	2.00	2.00	0.00	0.00	11.00	11.00	11.00	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.00
Dispatch	19.50
Overall L1	19.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 505e00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X1, [X28, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X7, X1, #1, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.GE 505fd4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x654>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X18, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 505f6c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x5ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X25, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X25, X25, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 505ed0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505eb8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x538>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505ea8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x528>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505e98 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505e88 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505e78 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505e68 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x4e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505f6c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x5ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X30, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 5068e4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
UBFM X25, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X1, [X23, X25]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR D1, [X5, X25]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X21, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 505e00 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X10, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 506130 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X25, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X25, X25, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 506094 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50607c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50606c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50605c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50604c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50603c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50602c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506130 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X17, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 5069b8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1038>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D31, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
UBFM X0, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [X24, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR D31, [X12, X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 505f88 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D2, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D2, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 505f88 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D0, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D0, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 505f88 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:3383-3484
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 216 paths individually, rerun with max-paths=216
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.50 to 2.67 cycles (7.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	136
nb uops	136
loop length	544
used w registers	0
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	4
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	19.50	19.50	16.00	16.00	16.00	16.00	2.00	2.00	0.00	0.00	11.00	11.00	11.00	2.00	2.00
cycles	19.50	19.50	16.00	16.00	16.00	16.00	2.00	2.00	0.00	0.00	11.00	11.00	11.00	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.00
Dispatch	19.50
Overall L1	19.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 505e00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X1, [X28, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X7, X1, #1, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.GE 505fd4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x654>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X18, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 505f6c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x5ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X25, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X25, X25, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 505ed0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505eb8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x538>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505ea8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x528>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505e98 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505e88 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505e78 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505e68 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x4e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506470 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xaf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 505f6c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x5ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X30, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 5068e4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
UBFM X25, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X1, [X23, X25]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR D1, [X5, X25]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X21, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 505e00 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X10, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 506130 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X25, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X25, X25, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 506094 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50607c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50606c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50605c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50604c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50603c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 50602c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506484 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 506130 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X17, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 5069b8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1038>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D31, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
UBFM X0, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [X24, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR D31, [X12, X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 505f88 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D2, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D2, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 505f88 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D0, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D0, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 505f88 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code