OV - exec - Loop 662

	Loop Id: 662	Module: exec	Source: par_multi_interp.c:1072-1125	Coverage: 0.04%

0x456960 LDR	X21, [SP, #104]

0x456964 LDR	X6, [X21, X9,LSL #3]

0x456968 UBFM	X15, X6, #61, #60

0x45696c ORN	X0, XZR, X6

0x456970 ADD	X14, X15, #8

0x456974 LDR	X3, [X12, X15]

0x456978 ADD	X5, X12, X14

0x45697c LDR	X13, [X12, X14]

0x456980 CMP	X3, X13

0x456984 B.GE	456ce8

0x456988 ORR	X28, XZR, X24

0x45698c STR	X6, [SP, #128]

0x456990 ORR	X6, XZR, X5

0x456994 B	4569a4

  (665) 0x456998 ADD	X3, X3, #1

  (665) 0x45699c CMP	X3, X13

  (665) 0x4569a0 B.GE	456ce0

  (665) 0x4569a4 LDR	X24, [X27, X3,LSL #3]

  (665) 0x4569a8 UBFM	X1, X24, #61, #60

  (665) 0x4569ac LDR	X16, [X25, X1]

  (665) 0x4569b0 CMP	X16, X7

  (665) 0x4569b4 B.NE	456998

  (665) 0x4569b8 LDR	X21, [SP, #152]

  (665) 0x4569bc ADD	X16, X1, #8

  (665) 0x4569c0 LDR	X13, [X23, X16]

  (665) 0x4569c4 LDR	X5, [X21, X1]

  (665) 0x4569c8 ADD	X13, X5, X13

  (665) 0x4569cc CMP	X5, X13

  (665) 0x4569d0 B.GE	456b58

  (665) 0x4569d4 LDR	X24, [SP, #160]

  (665) 0x4569d8 UBFM	X21, X5, #61, #60

  (665) 0x4569dc STR	X21, [SP, #144]

  (665) 0x4569e0 LDUR	X24, [X24, #504]

  (665) 0x4569e4 ADD	X13, X24, X13,LSL #3

  (665) 0x4569e8 ADD	X5, X24, X5,LSL #3

  (665) 0x4569ec SUB	X21, X13, X5

  (665) 0x4569f0 STR	X13, [SP, #96]

  (665) 0x4569f4 SUB	X21, X21, #8

  (665) 0x4569f8 UBFM	X21, X21, #3, #63

  (665) 0x4569fc ADD	X21, X21, #1

  (665) 0x456a00 ANDS	X21, X21, #0x3

  (665) 0x456a04 B.EQ	456aa0

  (665) 0x456a08 CMP	X21, #1

  (665) 0x456a0c B.EQ	456a6c

  (665) 0x456a10 CMP	X21, #2

  (665) 0x456a14 B.EQ	456a44

  (665) 0x456a18 LDR	X13, [SP, #144]

  (665) 0x456a1c LDR	X24, [X24, X13]

  (665) 0x456a20 UBFM	X21, X24, #61, #60

  (665) 0x456a24 LDR	X13, [X20, X21]

  (665) 0x456a28 CMP	X13, X0

  (665) 0x456a2c B.EQ	456a40

  (665) 0x456a30 LDR	X13, [X10, X22]

  (665) 0x456a34 STR	X24, [X13, X4,LSL #3]

  (665) 0x456a38 ADD	X4, X4, #1

  (665) 0x456a3c STR	X0, [X20, X21]

  (665) 0x456a40 ADD	X5, X5, #8

  (665) 0x456a44 LDR	X24, [X5]

  (665) 0x456a48 UBFM	X21, X24, #61, #60

  (665) 0x456a4c LDR	X13, [X20, X21]

  (665) 0x456a50 CMP	X13, X0

  (665) 0x456a54 B.EQ	456a68

  (665) 0x456a58 LDR	X13, [X10, X22]

  (665) 0x456a5c STR	X24, [X13, X4,LSL #3]

  (665) 0x456a60 ADD	X4, X4, #1

  (665) 0x456a64 STR	X0, [X20, X21]

  (665) 0x456a68 ADD	X5, X5, #8

  (665) 0x456a6c LDR	X24, [X5]

  (665) 0x456a70 UBFM	X21, X24, #61, #60

  (665) 0x456a74 LDR	X13, [X20, X21]

  (665) 0x456a78 CMP	X13, X0

  (665) 0x456a7c B.EQ	456a90

  (665) 0x456a80 LDR	X13, [X10, X22]

  (665) 0x456a84 STR	X24, [X13, X4,LSL #3]

  (665) 0x456a88 ADD	X4, X4, #1

  (665) 0x456a8c STR	X0, [X20, X21]

  (665) 0x456a90 LDR	X13, [SP, #96]

  (665) 0x456a94 ADD	X5, X5, #8

  (665) 0x456a98 CMP	X13, X5

  (665) 0x456a9c B.EQ	456b58

  (665) 0x456aa0 ORR	X24, XZR, X2

  (665) 0x456aa4 STR	X1, [SP, #96]

  (665) 0x456aa8 STR	X19, [SP, #144]

    (667) 0x456aac LDR	X21, [X5]

    (667) 0x456ab0 ADD	X2, X5, #8

    (667) 0x456ab4 UBFM	X19, X21, #61, #60

    (667) 0x456ab8 LDR	X1, [X20, X19]

    (667) 0x456abc CMP	X1, X0

    (667) 0x456ac0 B.EQ	456ad4

    (667) 0x456ac4 LDR	X1, [X10, X22]

    (667) 0x456ac8 STR	X21, [X1, X4,LSL #3]

    (667) 0x456acc ADD	X4, X4, #1

    (667) 0x456ad0 STR	X0, [X20, X19]

    (667) 0x456ad4 LDR	X19, [X5, #8]

    (667) 0x456ad8 UBFM	X5, X19, #61, #60

    (667) 0x456adc LDR	X21, [X20, X5]

    (667) 0x456ae0 CMP	X21, X0

    (667) 0x456ae4 B.EQ	456af8

    (667) 0x456ae8 LDR	X1, [X10, X22]

    (667) 0x456aec STR	X19, [X1, X4,LSL #3]

    (667) 0x456af0 ADD	X4, X4, #1

    (667) 0x456af4 STR	X0, [X20, X5]

    (667) 0x456af8 LDR	X21, [X2, #8]

    (667) 0x456afc ADD	X5, X2, #24

    (667) 0x456b00 UBFM	X19, X21, #61, #60

    (667) 0x456b04 LDR	X1, [X20, X19]

    (667) 0x456b08 CMP	X1, X0

    (667) 0x456b0c B.EQ	456b20

    (667) 0x456b10 LDR	X1, [X10, X22]

    (667) 0x456b14 STR	X21, [X1, X4,LSL #3]

    (667) 0x456b18 ADD	X4, X4, #1

    (667) 0x456b1c STR	X0, [X20, X19]

    (667) 0x456b20 LDR	X19, [X2, #16]

    (667) 0x456b24 UBFM	X2, X19, #61, #60

    (667) 0x456b28 LDR	X21, [X20, X2]

    (667) 0x456b2c CMP	X21, X0

    (667) 0x456b30 B.EQ	456b44

    (667) 0x456b34 LDR	X1, [X10, X22]

    (667) 0x456b38 STR	X19, [X1, X4,LSL #3]

    (667) 0x456b3c ADD	X4, X4, #1

    (667) 0x456b40 STR	X0, [X20, X2]

    (667) 0x456b44 CMP	X13, X5

    (667) 0x456b48 B.NE	456aac

  (665) 0x456b4c LDR	X1, [SP, #96]

  (665) 0x456b50 ORR	X2, XZR, X24

  (665) 0x456b54 LDR	X19, [SP, #144]

  (665) 0x456b58 LDR	X13, [SP, #136]

  (665) 0x456b5c LDR	X16, [X18, X16]

  (665) 0x456b60 LDR	X24, [X13, X1]

  (665) 0x456b64 ADD	X5, X24, X16

  (665) 0x456b68 CMP	X24, X5

  (665) 0x456b6c B.GE	456ccc

  (665) 0x456b70 LDR	X1, [SP, #168]

  (665) 0x456b74 UBFM	X21, X24, #61, #60

  (665) 0x456b78 LDUR	X16, [X1, #504]

  (665) 0x456b7c ADD	X1, X16, X24,LSL #3

  (665) 0x456b80 ADD	X5, X16, X5,LSL #3

  (665) 0x456b84 SUB	X13, X5, X1

  (665) 0x456b88 SUB	X24, X13, #8

  (665) 0x456b8c UBFM	X13, X24, #3, #63

  (665) 0x456b90 ADD	X24, X13, #1

  (665) 0x456b94 ANDS	X13, X24, #0x3

  (665) 0x456b98 B.EQ	456c2c

  (665) 0x456b9c CMP	X13, #1

  (665) 0x456ba0 B.EQ	456bfc

  (665) 0x456ba4 CMP	X13, #2

  (665) 0x456ba8 B.EQ	456bd4

  (665) 0x456bac LDR	X16, [X16, X21]

  (665) 0x456bb0 UBFM	X24, X16, #61, #60

  (665) 0x456bb4 LDR	X21, [X19, X24]

  (665) 0x456bb8 CMP	X21, X0

  (665) 0x456bbc B.EQ	456bd0

  (665) 0x456bc0 LDR	X13, [X8, X22]

  (665) 0x456bc4 STR	X16, [X13, X2,LSL #3]

  (665) 0x456bc8 ADD	X2, X2, #1

  (665) 0x456bcc STR	X0, [X19, X24]

  (665) 0x456bd0 ADD	X1, X1, #8

  (665) 0x456bd4 LDR	X16, [X1]

  (665) 0x456bd8 UBFM	X24, X16, #61, #60

  (665) 0x456bdc LDR	X21, [X19, X24]

  (665) 0x456be0 CMP	X21, X0

  (665) 0x456be4 B.EQ	456bf8

  (665) 0x456be8 LDR	X13, [X8, X22]

  (665) 0x456bec STR	X16, [X13, X2,LSL #3]

  (665) 0x456bf0 ADD	X2, X2, #1

  (665) 0x456bf4 STR	X0, [X19, X24]

  (665) 0x456bf8 ADD	X1, X1, #8

  (665) 0x456bfc LDR	X16, [X1]

  (665) 0x456c00 UBFM	X24, X16, #61, #60

  (665) 0x456c04 LDR	X21, [X19, X24]

  (665) 0x456c08 CMP	X21, X0

  (665) 0x456c0c B.EQ	456c20

  (665) 0x456c10 LDR	X13, [X8, X22]

  (665) 0x456c14 STR	X16, [X13, X2,LSL #3]

  (665) 0x456c18 ADD	X2, X2, #1

  (665) 0x456c1c STR	X0, [X19, X24]

  (665) 0x456c20 ADD	X1, X1, #8

  (665) 0x456c24 CMP	X1, X5

  (665) 0x456c28 B.EQ	456ccc

    (666) 0x456c2c LDR	X21, [X1]

    (666) 0x456c30 ADD	X13, X1, #8

    (666) 0x456c34 UBFM	X16, X21, #61, #60

    (666) 0x456c38 LDR	X24, [X19, X16]

    (666) 0x456c3c CMP	X24, X0

    (666) 0x456c40 B.EQ	456c54

    (666) 0x456c44 LDR	X24, [X8, X22]

    (666) 0x456c48 STR	X21, [X24, X2,LSL #3]

    (666) 0x456c4c ADD	X2, X2, #1

    (666) 0x456c50 STR	X0, [X19, X16]

    (666) 0x456c54 LDR	X16, [X1, #8]

    (666) 0x456c58 UBFM	X1, X16, #61, #60

    (666) 0x456c5c LDR	X21, [X19, X1]

    (666) 0x456c60 CMP	X21, X0

    (666) 0x456c64 B.EQ	456c78

    (666) 0x456c68 LDR	X24, [X8, X22]

    (666) 0x456c6c STR	X16, [X24, X2,LSL #3]

    (666) 0x456c70 ADD	X2, X2, #1

    (666) 0x456c74 STR	X0, [X19, X1]

    (666) 0x456c78 LDR	X21, [X13, #8]

    (666) 0x456c7c ADD	X1, X13, #24

    (666) 0x456c80 UBFM	X16, X21, #61, #60

    (666) 0x456c84 LDR	X24, [X19, X16]

    (666) 0x456c88 CMP	X24, X0

    (666) 0x456c8c B.EQ	456ca0

    (666) 0x456c90 LDR	X24, [X8, X22]

    (666) 0x456c94 STR	X21, [X24, X2,LSL #3]

    (666) 0x456c98 ADD	X2, X2, #1

    (666) 0x456c9c STR	X0, [X19, X16]

    (666) 0x456ca0 LDR	X16, [X13, #16]

    (666) 0x456ca4 UBFM	X13, X16, #61, #60

    (666) 0x456ca8 LDR	X21, [X19, X13]

    (666) 0x456cac CMP	X21, X0

    (666) 0x456cb0 B.EQ	456cc4

    (666) 0x456cb4 LDR	X24, [X8, X22]

    (666) 0x456cb8 STR	X16, [X24, X2,LSL #3]

    (666) 0x456cbc ADD	X2, X2, #1

    (666) 0x456cc0 STR	X0, [X19, X13]

    (666) 0x456cc4 CMP	X1, X5

    (666) 0x456cc8 B.NE	456c2c

  (665) 0x456ccc LDR	X13, [X6]

  (665) 0x456cd0 ADD	X3, X3, #1

  (665) 0x456cd4 CMP	X3, X13

  (665) 0x456cd8 B.LT	4569a4

0x456cdc HINT	#0

0x456ce0 LDR	X6, [SP, #128]

0x456ce4 ORR	X24, XZR, X28

0x456ce8 ORN	X6, XZR, X6

0x456cec LDR	X1, [X11, X15]

0x456cf0 ADD	X15, X11, X14

0x456cf4 LDR	X3, [X11, X14]

0x456cf8 CMP	X3, X1

0x456cfc B.LE	456e20

0x456d00 LDP	X21, X28, [SP, #112]

0x456d04 B	456d14

  (663) 0x456d08 ADD	X1, X1, #1

  (663) 0x456d0c CMP	X1, X3

  (663) 0x456d10 B.GE	456e20

  (663) 0x456d14 LDR	X0, [X26, X1,LSL #3]

  (663) 0x456d18 UBFM	X14, X0, #61, #60

  (663) 0x456d1c LDR	X5, [X24, X14]

  (663) 0x456d20 CMP	X5, X7

  (663) 0x456d24 B.NE	456d08

  (663) 0x456d28 ADD	X16, X21, X14

  (663) 0x456d2c LDR	X0, [X17, X14]

  (663) 0x456d30 LDR	X13, [X16, #8]

  (663) 0x456d34 ADD	X5, X0, X13

  (663) 0x456d38 CMP	X0, X5

  (663) 0x456d3c B.GE	456d08

  (663) 0x456d40 LDR	X16, [X28, X22]

  (663) 0x456d44 UBFM	X14, X0, #61, #60

  (663) 0x456d48 ADD	X5, X16, X5,LSL #3

  (663) 0x456d4c ADD	X0, X16, X0,LSL #3

  (663) 0x456d50 SUB	X3, X5, X0

  (663) 0x456d54 SUB	X13, X3, #8

  (663) 0x456d58 UBFM	X3, X13, #3, #63

  (663) 0x456d5c ADD	X13, X3, #1

  (663) 0x456d60 ANDS	X3, X13, #0x3

  (663) 0x456d64 B.EQ	456ee8

  (663) 0x456d68 CMP	X3, #1

  (663) 0x456d6c B.EQ	456dd0

  (663) 0x456d70 CMP	X3, #2

  (663) 0x456d74 B.EQ	456da4

  (663) 0x456d78 LDR	X16, [X16, X14]

  (663) 0x456d7c TBNZ	X16, #63, 45702c

  (663) 0x456d80 UBFM	X13, X16, #61, #60

  (663) 0x456d84 LDR	X14, [X19, X13]

  (663) 0x456d88 CMP	X14, X6

  (663) 0x456d8c B.EQ	456da0

  (663) 0x456d90 LDR	X3, [X8, X22]

  (663) 0x456d94 STR	X16, [X3, X2,LSL #3]

  (663) 0x456d98 ADD	X2, X2, #1

  (663) 0x456d9c STR	X6, [X19, X13]

  (663) 0x456da0 ADD	X0, X0, #8

  (663) 0x456da4 LDR	X3, [X0]

  (663) 0x456da8 TBNZ	X3, #63, 457000

  (663) 0x456dac UBFM	X13, X3, #61, #60

  (663) 0x456db0 LDR	X14, [X19, X13]

  (663) 0x456db4 CMP	X14, X6

  (663) 0x456db8 B.EQ	456dcc

  (663) 0x456dbc LDR	X16, [X8, X22]

  (663) 0x456dc0 STR	X3, [X16, X2,LSL #3]

  (663) 0x456dc4 ADD	X2, X2, #1

  (663) 0x456dc8 STR	X6, [X19, X13]

  (663) 0x456dcc ADD	X0, X0, #8

  (663) 0x456dd0 LDR	X16, [X0]

  (663) 0x456dd4 TBNZ	X16, #63, 456fd4

  (663) 0x456dd8 UBFM	X13, X16, #61, #60

  (663) 0x456ddc LDR	X14, [X19, X13]

  (663) 0x456de0 CMP	X14, X6

  (663) 0x456de4 B.EQ	456df8

  (663) 0x456de8 LDR	X3, [X8, X22]

  (663) 0x456dec STR	X16, [X3, X2,LSL #3]

  (663) 0x456df0 ADD	X2, X2, #1

  (663) 0x456df4 STR	X6, [X19, X13]

  (663) 0x456df8 ADD	X0, X0, #8

  (663) 0x456dfc CMP	X0, X5

  (663) 0x456e00 B.NE	456ee8

  (663) 0x456e04 LDR	X3, [X15]

  (663) 0x456e08 ADD	X1, X1, #1

  (663) 0x456e0c CMP	X1, X3

  (663) 0x456e10 B.LT	456d14

0x456e14 HINT	#0

0x456e18 HINT	#0

0x456e1c HINT	#0

0x456e20 ADD	X9, X9, #1

0x456e24 CMP	X30, X9

0x456e28 B.GT	456960

    (664) 0x456e6c UBFM	X13, X16, #61, #60

    (664) 0x456e70 LDR	X14, [X19, X13]

    (664) 0x456e74 CMP	X14, X6

    (664) 0x456e78 B.EQ	456e8c

    (664) 0x456e7c LDR	X3, [X8, X22]

    (664) 0x456e80 STR	X16, [X3, X2,LSL #3]

    (664) 0x456e84 ADD	X2, X2, #1

    (664) 0x456e88 STR	X6, [X19, X13]

    (664) 0x456e8c LDR	X3, [X0, #8]

    (664) 0x456e90 TBNZ	X3, #63, 456f4c

    (664) 0x456e94 UBFM	X13, X3, #61, #60

    (664) 0x456e98 LDR	X14, [X19, X13]

    (664) 0x456e9c CMP	X14, X6

    (664) 0x456ea0 B.EQ	456eb4

    (664) 0x456ea4 LDR	X16, [X8, X22]

    (664) 0x456ea8 STR	X3, [X16, X2,LSL #3]

    (664) 0x456eac ADD	X2, X2, #1

    (664) 0x456eb0 STR	X6, [X19, X13]

    (664) 0x456eb4 LDR	X16, [X0, #16]

    (664) 0x456eb8 TBNZ	X16, #63, 456f7c

    (664) 0x456ebc UBFM	X13, X16, #61, #60

    (664) 0x456ec0 LDR	X14, [X19, X13]

    (664) 0x456ec4 CMP	X14, X6

    (664) 0x456ec8 B.EQ	456edc

    (664) 0x456ecc LDR	X3, [X8, X22]

    (664) 0x456ed0 STR	X16, [X3, X2,LSL #3]

    (664) 0x456ed4 ADD	X2, X2, #1

    (664) 0x456ed8 STR	X6, [X19, X13]

    (664) 0x456edc ADD	X0, X0, #24

    (664) 0x456ee0 CMP	X0, X5

    (664) 0x456ee4 B.EQ	456e04

    (664) 0x456ee8 LDR	X3, [X0]

    (664) 0x456eec TBNZ	X3, #63, 456fa8

    (664) 0x456ef0 UBFM	X13, X3, #61, #60

    (664) 0x456ef4 LDR	X14, [X19, X13]

    (664) 0x456ef8 CMP	X14, X6

    (664) 0x456efc B.EQ	456f10

    (664) 0x456f00 LDR	X16, [X8, X22]

    (664) 0x456f04 STR	X3, [X16, X2,LSL #3]

    (664) 0x456f08 ADD	X2, X2, #1

    (664) 0x456f0c STR	X6, [X19, X13]

    (664) 0x456f10 LDR	X16, [X0, #8]

    (664) 0x456f14 ADD	X0, X0, #8

    (664) 0x456f18 TBZ	X16, #63, 456e6c

    (664) 0x456f1c ORN	X13, XZR, X16

    (664) 0x456f20 UBFM	X13, X13, #61, #60

    (664) 0x456f24 LDR	X14, [X20, X13]

    (664) 0x456f28 CMP	X14, X6

    (664) 0x456f2c B.EQ	456e8c

    (664) 0x456f30 LDR	X14, [X10, X22]

    (664) 0x456f34 ORN	X16, XZR, X16

    (664) 0x456f38 STR	X16, [X14, X4,LSL #3]

    (664) 0x456f3c ADD	X4, X4, #1

    (664) 0x456f40 STR	X6, [X20, X13]

    (664) 0x456f44 LDR	X3, [X0, #8]

    (664) 0x456f48 TBZ	X3, #63, 456e94

    (664) 0x456f4c ORN	X13, XZR, X3

    (664) 0x456f50 UBFM	X16, X13, #61, #60

    (664) 0x456f54 LDR	X14, [X20, X16]

    (664) 0x456f58 CMP	X14, X6

    (664) 0x456f5c B.EQ	456eb4

    (664) 0x456f60 LDR	X13, [X10, X22]

    (664) 0x456f64 ORN	X3, XZR, X3

    (664) 0x456f68 STR	X3, [X13, X4,LSL #3]

    (664) 0x456f6c ADD	X4, X4, #1

    (664) 0x456f70 STR	X6, [X20, X16]

    (664) 0x456f74 LDR	X16, [X0, #16]

    (664) 0x456f78 TBZ	X16, #63, 456ebc

    (664) 0x456f7c ORN	X13, XZR, X16

    (664) 0x456f80 UBFM	X13, X13, #61, #60

    (664) 0x456f84 LDR	X14, [X20, X13]

    (664) 0x456f88 CMP	X14, X6

    (664) 0x456f8c B.EQ	456edc

    (664) 0x456f90 LDR	X14, [X10, X22]

    (664) 0x456f94 ORN	X16, XZR, X16

    (664) 0x456f98 STR	X16, [X14, X4,LSL #3]

    (664) 0x456f9c ADD	X4, X4, #1

    (664) 0x456fa0 STR	X6, [X20, X13]

    (664) 0x456fa4 B	456edc

    (664) 0x456fa8 ORN	X13, XZR, X3

    (664) 0x456fac UBFM	X16, X13, #61, #60

    (664) 0x456fb0 LDR	X14, [X20, X16]

    (664) 0x456fb4 CMP	X14, X6

    (664) 0x456fb8 B.EQ	456f10

    (664) 0x456fbc LDR	X13, [X10, X22]

    (664) 0x456fc0 ORN	X3, XZR, X3

    (664) 0x456fc4 STR	X3, [X13, X4,LSL #3]

    (664) 0x456fc8 ADD	X4, X4, #1

    (664) 0x456fcc STR	X6, [X20, X16]

    (664) 0x456fd0 B	456f10

  (663) 0x456fd4 ORN	X13, XZR, X16

  (663) 0x456fd8 UBFM	X13, X13, #61, #60

  (663) 0x456fdc LDR	X14, [X20, X13]

  (663) 0x456fe0 CMP	X14, X6

  (663) 0x456fe4 B.EQ	456df8

  (663) 0x456fe8 LDR	X14, [X10, X22]

  (663) 0x456fec ORN	X16, XZR, X16

  (663) 0x456ff0 STR	X16, [X14, X4,LSL #3]

  (663) 0x456ff4 ADD	X4, X4, #1

  (663) 0x456ff8 STR	X6, [X20, X13]

  (663) 0x456ffc B	456df8

  (663) 0x457000 ORN	X13, XZR, X3

  (663) 0x457004 UBFM	X16, X13, #61, #60

  (663) 0x457008 LDR	X14, [X20, X16]

  (663) 0x45700c CMP	X14, X6

  (663) 0x457010 B.EQ	456dcc

  (663) 0x457014 LDR	X13, [X10, X22]

  (663) 0x457018 ORN	X3, XZR, X3

  (663) 0x45701c STR	X3, [X13, X4,LSL #3]

  (663) 0x457020 ADD	X4, X4, #1

  (663) 0x457024 STR	X6, [X20, X16]

  (663) 0x457028 B	456dcc

  (663) 0x45702c ORN	X13, XZR, X16

  (663) 0x457030 UBFM	X13, X13, #61, #60

  (663) 0x457034 LDR	X14, [X20, X13]

  (663) 0x457038 CMP	X14, X6

  (663) 0x45703c B.EQ	456da0

  (663) 0x457040 LDR	X14, [X10, X22]

  (663) 0x457044 ORN	X16, XZR, X16

  (663) 0x457048 STR	X16, [X14, X4,LSL #3]

  (663) 0x45704c ADD	X4, X4, #1

  (663) 0x457050 STR	X6, [X20, X13]

  (663) 0x457054 B	456da0

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1072 - 1125

--------------------------------------------------------------------------------

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
►98.16+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.84+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.38
CQA cycles if no scalar integer	3.38
CQA cycles if FP arith vectorized	3.38
CQA cycles if fully vectorized	0.84
Front-end cycles	3.38
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	3.25
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.17
P11 cycles	2.83
P12 cycles	3.00
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	27.00
Nb loads	NA
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.38
CQA cycles if no scalar integer	3.38
CQA cycles if FP arith vectorized	3.38
CQA cycles if fully vectorized	0.84
Front-end cycles	3.38
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	3.25
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.17
P11 cycles	2.83
P12 cycles	3.00
P13 cycles	0.50
P14 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	27.00
Nb loads	NA
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1125.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1104,1122.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.38 to 0.84 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	31
nb uops	27
loop length	124
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50
cycles	2.50	2.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	3.25
Overall L1	3.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.38 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 456960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X15, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN X0, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [X12, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X5, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X13, [X12, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456ce8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x103c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X6, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4569a4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X24, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORN X6, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [X11, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [X11, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 456e20 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 456d14 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1068>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 456960 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.38 to 0.84 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	31
nb uops	27
loop length	124
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50
cycles	2.50	2.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	3.25
Overall L1	3.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.38 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 456960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X15, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN X0, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [X12, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X5, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X13, [X12, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456ce8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x103c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X6, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4569a4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X24, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORN X6, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [X11, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X15, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [X11, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 456e20 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 456d14 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1068>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 456960 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code