OV - exec - Loop 665

	Loop Id: 665	Module: exec	Source: par_multi_interp.c:1075-1099	Coverage: 0.55%

0x456998 ADD	X3, X3, #1

0x45699c CMP	X3, X13

0x4569a0 B.GE	456ce0

0x4569a4 LDR	X24, [X27, X3,LSL #3]

0x4569a8 UBFM	X1, X24, #61, #60

0x4569ac LDR	X16, [X25, X1]

0x4569b0 CMP	X16, X7

0x4569b4 B.NE	456998

0x4569b8 LDR	X21, [SP, #152]

0x4569bc ADD	X16, X1, #8

0x4569c0 LDR	X13, [X23, X16]

0x4569c4 LDR	X5, [X21, X1]

0x4569c8 ADD	X13, X5, X13

0x4569cc CMP	X5, X13

0x4569d0 B.GE	456b58

0x4569d4 LDR	X24, [SP, #160]

0x4569d8 UBFM	X21, X5, #61, #60

0x4569dc STR	X21, [SP, #144]

0x4569e0 LDUR	X24, [X24, #504]

0x4569e4 ADD	X13, X24, X13,LSL #3

0x4569e8 ADD	X5, X24, X5,LSL #3

0x4569ec SUB	X21, X13, X5

0x4569f0 STR	X13, [SP, #96]

0x4569f4 SUB	X21, X21, #8

0x4569f8 UBFM	X21, X21, #3, #63

0x4569fc ADD	X21, X21, #1

0x456a00 ANDS	X21, X21, #0x3

0x456a04 B.EQ	456aa0

0x456a08 CMP	X21, #1

0x456a0c B.EQ	456a6c

0x456a10 CMP	X21, #2

0x456a14 B.EQ	456a44

0x456a18 LDR	X13, [SP, #144]

0x456a1c LDR	X24, [X24, X13]

0x456a20 UBFM	X21, X24, #61, #60

0x456a24 LDR	X13, [X20, X21]

0x456a28 CMP	X13, X0

0x456a2c B.EQ	456a40

0x456a30 LDR	X13, [X10, X22]

0x456a34 STR	X24, [X13, X4,LSL #3]

0x456a38 ADD	X4, X4, #1

0x456a3c STR	X0, [X20, X21]

0x456a40 ADD	X5, X5, #8

0x456a44 LDR	X24, [X5]

0x456a48 UBFM	X21, X24, #61, #60

0x456a4c LDR	X13, [X20, X21]

0x456a50 CMP	X13, X0

0x456a54 B.EQ	456a68

0x456a58 LDR	X13, [X10, X22]

0x456a5c STR	X24, [X13, X4,LSL #3]

0x456a60 ADD	X4, X4, #1

0x456a64 STR	X0, [X20, X21]

0x456a68 ADD	X5, X5, #8

0x456a6c LDR	X24, [X5]

0x456a70 UBFM	X21, X24, #61, #60

0x456a74 LDR	X13, [X20, X21]

0x456a78 CMP	X13, X0

0x456a7c B.EQ	456a90

0x456a80 LDR	X13, [X10, X22]

0x456a84 STR	X24, [X13, X4,LSL #3]

0x456a88 ADD	X4, X4, #1

0x456a8c STR	X0, [X20, X21]

0x456a90 LDR	X13, [SP, #96]

0x456a94 ADD	X5, X5, #8

0x456a98 CMP	X13, X5

0x456a9c B.EQ	456b58

0x456aa0 ORR	X24, XZR, X2

0x456aa4 STR	X1, [SP, #96]

0x456aa8 STR	X19, [SP, #144]

  (667) 0x456aac LDR	X21, [X5]

  (667) 0x456ab0 ADD	X2, X5, #8

  (667) 0x456ab4 UBFM	X19, X21, #61, #60

  (667) 0x456ab8 LDR	X1, [X20, X19]

  (667) 0x456abc CMP	X1, X0

  (667) 0x456ac0 B.EQ	456ad4

  (667) 0x456ac4 LDR	X1, [X10, X22]

  (667) 0x456ac8 STR	X21, [X1, X4,LSL #3]

  (667) 0x456acc ADD	X4, X4, #1

  (667) 0x456ad0 STR	X0, [X20, X19]

  (667) 0x456ad4 LDR	X19, [X5, #8]

  (667) 0x456ad8 UBFM	X5, X19, #61, #60

  (667) 0x456adc LDR	X21, [X20, X5]

  (667) 0x456ae0 CMP	X21, X0

  (667) 0x456ae4 B.EQ	456af8

  (667) 0x456ae8 LDR	X1, [X10, X22]

  (667) 0x456aec STR	X19, [X1, X4,LSL #3]

  (667) 0x456af0 ADD	X4, X4, #1

  (667) 0x456af4 STR	X0, [X20, X5]

  (667) 0x456af8 LDR	X21, [X2, #8]

  (667) 0x456afc ADD	X5, X2, #24

  (667) 0x456b00 UBFM	X19, X21, #61, #60

  (667) 0x456b04 LDR	X1, [X20, X19]

  (667) 0x456b08 CMP	X1, X0

  (667) 0x456b0c B.EQ	456b20

  (667) 0x456b10 LDR	X1, [X10, X22]

  (667) 0x456b14 STR	X21, [X1, X4,LSL #3]

  (667) 0x456b18 ADD	X4, X4, #1

  (667) 0x456b1c STR	X0, [X20, X19]

  (667) 0x456b20 LDR	X19, [X2, #16]

  (667) 0x456b24 UBFM	X2, X19, #61, #60

  (667) 0x456b28 LDR	X21, [X20, X2]

  (667) 0x456b2c CMP	X21, X0

  (667) 0x456b30 B.EQ	456b44

  (667) 0x456b34 LDR	X1, [X10, X22]

  (667) 0x456b38 STR	X19, [X1, X4,LSL #3]

  (667) 0x456b3c ADD	X4, X4, #1

  (667) 0x456b40 STR	X0, [X20, X2]

  (667) 0x456b44 CMP	X13, X5

  (667) 0x456b48 B.NE	456aac

0x456b4c LDR	X1, [SP, #96]

0x456b50 ORR	X2, XZR, X24

0x456b54 LDR	X19, [SP, #144]

0x456b58 LDR	X13, [SP, #136]

0x456b5c LDR	X16, [X18, X16]

0x456b60 LDR	X24, [X13, X1]

0x456b64 ADD	X5, X24, X16

0x456b68 CMP	X24, X5

0x456b6c B.GE	456ccc

0x456b70 LDR	X1, [SP, #168]

0x456b74 UBFM	X21, X24, #61, #60

0x456b78 LDUR	X16, [X1, #504]

0x456b7c ADD	X1, X16, X24,LSL #3

0x456b80 ADD	X5, X16, X5,LSL #3

0x456b84 SUB	X13, X5, X1

0x456b88 SUB	X24, X13, #8

0x456b8c UBFM	X13, X24, #3, #63

0x456b90 ADD	X24, X13, #1

0x456b94 ANDS	X13, X24, #0x3

0x456b98 B.EQ	456c2c

0x456b9c CMP	X13, #1

0x456ba0 B.EQ	456bfc

0x456ba4 CMP	X13, #2

0x456ba8 B.EQ	456bd4

0x456bac LDR	X16, [X16, X21]

0x456bb0 UBFM	X24, X16, #61, #60

0x456bb4 LDR	X21, [X19, X24]

0x456bb8 CMP	X21, X0

0x456bbc B.EQ	456bd0

0x456bc0 LDR	X13, [X8, X22]

0x456bc4 STR	X16, [X13, X2,LSL #3]

0x456bc8 ADD	X2, X2, #1

0x456bcc STR	X0, [X19, X24]

0x456bd0 ADD	X1, X1, #8

0x456bd4 LDR	X16, [X1]

0x456bd8 UBFM	X24, X16, #61, #60

0x456bdc LDR	X21, [X19, X24]

0x456be0 CMP	X21, X0

0x456be4 B.EQ	456bf8

0x456be8 LDR	X13, [X8, X22]

0x456bec STR	X16, [X13, X2,LSL #3]

0x456bf0 ADD	X2, X2, #1

0x456bf4 STR	X0, [X19, X24]

0x456bf8 ADD	X1, X1, #8

0x456bfc LDR	X16, [X1]

0x456c00 UBFM	X24, X16, #61, #60

0x456c04 LDR	X21, [X19, X24]

0x456c08 CMP	X21, X0

0x456c0c B.EQ	456c20

0x456c10 LDR	X13, [X8, X22]

0x456c14 STR	X16, [X13, X2,LSL #3]

0x456c18 ADD	X2, X2, #1

0x456c1c STR	X0, [X19, X24]

0x456c20 ADD	X1, X1, #8

0x456c24 CMP	X1, X5

0x456c28 B.EQ	456ccc

  (666) 0x456c2c LDR	X21, [X1]

  (666) 0x456c30 ADD	X13, X1, #8

  (666) 0x456c34 UBFM	X16, X21, #61, #60

  (666) 0x456c38 LDR	X24, [X19, X16]

  (666) 0x456c3c CMP	X24, X0

  (666) 0x456c40 B.EQ	456c54

  (666) 0x456c44 LDR	X24, [X8, X22]

  (666) 0x456c48 STR	X21, [X24, X2,LSL #3]

  (666) 0x456c4c ADD	X2, X2, #1

  (666) 0x456c50 STR	X0, [X19, X16]

  (666) 0x456c54 LDR	X16, [X1, #8]

  (666) 0x456c58 UBFM	X1, X16, #61, #60

  (666) 0x456c5c LDR	X21, [X19, X1]

  (666) 0x456c60 CMP	X21, X0

  (666) 0x456c64 B.EQ	456c78

  (666) 0x456c68 LDR	X24, [X8, X22]

  (666) 0x456c6c STR	X16, [X24, X2,LSL #3]

  (666) 0x456c70 ADD	X2, X2, #1

  (666) 0x456c74 STR	X0, [X19, X1]

  (666) 0x456c78 LDR	X21, [X13, #8]

  (666) 0x456c7c ADD	X1, X13, #24

  (666) 0x456c80 UBFM	X16, X21, #61, #60

  (666) 0x456c84 LDR	X24, [X19, X16]

  (666) 0x456c88 CMP	X24, X0

  (666) 0x456c8c B.EQ	456ca0

  (666) 0x456c90 LDR	X24, [X8, X22]

  (666) 0x456c94 STR	X21, [X24, X2,LSL #3]

  (666) 0x456c98 ADD	X2, X2, #1

  (666) 0x456c9c STR	X0, [X19, X16]

  (666) 0x456ca0 LDR	X16, [X13, #16]

  (666) 0x456ca4 UBFM	X13, X16, #61, #60

  (666) 0x456ca8 LDR	X21, [X19, X13]

  (666) 0x456cac CMP	X21, X0

  (666) 0x456cb0 B.EQ	456cc4

  (666) 0x456cb4 LDR	X24, [X8, X22]

  (666) 0x456cb8 STR	X16, [X24, X2,LSL #3]

  (666) 0x456cbc ADD	X2, X2, #1

  (666) 0x456cc0 STR	X0, [X19, X13]

  (666) 0x456cc4 CMP	X1, X5

  (666) 0x456cc8 B.NE	456c2c

0x456ccc LDR	X13, [X6]

0x456cd0 ADD	X3, X3, #1

0x456cd4 CMP	X3, X13

0x456cd8 B.LT	4569a4

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1075 - 1099

--------------------------------------------------------------------------------

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
►98.44+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.56+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1075-1075,par_multi_interp.c:1078-1088,par_multi_interp.c:1091-1099
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	4.25
Front-end cycles	16.13
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	14.75
P3 cycles	14.75
P4 cycles	14.75
P5 cycles	14.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	17.00
P11 cycles	17.00
P12 cycles	17.00
P13 cycles	8.00
P14 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	129.00
Nb loads	NA
Nb stores	16.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1075-1075,par_multi_interp.c:1078-1088,par_multi_interp.c:1091-1099
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	4.25
Front-end cycles	16.13
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	14.75
P3 cycles	14.75
P4 cycles	14.75
P5 cycles	14.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	17.00
P11 cycles	17.00
P12 cycles	17.00
P13 cycles	8.00
P14 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	129.00
Nb loads	NA
Nb stores	16.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1075-1099
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075-1099.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075,1078-1088,1091-1099.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 65026 paths individually, rerun with max-paths=65026
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 65026 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 17.00 to 4.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	129
nb uops	129
loop length	516
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.13 cycles
front end	16.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.50	9.50	14.75	14.75	14.75	14.75	0.00	0.00	0.00	0.00	17.00	17.00	17.00	8.00	8.00
cycles	9.50	9.50	14.75	14.75	14.75	14.75	0.00	0.00	0.00	0.00	17.00	17.00	17.00	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.13
Dispatch	17.00
Overall L1	17.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4569a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456ce0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1034>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X27, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X25, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 456998 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X23, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456b58 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X24, [X24, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X24, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X5, X24, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X21, X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X21, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X21, X21, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X21, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X21, X21, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 456aa0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456a6c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456a44 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X24, X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456a40 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456a68 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456a90 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xde4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456b58 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X19, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X19, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X18, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X13, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X24, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X24, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456ccc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDUR X16, [X1, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X16, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X5, X16, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X13, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X24, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X13, X24, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X24, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X13, X24, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 456c2c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456bfc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456bd4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X16, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456bd0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456bf8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456c20 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456ccc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 4569a4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1075-1099
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 65026 paths individually, rerun with max-paths=65026
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	129
nb uops	129
loop length	516
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.13 cycles
front end	16.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.50	9.50	14.75	14.75	14.75	14.75	0.00	0.00	0.00	0.00	17.00	17.00	17.00	8.00	8.00
cycles	9.50	9.50	14.75	14.75	14.75	14.75	0.00	0.00	0.00	0.00	17.00	17.00	17.00	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.13
Dispatch	17.00
Overall L1	17.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4569a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456ce0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1034>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X27, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X25, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 456998 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X23, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456b58 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X24, [X24, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X24, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X5, X24, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X21, X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X21, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X21, X21, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X21, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X21, X21, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 456aa0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456a6c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456a44 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X24, X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456a40 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456a68 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X20, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456a90 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xde4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X10, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X20, X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456b58 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X19, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X19, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X18, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X13, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X24, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X24, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456ccc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDUR X16, [X1, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X16, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X5, X16, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X13, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X24, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X13, X24, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X24, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ANDS X13, X24, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 456c2c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456bfc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456bd4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X16, X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456bd0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456bf8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X19, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456c20 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xf74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X8, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X19, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456ccc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 4569a4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code