OV - exec - Loop 670

	Loop Id: 670	Module: exec	Source: par_multi_interp.c:939-999 [...]	Coverage: 0.04%

0x455e80 LDR	X14, [SP, #104]

0x455e84 LDR	X0, [X14, X15,LSL #3]

0x455e88 UBFM	X10, X0, #61, #60

0x455e8c ADD	X1, X10, #8

0x455e90 STR	X6, [X18, X10]

0x455e94 ADD	X4, X12, X1

0x455e98 STR	X5, [X16, X10]

0x455e9c LDR	X3, [X12, X10]

0x455ea0 LDR	X8, [X12, X1]

0x455ea4 CMP	X3, X8

0x455ea8 B.GE	456214

0x455eac ORR	X28, XZR, X24

0x455eb0 STR	X9, [SP, #128]

0x455eb4 ORR	X9, XZR, X4

0x455eb8 B	455ec8

  (673) 0x455ebc ADD	X3, X3, #1

  (673) 0x455ec0 CMP	X3, X8

  (673) 0x455ec4 B.GE	45620c

  (673) 0x455ec8 LDR	X24, [X27, X3,LSL #3]

  (673) 0x455ecc UBFM	X2, X24, #61, #60

  (673) 0x455ed0 LDR	X17, [X25, X2]

  (673) 0x455ed4 STR	X2, [SP, #96]

  (673) 0x455ed8 CMP	X17, X7

  (673) 0x455edc B.NE	455ebc

  (673) 0x455ee0 ADD	X17, X2, #8

  (673) 0x455ee4 LDR	X8, [X18, X2]

  (673) 0x455ee8 LDR	X14, [X23, X17]

  (673) 0x455eec ADD	X4, X8, X14

  (673) 0x455ef0 CMP	X8, X4

  (673) 0x455ef4 B.GE	456070

  (673) 0x455ef8 LDR	X24, [SP, #144]

  (673) 0x455efc UBFM	X2, X8, #61, #60

  (673) 0x455f00 LDUR	X24, [X24, #504]

  (673) 0x455f04 ADD	X14, X24, X4,LSL #3

  (673) 0x455f08 ADD	X4, X24, X8,LSL #3

  (673) 0x455f0c SUB	X8, X14, X4

  (673) 0x455f10 SUB	X8, X8, #8

  (673) 0x455f14 UBFM	X8, X8, #3, #63

  (673) 0x455f18 ADD	X8, X8, #1

  (673) 0x455f1c ANDS	X8, X8, #0x3

  (673) 0x455f20 B.EQ	455fc0

  (673) 0x455f24 CMP	X8, #1

  (673) 0x455f28 B.EQ	455f8c

  (673) 0x455f2c CMP	X8, #2

  (673) 0x455f30 B.EQ	455f60

  (673) 0x455f34 LDR	X24, [X24, X2]

  (673) 0x455f38 UBFM	X2, X24, #61, #60

  (673) 0x455f3c LDR	X8, [X20, X2]

  (673) 0x455f40 CMP	X0, X8

  (673) 0x455f44 B.EQ	455f5c

  (673) 0x455f48 LDR	X24, [X23, X1]

  (673) 0x455f4c ADD	X6, X6, #1

  (673) 0x455f50 ADD	X8, X24, #1

  (673) 0x455f54 STR	X8, [X23, X1]

  (673) 0x455f58 STR	X0, [X20, X2]

  (673) 0x455f5c ADD	X4, X4, #8

  (673) 0x455f60 LDR	X2, [X4]

  (673) 0x455f64 UBFM	X8, X2, #61, #60

  (673) 0x455f68 LDR	X24, [X20, X8]

  (673) 0x455f6c CMP	X0, X24

  (673) 0x455f70 B.EQ	455f88

  (673) 0x455f74 LDR	X2, [X23, X1]

  (673) 0x455f78 ADD	X6, X6, #1

  (673) 0x455f7c ADD	X24, X2, #1

  (673) 0x455f80 STR	X24, [X23, X1]

  (673) 0x455f84 STR	X0, [X20, X8]

  (673) 0x455f88 ADD	X4, X4, #8

  (673) 0x455f8c LDR	X8, [X4]

  (673) 0x455f90 UBFM	X2, X8, #61, #60

  (673) 0x455f94 LDR	X24, [X20, X2]

  (673) 0x455f98 CMP	X0, X24

  (673) 0x455f9c B.EQ	455fb4

  (673) 0x455fa0 LDR	X8, [X23, X1]

  (673) 0x455fa4 ADD	X6, X6, #1

  (673) 0x455fa8 ADD	X24, X8, #1

  (673) 0x455fac STR	X24, [X23, X1]

  (673) 0x455fb0 STR	X0, [X20, X2]

  (673) 0x455fb4 ADD	X4, X4, #8

  (673) 0x455fb8 CMP	X14, X4

  (673) 0x455fbc B.EQ	456070

    (675) 0x455fc0 LDR	X2, [X4]

    (675) 0x455fc4 ADD	X8, X4, #8

    (675) 0x455fc8 UBFM	X2, X2, #61, #60

    (675) 0x455fcc LDR	X24, [X20, X2]

    (675) 0x455fd0 CMP	X0, X24

    (675) 0x455fd4 B.EQ	455fec

    (675) 0x455fd8 LDR	X24, [X23, X1]

    (675) 0x455fdc ADD	X6, X6, #1

    (675) 0x455fe0 ADD	X24, X24, #1

    (675) 0x455fe4 STR	X24, [X23, X1]

    (675) 0x455fe8 STR	X0, [X20, X2]

    (675) 0x455fec LDR	X4, [X4, #8]

    (675) 0x455ff0 UBFM	X2, X4, #61, #60

    (675) 0x455ff4 LDR	X24, [X20, X2]

    (675) 0x455ff8 CMP	X0, X24

    (675) 0x455ffc B.EQ	456014

    (675) 0x456000 LDR	X4, [X23, X1]

    (675) 0x456004 ADD	X6, X6, #1

    (675) 0x456008 ADD	X24, X4, #1

    (675) 0x45600c STR	X24, [X23, X1]

    (675) 0x456010 STR	X0, [X20, X2]

    (675) 0x456014 LDR	X2, [X8, #8]

    (675) 0x456018 ADD	X4, X8, #24

    (675) 0x45601c UBFM	X2, X2, #61, #60

    (675) 0x456020 LDR	X24, [X20, X2]

    (675) 0x456024 CMP	X0, X24

    (675) 0x456028 B.EQ	456040

    (675) 0x45602c LDR	X24, [X23, X1]

    (675) 0x456030 ADD	X6, X6, #1

    (675) 0x456034 ADD	X24, X24, #1

    (675) 0x456038 STR	X24, [X23, X1]

    (675) 0x45603c STR	X0, [X20, X2]

    (675) 0x456040 LDR	X8, [X8, #16]

    (675) 0x456044 UBFM	X2, X8, #61, #60

    (675) 0x456048 LDR	X24, [X20, X2]

    (675) 0x45604c CMP	X0, X24

    (675) 0x456050 B.EQ	456068

    (675) 0x456054 LDR	X8, [X23, X1]

    (675) 0x456058 ADD	X6, X6, #1

    (675) 0x45605c ADD	X24, X8, #1

    (675) 0x456060 STR	X24, [X23, X1]

    (675) 0x456064 STR	X0, [X20, X2]

    (675) 0x456068 CMP	X14, X4

    (675) 0x45606c B.NE	455fc0

  (673) 0x456070 LDR	X14, [SP, #96]

  (673) 0x456074 LDR	X17, [X21, X17]

  (673) 0x456078 LDR	X4, [X16, X14]

  (673) 0x45607c ADD	X2, X4, X17

  (673) 0x456080 CMP	X4, X2

  (673) 0x456084 B.GE	4561fc

  (673) 0x456088 LDUR	X17, [X30, #504]

  (673) 0x45608c UBFM	X24, X4, #61, #60

  (673) 0x456090 ADD	X8, X17, X2,LSL #3

  (673) 0x456094 ADD	X2, X17, X4,LSL #3

  (673) 0x456098 SUB	X14, X8, X2

  (673) 0x45609c SUB	X4, X14, #8

  (673) 0x4560a0 UBFM	X14, X4, #3, #63

  (673) 0x4560a4 ADD	X4, X14, #1

  (673) 0x4560a8 ANDS	X14, X4, #0x3

  (673) 0x4560ac B.EQ	45614c

  (673) 0x4560b0 CMP	X14, #1

  (673) 0x4560b4 B.EQ	456118

  (673) 0x4560b8 CMP	X14, #2

  (673) 0x4560bc B.EQ	4560ec

  (673) 0x4560c0 LDR	X24, [X17, X24]

  (673) 0x4560c4 UBFM	X17, X24, #61, #60

  (673) 0x4560c8 LDR	X4, [X19, X17]

  (673) 0x4560cc CMP	X0, X4

  (673) 0x4560d0 B.EQ	4560e8

  (673) 0x4560d4 LDR	X14, [X21, X1]

  (673) 0x4560d8 ADD	X5, X5, #1

  (673) 0x4560dc ADD	X24, X14, #1

  (673) 0x4560e0 STR	X24, [X21, X1]

  (673) 0x4560e4 STR	X0, [X19, X17]

  (673) 0x4560e8 ADD	X2, X2, #8

  (673) 0x4560ec LDR	X17, [X2]

  (673) 0x4560f0 UBFM	X4, X17, #61, #60

  (673) 0x4560f4 LDR	X14, [X19, X4]

  (673) 0x4560f8 CMP	X0, X14

  (673) 0x4560fc B.EQ	456114

  (673) 0x456100 LDR	X24, [X21, X1]

  (673) 0x456104 ADD	X5, X5, #1

  (673) 0x456108 ADD	X17, X24, #1

  (673) 0x45610c STR	X17, [X21, X1]

  (673) 0x456110 STR	X0, [X19, X4]

  (673) 0x456114 ADD	X2, X2, #8

  (673) 0x456118 LDR	X4, [X2]

  (673) 0x45611c UBFM	X24, X4, #61, #60

  (673) 0x456120 LDR	X14, [X19, X24]

  (673) 0x456124 CMP	X0, X14

  (673) 0x456128 B.EQ	456140

  (673) 0x45612c LDR	X17, [X21, X1]

  (673) 0x456130 ADD	X5, X5, #1

  (673) 0x456134 ADD	X4, X17, #1

  (673) 0x456138 STR	X4, [X21, X1]

  (673) 0x45613c STR	X0, [X19, X24]

  (673) 0x456140 ADD	X2, X2, #8

  (673) 0x456144 CMP	X2, X8

  (673) 0x456148 B.EQ	4561fc

    (674) 0x45614c LDR	X14, [X2]

    (674) 0x456150 ADD	X24, X2, #8

    (674) 0x456154 UBFM	X4, X14, #61, #60

    (674) 0x456158 LDR	X17, [X19, X4]

    (674) 0x45615c CMP	X0, X17

    (674) 0x456160 B.EQ	456178

    (674) 0x456164 LDR	X14, [X21, X1]

    (674) 0x456168 ADD	X5, X5, #1

    (674) 0x45616c ADD	X17, X14, #1

    (674) 0x456170 STR	X17, [X21, X1]

    (674) 0x456174 STR	X0, [X19, X4]

    (674) 0x456178 LDR	X2, [X2, #8]

    (674) 0x45617c UBFM	X14, X2, #61, #60

    (674) 0x456180 LDR	X4, [X19, X14]

    (674) 0x456184 CMP	X0, X4

    (674) 0x456188 B.EQ	4561a0

    (674) 0x45618c LDR	X17, [X21, X1]

    (674) 0x456190 ADD	X5, X5, #1

    (674) 0x456194 ADD	X2, X17, #1

    (674) 0x456198 STR	X2, [X21, X1]

    (674) 0x45619c STR	X0, [X19, X14]

    (674) 0x4561a0 LDR	X14, [X24, #8]

    (674) 0x4561a4 ADD	X2, X24, #24

    (674) 0x4561a8 UBFM	X4, X14, #61, #60

    (674) 0x4561ac LDR	X17, [X19, X4]

    (674) 0x4561b0 CMP	X0, X17

    (674) 0x4561b4 B.EQ	4561cc

    (674) 0x4561b8 LDR	X14, [X21, X1]

    (674) 0x4561bc ADD	X5, X5, #1

    (674) 0x4561c0 ADD	X17, X14, #1

    (674) 0x4561c4 STR	X17, [X21, X1]

    (674) 0x4561c8 STR	X0, [X19, X4]

    (674) 0x4561cc LDR	X24, [X24, #16]

    (674) 0x4561d0 UBFM	X4, X24, #61, #60

    (674) 0x4561d4 LDR	X14, [X19, X4]

    (674) 0x4561d8 CMP	X0, X14

    (674) 0x4561dc B.EQ	4561f4

    (674) 0x4561e0 LDR	X17, [X21, X1]

    (674) 0x4561e4 ADD	X5, X5, #1

    (674) 0x4561e8 ADD	X24, X17, #1

    (674) 0x4561ec STR	X24, [X21, X1]

    (674) 0x4561f0 STR	X0, [X19, X4]

    (674) 0x4561f4 CMP	X2, X8

    (674) 0x4561f8 B.NE	45614c

  (673) 0x4561fc LDR	X8, [X9]

  (673) 0x456200 ADD	X3, X3, #1

  (673) 0x456204 CMP	X3, X8

  (673) 0x456208 B.LT	455ec8

0x45620c LDR	X9, [SP, #128]

0x456210 ORR	X24, XZR, X28

0x456214 LDR	X3, [X11, X10]

0x456218 ADD	X10, X11, X1

0x45621c LDR	X4, [X11, X1]

0x456220 CMP	X3, X4

0x456224 B.GE	456360

0x456228 LDP	X14, X28, [SP, #112]

0x45622c ORR	X2, XZR, X10

0x456230 B	456240

  (671) 0x456234 ADD	X3, X3, #1

  (671) 0x456238 CMP	X3, X4

  (671) 0x45623c B.GE	456360

  (671) 0x456240 LDR	X17, [X26, X3,LSL #3]

  (671) 0x456244 UBFM	X8, X17, #61, #60

  (671) 0x456248 LDR	X10, [X24, X8]

  (671) 0x45624c CMP	X10, X7

  (671) 0x456250 B.NE	456234

  (671) 0x456254 ADD	X17, X14, X8

  (671) 0x456258 LDR	X8, [X13, X8]

  (671) 0x45625c LDR	X10, [X17, #8]

  (671) 0x456260 ADD	X10, X8, X10

  (671) 0x456264 CMP	X8, X10

  (671) 0x456268 B.GE	456234

  (671) 0x45626c LDR	X17, [X28, X22]

  (671) 0x456270 UBFM	X4, X8, #61, #60

  (671) 0x456274 STR	X4, [SP, #96]

  (671) 0x456278 ADD	X10, X17, X10,LSL #3

  (671) 0x45627c ADD	X4, X17, X8,LSL #3

  (671) 0x456280 SUB	X8, X10, X4

  (671) 0x456284 SUB	X8, X8, #8

  (671) 0x456288 UBFM	X8, X8, #3, #63

  (671) 0x45628c ADD	X8, X8, #1

  (671) 0x456290 ANDS	X8, X8, #0x3

  (671) 0x456294 B.EQ	45659c

  (671) 0x456298 CMP	X8, #1

  (671) 0x45629c B.EQ	45630c

  (671) 0x4562a0 CMP	X8, #2

  (671) 0x4562a4 B.EQ	4562dc

  (671) 0x4562a8 LDR	X8, [SP, #96]

  (671) 0x4562ac LDR	X17, [X17, X8]

  (671) 0x4562b0 TBNZ	X17, #63, 4566bc

  (671) 0x4562b4 UBFM	X8, X17, #61, #60

  (671) 0x4562b8 LDR	X17, [X19, X8]

  (671) 0x4562bc CMP	X0, X17

  (671) 0x4562c0 B.EQ	4562d8

  (671) 0x4562c4 LDR	X17, [X21, X1]

  (671) 0x4562c8 ADD	X5, X5, #1

  (671) 0x4562cc ADD	X17, X17, #1

  (671) 0x4562d0 STR	X17, [X21, X1]

  (671) 0x4562d4 STR	X0, [X19, X8]

  (671) 0x4562d8 ADD	X4, X4, #8

  (671) 0x4562dc LDR	X8, [X4]

  (671) 0x4562e0 TBNZ	X8, #63, 456690

  (671) 0x4562e4 UBFM	X8, X8, #61, #60

  (671) 0x4562e8 LDR	X17, [X19, X8]

  (671) 0x4562ec CMP	X0, X17

  (671) 0x4562f0 B.EQ	456308

  (671) 0x4562f4 LDR	X17, [X21, X1]

  (671) 0x4562f8 ADD	X5, X5, #1

  (671) 0x4562fc ADD	X17, X17, #1

  (671) 0x456300 STR	X17, [X21, X1]

  (671) 0x456304 STR	X0, [X19, X8]

  (671) 0x456308 ADD	X4, X4, #8

  (671) 0x45630c LDR	X8, [X4]

  (671) 0x456310 TBNZ	X8, #63, 456664

  (671) 0x456314 UBFM	X8, X8, #61, #60

  (671) 0x456318 LDR	X17, [X19, X8]

  (671) 0x45631c CMP	X0, X17

  (671) 0x456320 B.EQ	456338

  (671) 0x456324 LDR	X17, [X21, X1]

  (671) 0x456328 ADD	X5, X5, #1

  (671) 0x45632c ADD	X17, X17, #1

  (671) 0x456330 STR	X17, [X21, X1]

  (671) 0x456334 STR	X0, [X19, X8]

  (671) 0x456338 ADD	X4, X4, #8

  (671) 0x45633c CMP	X4, X10

  (671) 0x456340 B.NE	45659c

  (671) 0x456344 LDR	X4, [X2]

  (671) 0x456348 ADD	X3, X3, #1

  (671) 0x45634c CMP	X3, X4

  (671) 0x456350 B.LT	456240

0x456354 HINT	#0

0x456358 HINT	#0

0x45635c HINT	#0

0x456360 ADD	X15, X15, #1

0x456364 CMP	X9, X15

0x456368 B.GT	455e80

    (672) 0x4564e4 UBFM	X8, X8, #61, #60

    (672) 0x4564e8 LDR	X17, [X19, X8]

    (672) 0x4564ec CMP	X0, X17

    (672) 0x4564f0 B.EQ	456508

    (672) 0x4564f4 LDR	X17, [X21, X1]

    (672) 0x4564f8 ADD	X5, X5, #1

    (672) 0x4564fc ADD	X17, X17, #1

    (672) 0x456500 STR	X17, [X21, X1]

    (672) 0x456504 STR	X0, [X19, X8]

    (672) 0x456508 LDR	X8, [X4, #8]

    (672) 0x45650c ADD	X4, X4, #8

    (672) 0x456510 TBNZ	X8, #63, 4565d8

    (672) 0x456514 UBFM	X8, X8, #61, #60

    (672) 0x456518 LDR	X17, [X19, X8]

    (672) 0x45651c CMP	X0, X17

    (672) 0x456520 B.EQ	456538

    (672) 0x456524 LDR	X17, [X21, X1]

    (672) 0x456528 ADD	X5, X5, #1

    (672) 0x45652c ADD	X17, X17, #1

    (672) 0x456530 STR	X17, [X21, X1]

    (672) 0x456534 STR	X0, [X19, X8]

    (672) 0x456538 LDR	X8, [X4, #8]

    (672) 0x45653c TBNZ	X8, #63, 456608

    (672) 0x456540 UBFM	X8, X8, #61, #60

    (672) 0x456544 LDR	X17, [X19, X8]

    (672) 0x456548 CMP	X0, X17

    (672) 0x45654c B.EQ	456564

    (672) 0x456550 LDR	X17, [X21, X1]

    (672) 0x456554 ADD	X5, X5, #1

    (672) 0x456558 ADD	X17, X17, #1

    (672) 0x45655c STR	X17, [X21, X1]

    (672) 0x456560 STR	X0, [X19, X8]

    (672) 0x456564 LDR	X8, [X4, #16]

    (672) 0x456568 TBNZ	X8, #63, 456638

    (672) 0x45656c UBFM	X8, X8, #61, #60

    (672) 0x456570 LDR	X17, [X19, X8]

    (672) 0x456574 CMP	X0, X17

    (672) 0x456578 B.EQ	456590

    (672) 0x45657c LDR	X17, [X21, X1]

    (672) 0x456580 ADD	X5, X5, #1

    (672) 0x456584 ADD	X17, X17, #1

    (672) 0x456588 STR	X17, [X21, X1]

    (672) 0x45658c STR	X0, [X19, X8]

    (672) 0x456590 ADD	X4, X4, #24

    (672) 0x456594 CMP	X4, X10

    (672) 0x456598 B.EQ	456344

    (672) 0x45659c LDR	X8, [X4]

    (672) 0x4565a0 TBZ	X8, #63, 4564e4

    (672) 0x4565a4 ORN	X8, XZR, X8

    (672) 0x4565a8 UBFM	X8, X8, #61, #60

    (672) 0x4565ac LDR	X17, [X20, X8]

    (672) 0x4565b0 CMP	X0, X17

    (672) 0x4565b4 B.EQ	456508

    (672) 0x4565b8 LDR	X17, [X23, X1]

    (672) 0x4565bc ADD	X6, X6, #1

    (672) 0x4565c0 ADD	X4, X4, #8

    (672) 0x4565c4 ADD	X17, X17, #1

    (672) 0x4565c8 STR	X17, [X23, X1]

    (672) 0x4565cc STR	X0, [X20, X8]

    (672) 0x4565d0 LDR	X8, [X4]

    (672) 0x4565d4 TBZ	X8, #63, 456514

    (672) 0x4565d8 ORN	X8, XZR, X8

    (672) 0x4565dc UBFM	X8, X8, #61, #60

    (672) 0x4565e0 LDR	X17, [X20, X8]

    (672) 0x4565e4 CMP	X0, X17

    (672) 0x4565e8 B.EQ	456538

    (672) 0x4565ec LDR	X17, [X23, X1]

    (672) 0x4565f0 ADD	X6, X6, #1

    (672) 0x4565f4 ADD	X17, X17, #1

    (672) 0x4565f8 STR	X17, [X23, X1]

    (672) 0x4565fc STR	X0, [X20, X8]

    (672) 0x456600 LDR	X8, [X4, #8]

    (672) 0x456604 TBZ	X8, #63, 456540

    (672) 0x456608 ORN	X8, XZR, X8

    (672) 0x45660c UBFM	X8, X8, #61, #60

    (672) 0x456610 LDR	X17, [X20, X8]

    (672) 0x456614 CMP	X0, X17

    (672) 0x456618 B.EQ	456564

    (672) 0x45661c LDR	X17, [X23, X1]

    (672) 0x456620 ADD	X6, X6, #1

    (672) 0x456624 ADD	X17, X17, #1

    (672) 0x456628 STR	X17, [X23, X1]

    (672) 0x45662c STR	X0, [X20, X8]

    (672) 0x456630 LDR	X8, [X4, #16]

    (672) 0x456634 TBZ	X8, #63, 45656c

    (672) 0x456638 ORN	X8, XZR, X8

    (672) 0x45663c UBFM	X8, X8, #61, #60

    (672) 0x456640 LDR	X17, [X20, X8]

    (672) 0x456644 CMP	X0, X17

    (672) 0x456648 B.EQ	456590

    (672) 0x45664c LDR	X17, [X23, X1]

    (672) 0x456650 ADD	X6, X6, #1

    (672) 0x456654 ADD	X17, X17, #1

    (672) 0x456658 STR	X17, [X23, X1]

    (672) 0x45665c STR	X0, [X20, X8]

    (672) 0x456660 B	456590

  (671) 0x456664 ORN	X8, XZR, X8

  (671) 0x456668 UBFM	X8, X8, #61, #60

  (671) 0x45666c LDR	X17, [X20, X8]

  (671) 0x456670 CMP	X0, X17

  (671) 0x456674 B.EQ	456338

  (671) 0x456678 LDR	X17, [X23, X1]

  (671) 0x45667c ADD	X6, X6, #1

  (671) 0x456680 ADD	X17, X17, #1

  (671) 0x456684 STR	X17, [X23, X1]

  (671) 0x456688 STR	X0, [X20, X8]

  (671) 0x45668c B	456338

  (671) 0x456690 ORN	X8, XZR, X8

  (671) 0x456694 UBFM	X8, X8, #61, #60

  (671) 0x456698 LDR	X17, [X20, X8]

  (671) 0x45669c CMP	X0, X17

  (671) 0x4566a0 B.EQ	456308

  (671) 0x4566a4 LDR	X17, [X23, X1]

  (671) 0x4566a8 ADD	X6, X6, #1

  (671) 0x4566ac ADD	X17, X17, #1

  (671) 0x4566b0 STR	X17, [X23, X1]

  (671) 0x4566b4 STR	X0, [X20, X8]

  (671) 0x4566b8 B	456308

  (671) 0x4566bc ORN	X8, XZR, X17

  (671) 0x4566c0 UBFM	X8, X8, #61, #60

  (671) 0x4566c4 LDR	X17, [X20, X8]

  (671) 0x4566c8 CMP	X0, X17

  (671) 0x4566cc B.EQ	4562d8

  (671) 0x4566d0 LDR	X17, [X23, X1]

  (671) 0x4566d4 ADD	X6, X6, #1

  (671) 0x4566d8 ADD	X17, X17, #1

  (671) 0x4566dc STR	X17, [X23, X1]

  (671) 0x4566e0 STR	X0, [X20, X8]

  (671) 0x4566e4 B	4562d8

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 939 - 999

--------------------------------------------------------------------------------

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

Coverage (%)	Name	Source Location	Module
►98.16+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.84+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P10,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	3.83
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	0.96
Front-end cycles	3.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.83
P11 cycles	3.50
P12 cycles	3.67
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	28.00
Nb loads	NA
Nb stores	3.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P10,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	3.83
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	0.96
Front-end cycles	3.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.83
P11 cycles	3.50
P12 cycles	3.67
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	28.00
Nb loads	NA
Nb stores	3.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-970,976-999.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 0.96 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	31
nb uops	28
loop length	124
used w registers	0
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	2.50	2.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	3.83
Overall L1	3.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 455e80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X14, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X10, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [X18, X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X5, [X16, X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X12, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [X12, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456214 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x568>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X9, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 455ec8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X3, [X11, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X10, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X11, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456360 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x6b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X2, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 456240 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x594>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 455e80 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 0.96 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	31
nb uops	28
loop length	124
used w registers	0
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	2.50	2.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	3.83
Overall L1	3.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 455e80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X14, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X10, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [X18, X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X5, [X16, X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X12, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [X12, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456214 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x568>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X9, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 455ec8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X3, [X11, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X10, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X11, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 456360 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x6b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X2, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 456240 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x594>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 455e80 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code