OV - exec - Loop 698

	Loop Id: 698	Module: exec	Source: par_multi_interp.c:1774-1876	Coverage: 0.16%

0x4599e0 LDR	X5, [SP, #128]

0x4599e4 LDR	X0, [SP, #216]

0x4599e8 LDR	X1, [SP, #208]

0x4599ec LDR	X3, [X0, X5,LSL #3]

0x4599f0 UBFM	X4, X3, #61, #60

0x4599f4 ADD	X8, X4, #8

0x4599f8 LDR	X14, [X1, X4]

0x4599fc LDR	X13, [X16, X8]

0x459a00 LDR	X0, [X16, X4]

0x459a04 ADD	X5, X14, X13

0x459a08 SUB	X5, X5, X0

0x459a0c CMP	X14, X5

0x459a10 B.GE	459bec

0x459a14 LDR	X13, [SP, #136]

0x459a18 LDR	X1, [SP, #288]

0x459a1c LDR	X1, [X1, X13]

0x459a20 SUB	X13, X0, X14

0x459a24 ADD	X13, X13, X5

0x459a28 SUB	X5, X13, X0

0x459a2c ANDS	X5, X5, #0x7

0x459a30 STR	X1, [SP, #144]

0x459a34 SUB	X1, XZR, X0,LSL #3

0x459a38 ADD	X1, X1, X14,LSL #3

0x459a3c LDR	X14, [SP, #144]

0x459a40 ADD	X1, X14, X1

0x459a44 B.EQ	45aa64

0x459a48 CMP	X5, #1

0x459a4c B.EQ	459b08

0x459a50 CMP	X5, #2

0x459a54 B.EQ	459af0

0x459a58 CMP	X5, #3

0x459a5c B.EQ	459ad8

0x459a60 CMP	X5, #4

0x459a64 B.EQ	459ac0

0x459a68 CMP	X5, #5

0x459a6c B.EQ	459aa8

0x459a70 CMP	X5, #6

0x459a74 B.EQ	459a90

0x459a78 LDR	X5, [X1, X0,LSL #3]

0x459a7c LDR	X14, [SP, #104]

0x459a80 STR	X0, [X23, X5,LSL #3]

0x459a84 STR	XZR, [X20, X0,LSL #3]

0x459a88 ADD	X0, X0, #1

0x459a8c STR	X5, [X14, X0,LSL #3]

0x459a90 LDR	X5, [X1, X0,LSL #3]

0x459a94 LDR	X14, [SP, #104]

0x459a98 STR	X0, [X23, X5,LSL #3]

0x459a9c STR	XZR, [X20, X0,LSL #3]

0x459aa0 ADD	X0, X0, #1

0x459aa4 STR	X5, [X14, X0,LSL #3]

0x459aa8 LDR	X5, [X1, X0,LSL #3]

0x459aac LDR	X14, [SP, #104]

0x459ab0 STR	X0, [X23, X5,LSL #3]

0x459ab4 STR	XZR, [X20, X0,LSL #3]

0x459ab8 ADD	X0, X0, #1

0x459abc STR	X5, [X14, X0,LSL #3]

0x459ac0 LDR	X5, [X1, X0,LSL #3]

0x459ac4 LDR	X14, [SP, #104]

0x459ac8 STR	X0, [X23, X5,LSL #3]

0x459acc STR	XZR, [X20, X0,LSL #3]

0x459ad0 ADD	X0, X0, #1

0x459ad4 STR	X5, [X14, X0,LSL #3]

0x459ad8 LDR	X5, [X1, X0,LSL #3]

0x459adc LDR	X14, [SP, #104]

0x459ae0 STR	X0, [X23, X5,LSL #3]

0x459ae4 STR	XZR, [X20, X0,LSL #3]

0x459ae8 ADD	X0, X0, #1

0x459aec STR	X5, [X14, X0,LSL #3]

0x459af0 LDR	X5, [X1, X0,LSL #3]

0x459af4 LDR	X14, [SP, #104]

0x459af8 STR	X0, [X23, X5,LSL #3]

0x459afc STR	XZR, [X20, X0,LSL #3]

0x459b00 ADD	X0, X0, #1

0x459b04 STR	X5, [X14, X0,LSL #3]

0x459b08 LDR	X5, [X1, X0,LSL #3]

0x459b0c LDR	X14, [SP, #104]

0x459b10 STR	X0, [X23, X5,LSL #3]

0x459b14 STR	XZR, [X20, X0,LSL #3]

0x459b18 ADD	X0, X0, #1

0x459b1c STR	X5, [X14, X0,LSL #3]

0x459b20 CMP	X13, X0

0x459b24 B.EQ	459bec

0x459b28 ORR	X5, XZR, X14

0x459b2c STP	X26, X15, [SP, #144]

0x459b30 STP	X22, X28, [SP, #160]

0x459b34 STP	X9, X6, [SP, #176]

  (709) 0x459b38 ADD	X6, X0, #1

  (709) 0x459b3c ADD	X26, X0, #2

  (709) 0x459b40 ADD	X22, X0, #3

  (709) 0x459b44 ADD	X15, X0, #4

  (709) 0x459b48 LDR	X28, [X1, X0,LSL #3]

  (709) 0x459b4c ADD	X14, X0, #5

  (709) 0x459b50 ADD	X9, X0, #6

  (709) 0x459b54 STR	X0, [X23, X28,LSL #3]

  (709) 0x459b58 STR	XZR, [X20, X0,LSL #3]

  (709) 0x459b5c STR	X28, [X5, X6,LSL #3]

  (709) 0x459b60 LDR	X28, [X1, X6,LSL #3]

  (709) 0x459b64 STR	X6, [X23, X28,LSL #3]

  (709) 0x459b68 STR	XZR, [X20, X6,LSL #3]

  (709) 0x459b6c ADD	X6, X0, #7

  (709) 0x459b70 ADD	X0, X0, #8

  (709) 0x459b74 STR	X28, [X5, X26,LSL #3]

  (709) 0x459b78 LDR	X28, [X1, X26,LSL #3]

  (709) 0x459b7c STR	X26, [X23, X28,LSL #3]

  (709) 0x459b80 STR	XZR, [X20, X26,LSL #3]

  (709) 0x459b84 STR	X28, [X5, X22,LSL #3]

  (709) 0x459b88 LDR	X26, [X1, X22,LSL #3]

  (709) 0x459b8c STR	X22, [X23, X26,LSL #3]

  (709) 0x459b90 STR	XZR, [X20, X22,LSL #3]

  (709) 0x459b94 STR	X26, [X5, X15,LSL #3]

  (709) 0x459b98 LDR	X22, [X1, X15,LSL #3]

  (709) 0x459b9c STR	X15, [X23, X22,LSL #3]

  (709) 0x459ba0 STR	XZR, [X20, X15,LSL #3]

  (709) 0x459ba4 STR	X22, [X5, X14,LSL #3]

  (709) 0x459ba8 LDR	X15, [X1, X14,LSL #3]

  (709) 0x459bac STR	X14, [X23, X15,LSL #3]

  (709) 0x459bb0 STR	XZR, [X20, X14,LSL #3]

  (709) 0x459bb4 STR	X15, [X5, X9,LSL #3]

  (709) 0x459bb8 LDR	X14, [X1, X9,LSL #3]

  (709) 0x459bbc STR	X9, [X23, X14,LSL #3]

  (709) 0x459bc0 STR	XZR, [X20, X9,LSL #3]

  (709) 0x459bc4 STR	X14, [X5, X6,LSL #3]

  (709) 0x459bc8 LDR	X9, [X1, X6,LSL #3]

  (709) 0x459bcc STR	X6, [X23, X9,LSL #3]

  (709) 0x459bd0 STR	XZR, [X20, X6,LSL #3]

  (709) 0x459bd4 STR	X9, [X5, X0,LSL #3]

  (709) 0x459bd8 CMP	X13, X0

  (709) 0x459bdc B.NE	459b38

0x459be0 LDP	X26, X15, [SP, #144]

0x459be4 LDP	X22, X28, [SP, #160]

0x459be8 LDP	X9, X6, [SP, #176]

0x459bec LDR	X13, [SP, #120]

0x459bf0 LDR	X0, [SP, #200]

0x459bf4 LDR	X5, [X13, X8]

0x459bf8 LDR	X1, [X0, X4]

0x459bfc LDR	X0, [X13, X4]

0x459c00 ADD	X14, X1, X5

0x459c04 SUB	X5, X14, X0

0x459c08 CMP	X1, X5

0x459c0c B.GE	459de0

0x459c10 LDR	X14, [SP, #136]

0x459c14 LDR	X13, [SP, #280]

0x459c18 LDR	X14, [X13, X14]

0x459c1c SUB	X13, X0, X1

0x459c20 UBFM	X1, X1, #61, #60

0x459c24 ADD	X13, X13, X5

0x459c28 SUB	X1, X1, X0,LSL #3

0x459c2c SUB	X5, X13, X0

0x459c30 ANDS	X5, X5, #0x7

0x459c34 ADD	X1, X14, X1

0x459c38 B.EQ	45aa50

0x459c3c CMP	X5, #1

0x459c40 B.EQ	459cfc

0x459c44 CMP	X5, #2

0x459c48 B.EQ	459ce4

0x459c4c CMP	X5, #3

0x459c50 B.EQ	459ccc

0x459c54 CMP	X5, #4

0x459c58 B.EQ	459cb4

0x459c5c CMP	X5, #5

0x459c60 B.EQ	459c9c

0x459c64 CMP	X5, #6

0x459c68 B.EQ	459c84

0x459c6c LDR	X5, [X1, X0,LSL #3]

0x459c70 LDR	X14, [SP, #112]

0x459c74 STR	X0, [X22, X5,LSL #3]

0x459c78 STR	XZR, [X19, X0,LSL #3]

0x459c7c ADD	X0, X0, #1

0x459c80 STR	X5, [X14, X0,LSL #3]

0x459c84 LDR	X5, [X1, X0,LSL #3]

0x459c88 LDR	X14, [SP, #112]

0x459c8c STR	X0, [X22, X5,LSL #3]

0x459c90 STR	XZR, [X19, X0,LSL #3]

0x459c94 ADD	X0, X0, #1

0x459c98 STR	X5, [X14, X0,LSL #3]

0x459c9c LDR	X5, [X1, X0,LSL #3]

0x459ca0 LDR	X14, [SP, #112]

0x459ca4 STR	X0, [X22, X5,LSL #3]

0x459ca8 STR	XZR, [X19, X0,LSL #3]

0x459cac ADD	X0, X0, #1

0x459cb0 STR	X5, [X14, X0,LSL #3]

0x459cb4 LDR	X5, [X1, X0,LSL #3]

0x459cb8 LDR	X14, [SP, #112]

0x459cbc STR	X0, [X22, X5,LSL #3]

0x459cc0 STR	XZR, [X19, X0,LSL #3]

0x459cc4 ADD	X0, X0, #1

0x459cc8 STR	X5, [X14, X0,LSL #3]

0x459ccc LDR	X5, [X1, X0,LSL #3]

0x459cd0 LDR	X14, [SP, #112]

0x459cd4 STR	X0, [X22, X5,LSL #3]

0x459cd8 STR	XZR, [X19, X0,LSL #3]

0x459cdc ADD	X0, X0, #1

0x459ce0 STR	X5, [X14, X0,LSL #3]

0x459ce4 LDR	X5, [X1, X0,LSL #3]

0x459ce8 LDR	X14, [SP, #112]

0x459cec STR	X0, [X22, X5,LSL #3]

0x459cf0 STR	XZR, [X19, X0,LSL #3]

0x459cf4 ADD	X0, X0, #1

0x459cf8 STR	X5, [X14, X0,LSL #3]

0x459cfc LDR	X5, [X1, X0,LSL #3]

0x459d00 LDR	X14, [SP, #112]

0x459d04 STR	X0, [X22, X5,LSL #3]

0x459d08 STR	XZR, [X19, X0,LSL #3]

0x459d0c ADD	X0, X0, #1

0x459d10 STR	X5, [X14, X0,LSL #3]

0x459d14 CMP	X0, X13

0x459d18 B.EQ	459de0

0x459d1c ORR	X5, XZR, X14

0x459d20 STP	X26, X15, [SP, #144]

0x459d24 STP	X23, X28, [SP, #160]

0x459d28 STP	X9, X6, [SP, #176]

  (708) 0x459d2c ADD	X6, X0, #1

  (708) 0x459d30 ADD	X26, X0, #2

  (708) 0x459d34 ADD	X23, X0, #3

  (708) 0x459d38 ADD	X15, X0, #4

  (708) 0x459d3c LDR	X28, [X1, X0,LSL #3]

  (708) 0x459d40 ADD	X14, X0, #5

  (708) 0x459d44 ADD	X9, X0, #6

  (708) 0x459d48 STR	X0, [X22, X28,LSL #3]

  (708) 0x459d4c STR	XZR, [X19, X0,LSL #3]

  (708) 0x459d50 STR	X28, [X5, X6,LSL #3]

  (708) 0x459d54 LDR	X28, [X1, X6,LSL #3]

  (708) 0x459d58 STR	X6, [X22, X28,LSL #3]

  (708) 0x459d5c STR	XZR, [X19, X6,LSL #3]

  (708) 0x459d60 ADD	X6, X0, #7

  (708) 0x459d64 ADD	X0, X0, #8

  (708) 0x459d68 STR	X28, [X5, X26,LSL #3]

  (708) 0x459d6c LDR	X28, [X1, X26,LSL #3]

  (708) 0x459d70 STR	X26, [X22, X28,LSL #3]

  (708) 0x459d74 STR	XZR, [X19, X26,LSL #3]

  (708) 0x459d78 STR	X28, [X5, X23,LSL #3]

  (708) 0x459d7c LDR	X26, [X1, X23,LSL #3]

  (708) 0x459d80 STR	X23, [X22, X26,LSL #3]

  (708) 0x459d84 STR	XZR, [X19, X23,LSL #3]

  (708) 0x459d88 STR	X26, [X5, X15,LSL #3]

  (708) 0x459d8c LDR	X23, [X1, X15,LSL #3]

  (708) 0x459d90 STR	X15, [X22, X23,LSL #3]

  (708) 0x459d94 STR	XZR, [X19, X15,LSL #3]

  (708) 0x459d98 STR	X23, [X5, X14,LSL #3]

  (708) 0x459d9c LDR	X15, [X1, X14,LSL #3]

  (708) 0x459da0 STR	X14, [X22, X15,LSL #3]

  (708) 0x459da4 STR	XZR, [X19, X14,LSL #3]

  (708) 0x459da8 STR	X15, [X5, X9,LSL #3]

  (708) 0x459dac LDR	X14, [X1, X9,LSL #3]

  (708) 0x459db0 STR	X9, [X22, X14,LSL #3]

  (708) 0x459db4 STR	XZR, [X19, X9,LSL #3]

  (708) 0x459db8 STR	X14, [X5, X6,LSL #3]

  (708) 0x459dbc LDR	X9, [X1, X6,LSL #3]

  (708) 0x459dc0 STR	X6, [X22, X9,LSL #3]

  (708) 0x459dc4 STR	XZR, [X19, X6,LSL #3]

  (708) 0x459dc8 STR	X9, [X5, X0,LSL #3]

  (708) 0x459dcc CMP	X0, X13

  (708) 0x459dd0 B.NE	459d2c

0x459dd4 LDP	X26, X15, [SP, #144]

0x459dd8 LDP	X23, X28, [SP, #160]

0x459ddc LDP	X9, X6, [SP, #176]

0x459de0 LDR	X0, [SP, #232]

0x459de4 LDR	X1, [X0, X4]

0x459de8 ADD	X14, X0, X8

0x459dec LDR	X13, [X0, X8]

0x459df0 CMP	X1, X13

0x459df4 B.GE	459e20

0x459df8 HINT	#0

0x459dfc HINT	#0

  (707) 0x459e00 LDR	X5, [X11, X1,LSL #3]

  (707) 0x459e04 UBFM	X0, X5, #61, #60

  (707) 0x459e08 LDR	X5, [X9, X0]

  (707) 0x459e0c CMP	X2, X5

  (707) 0x459e10 B.EQ	45a3fc

  (707) 0x459e14 ADD	X1, X1, #1

  (707) 0x459e18 CMP	X1, X13

  (707) 0x459e1c B.LT	459e00

0x459e20 LDR	X0, [SP, #224]

0x459e24 LDR	X1, [X0, X4]

0x459e28 ADD	X14, X0, X8

0x459e2c LDR	X13, [X0, X8]

0x459e30 CMP	X1, X13

0x459e34 B.GE	459e60

0x459e38 HINT	#0

0x459e3c HINT	#0

  (706) 0x459e40 LDR	X5, [X10, X1,LSL #3]

  (706) 0x459e44 UBFM	X0, X5, #61, #60

  (706) 0x459e48 LDR	X5, [X28, X0]

  (706) 0x459e4c CMP	X2, X5

  (706) 0x459e50 B.EQ	45a414

  (706) 0x459e54 ADD	X1, X1, #1

  (706) 0x459e58 CMP	X1, X13

  (706) 0x459e5c B.LT	459e40

0x459e60 LDR	X14, [SP, #248]

0x459e64 MOVI	D20, #0

0x459e68 FMOV	D29, D20

0x459e6c LDR	X1, [X14, X4]

0x459e70 LDR	X14, [X14, X8]

0x459e74 ADD	X0, X1, #1

0x459e78 CMP	X0, X14

0x459e7c B.GE	459f04

0x459e80 STP	X15, X28, [SP, #144]

0x459e84 ORR	X15, XZR, X10

0x459e88 ORR	X10, XZR, X17

0x459e8c STR	X9, [SP, #160]

0x459e90 ORR	X9, XZR, X6

0x459e94 B	459eb4

  (703) 0x459e98 LDR	X13, [X27, X5]

  (703) 0x459e9c LDR	X17, [X27, X4]

  (703) 0x459ea0 CMP	X17, X13

  (703) 0x459ea4 B.EQ	459edc

  (703) 0x459ea8 ADD	X0, X0, #1

  (703) 0x459eac CMP	X0, X14

  (703) 0x459eb0 B.EQ	459ef0

  (703) 0x459eb4 LDR	X17, [X12, X0,LSL #3]

  (703) 0x459eb8 UBFM	X5, X17, #61, #60

  (703) 0x459ebc LDR	X28, [X26, X5]

  (703) 0x459ec0 CMP	X3, X28

  (703) 0x459ec4 B.EQ	45a42c

  (703) 0x459ec8 LDR	X6, [X7, X5]

  (703) 0x459ecc CMN	X6, #3

  (703) 0x459ed0 B.EQ	459ea8

  (703) 0x459ed4 CMP	X18, #1

  (703) 0x459ed8 B.NE	459e98

  (703) 0x459edc LDR	D28, [X21, X0,LSL #3]

  (703) 0x459ee0 ADD	X0, X0, #1

  (703) 0x459ee4 FADD	D20, D20, D28

  (703) 0x459ee8 CMP	X0, X14

  (703) 0x459eec B.NE	459eb4

0x459ef0 ORR	X6, XZR, X9

0x459ef4 LDR	X9, [SP, #160]

0x459ef8 ORR	X17, XZR, X10

0x459efc ORR	X10, XZR, X15

0x459f00 LDP	X15, X28, [SP, #144]

0x459f04 LDR	X5, [SP, #240]

0x459f08 LDR	X0, [X5, X4]

0x459f0c LDR	X5, [X5, X8]

0x459f10 CMP	X0, X5

0x459f14 B.GE	459fa4

0x459f18 LDR	X13, [SP, #304]

0x459f1c STP	X26, X28, [SP, #144]

0x459f20 STP	X9, X24, [SP, #160]

0x459f24 STP	X25, X1, [SP, #176]

0x459f28 LDR	X1, [SP, #296]

0x459f2c LDP	X24, X25, [SP, #264]

0x459f30 B	459f50

  (701) 0x459f34 LDR	X28, [X1, X9]

  (701) 0x459f38 LDR	X9, [X27, X4]

  (701) 0x459f3c CMP	X28, X9

  (701) 0x459f40 B.EQ	459f84

  (701) 0x459f44 ADD	X0, X0, #1

  (701) 0x459f48 CMP	X0, X5

  (701) 0x459f4c B.EQ	459f98

  (701) 0x459f50 LDR	X28, [X13, X0,LSL #3]

  (701) 0x459f54 CBZ	X30, 459f5c

  (701) 0x459f58 LDR	X28, [X25, X28,LSL #3]

  (701) 0x459f5c UBFM	X9, X28, #61, #60

  (701) 0x459f60 TBNZ	X28, #63, 459f70

  (701) 0x459f64 LDR	X26, [X15, X9]

  (701) 0x459f68 CMP	X3, X26

  (701) 0x459f6c B.EQ	45a768

  (701) 0x459f70 LDR	X14, [X6, X9]

  (701) 0x459f74 CMN	X14, #3

  (701) 0x459f78 B.EQ	459f44

  (701) 0x459f7c CMP	X18, #1

  (701) 0x459f80 B.NE	459f34

  (701) 0x459f84 LDR	D6, [X17, X0,LSL #3]

  (701) 0x459f88 ADD	X0, X0, #1

  (701) 0x459f8c FADD	D20, D20, D6

  (701) 0x459f90 CMP	X0, X5

  (701) 0x459f94 B.NE	459f50

0x459f98 LDP	X26, X28, [SP, #144]

0x459f9c LDP	X9, X24, [SP, #160]

0x459fa0 LDP	X25, X1, [SP, #176]

0x459fa4 LDR	D21, [X21, X1,LSL #3]

0x459fa8 FMUL	D22, D29, D21

0x459fac FCMP	D22, #0

0x459fb0 B.EQ	459fbc

0x459fb4 FNEG	D20, D20

0x459fb8 FDIV	D31, D20, D22

0x459fbc LDR	X3, [X16, X4]

0x459fc0 LDR	X14, [X16, X8]

0x459fc4 CMP	X3, X14

0x459fc8 B.GE	45a1b4

0x459fcc SUB	X1, X14, X3

0x459fd0 SUB	X5, X1, #1

0x459fd4 CMP	X5, #2

0x459fd8 B.LS	45aa78

0x459fdc UBFM	X5, X1, #2, #63

0x459fe0 ADD	X0, X20, X3,LSL #3

0x459fe4 DUP	V23.2D, V31.D[0]

0x459fe8 UBFM	X13, X5, #59, #58

0x459fec UBFM	X14, X3, #61, #60

0x459ff0 SUB	X13, X13, #32

0x459ff4 ADD	X5, X0, X5,LSL #5

0x459ff8 UBFM	X13, X13, #5, #63

0x459ffc ADD	X13, X13, #1

0x45a000 ANDS	X13, X13, #0x7

0x45a004 B.EQ	45a0d4

0x45a008 CMP	X13, #1

0x45a00c B.EQ	45a0b8

0x45a010 CMP	X13, #2

0x45a014 B.EQ	45a0a4

0x45a018 CMP	X13, #3

0x45a01c B.EQ	45a090

0x45a020 CMP	X13, #4

0x45a024 B.EQ	45a07c

0x45a028 CMP	X13, #5

0x45a02c B.EQ	45a068

0x45a030 CMP	X13, #6

0x45a034 B.EQ	45a054

0x45a038 LDR	Q30, [X20, X14]

0x45a03c ADD	X0, X0, #32

0x45a040 LDUR	Q18, [X0, #496]

0x45a044 FMUL	V27.2D, V30.2D, V23.2D

0x45a048 FMUL	V17.2D, V18.2D, V23.2D

0x45a04c STR	Q27, [X20, X14]

0x45a050 STUR	Q17, [X0, #496]

0x45a054 LDP	Q0, Q28, [X0]

0x45a058 ADD	X0, X0, #32

0x45a05c FMUL	V1.2D, V0.2D, V23.2D

0x45a060 FMUL	V25.2D, V28.2D, V23.2D

0x45a064 STP	Q1, Q25, [X0, #2016]

0x45a068 LDP	Q24, Q7, [X0]

0x45a06c ADD	X0, X0, #32

0x45a070 FMUL	V2.2D, V24.2D, V23.2D

0x45a074 FMUL	V6.2D, V7.2D, V23.2D

0x45a078 STP	Q2, Q6, [X0, #2016]

0x45a07c LDP	Q3, Q5, [X0]

0x45a080 ADD	X0, X0, #32

0x45a084 FMUL	V26.2D, V3.2D, V23.2D

0x45a088 FMUL	V4.2D, V5.2D, V23.2D

0x45a08c STP	Q26, Q4, [X0, #2016]

0x45a090 LDP	Q16, Q19, [X0]

0x45a094 ADD	X0, X0, #32

0x45a098 FMUL	V29.2D, V16.2D, V23.2D

0x45a09c FMUL	V21.2D, V19.2D, V23.2D

0x45a0a0 STP	Q29, Q21, [X0, #2016]

0x45a0a4 LDP	Q22, Q20, [X0]

0x45a0a8 ADD	X0, X0, #32

0x45a0ac FMUL	V30.2D, V22.2D, V23.2D

0x45a0b0 FMUL	V27.2D, V20.2D, V23.2D

0x45a0b4 STP	Q30, Q27, [X0, #2016]

0x45a0b8 LDP	Q18, Q17, [X0]

0x45a0bc ADD	X0, X0, #32

0x45a0c0 FMUL	V0.2D, V18.2D, V23.2D

0x45a0c4 FMUL	V28.2D, V17.2D, V23.2D

0x45a0c8 STP	Q0, Q28, [X0, #2016]

0x45a0cc CMP	X5, X0

0x45a0d0 B.EQ	45a17c

0x45a0d4 STP	X26, X15, [SP, #144]

0x45a0d8 STP	X23, X22, [SP, #160]

  (700) 0x45a0dc ORR	X22, XZR, X0

  (700) 0x45a0e0 LDP	Q1, Q24, [X0]

  (700) 0x45a0e4 LDP	Q7, Q2, [X0, #32]

  (700) 0x45a0e8 LDP	Q6, Q3, [X0, #64]

  (700) 0x45a0ec LDP	Q29, Q21, [X0, #96]

  (700) 0x45a0f0 LDP	Q22, Q20, [X0, #128]

  (700) 0x45a0f4 FMUL	V25.2D, V1.2D, V23.2D

  (700) 0x45a0f8 LDP	Q27, Q18, [X0, #160]

  (700) 0x45a0fc FMUL	V5.2D, V24.2D, V23.2D

  (700) 0x45a100 LDP	Q0, Q28, [X0, #192]

  (700) 0x45a104 FMUL	V26.2D, V7.2D, V23.2D

  (700) 0x45a108 LDP	Q30, Q1, [X0, #224]

  (700) 0x45a10c ADD	X0, X0, #256

  (700) 0x45a110 FMUL	V4.2D, V2.2D, V23.2D

  (700) 0x45a114 FMUL	V16.2D, V6.2D, V23.2D

  (700) 0x45a118 FMUL	V19.2D, V3.2D, V23.2D

  (700) 0x45a11c FMUL	V17.2D, V21.2D, V23.2D

  (700) 0x45a120 FMUL	V6.2D, V22.2D, V23.2D

  (700) 0x45a124 FMUL	V7.2D, V20.2D, V23.2D

  (700) 0x45a128 FMUL	V2.2D, V0.2D, V23.2D

  (700) 0x45a12c STUR	Q16, [X0, #320]

  (700) 0x45a130 FMUL	V3.2D, V28.2D, V23.2D

  (700) 0x45a134 STUR	Q19, [X0, #336]

  (700) 0x45a138 STP	Q25, Q5, [X0, #1792]

  (700) 0x45a13c FMUL	V25.2D, V29.2D, V23.2D

  (700) 0x45a140 FMUL	V5.2D, V18.2D, V23.2D

  (700) 0x45a144 STP	Q26, Q4, [X0, #1824]

  (700) 0x45a148 FMUL	V26.2D, V27.2D, V23.2D

  (700) 0x45a14c FMUL	V4.2D, V30.2D, V23.2D

  (700) 0x45a150 FMUL	V24.2D, V1.2D, V23.2D

  (700) 0x45a154 STP	Q25, Q17, [X0, #1888]

  (700) 0x45a158 STP	Q6, Q7, [X0, #1920]

  (700) 0x45a15c STP	Q26, Q5, [X0, #1952]

  (700) 0x45a160 STP	Q2, Q3, [X0, #1984]

  (700) 0x45a164 STUR	Q4, [X0, #480]

  (700) 0x45a168 STR	Q24, [X22, #240]

  (700) 0x45a16c CMP	X5, X0

  (700) 0x45a170 B.NE	45a0dc

0x45a174 LDP	X26, X15, [SP, #144]

0x45a178 LDP	X23, X22, [SP, #160]

0x45a17c AND	X13, X1, #0x0

0x45a180 ANDS	XZR, X1, #0x3

0x45a184 B.EQ	45a1b4

0x45a188 ADD	X3, X13, X3

0x45a18c SUB	X14, X1, X13

0x45a190 DUP	Z23.D, Z31.D[0]

0x45a194 WHILELO	P7.D, XZR, X14

0x45a198 ADD	X1, X20, X3,LSL #3

0x45a19c LD1D	{Z16.D}, P7/Z, [X20, X3,LSL #3]

0x45a1a0 FMUL	Z19.D, Z16.D, Z23.D

0x45a1a4 ST1D	{Z19.D}, P7, [X1, MUL VL]

0x45a1a8 CNTD	X5, ALL

0x45a1ac WHILELO	P0.D, X5, X14

0x45a1b0 B.NE	45aa04

0x45a1b4 LDR	X13, [SP, #120]

0x45a1b8 LDR	X3, [X13, X4]

0x45a1bc LDR	X4, [X13, X8]

0x45a1c0 CMP	X3, X4

0x45a1c4 B.GE	45a3a8

0x45a1c8 SUB	X14, X4, X3

0x45a1cc SUB	X8, X14, #1

0x45a1d0 CMP	X8, #2

0x45a1d4 B.LS	45aa80

0x45a1d8 UBFM	X1, X14, #2, #63

0x45a1dc ADD	X0, X19, X3,LSL #3

0x45a1e0 DUP	V27.2D, V31.D[0]

0x45a1e4 UBFM	X5, X1, #59, #58

0x45a1e8 UBFM	X13, X3, #61, #60

0x45a1ec SUB	X8, X5, #32

0x45a1f0 ADD	X4, X0, X1,LSL #5

0x45a1f4 UBFM	X1, X8, #5, #63

0x45a1f8 ADD	X5, X1, #1

0x45a1fc ANDS	X8, X5, #0x7

0x45a200 B.EQ	45a2d0

0x45a204 CMP	X8, #1

0x45a208 B.EQ	45a2b4

0x45a20c CMP	X8, #2

0x45a210 B.EQ	45a2a0

0x45a214 CMP	X8, #3

0x45a218 B.EQ	45a28c

0x45a21c CMP	X8, #4

0x45a220 B.EQ	45a278

0x45a224 CMP	X8, #5

0x45a228 B.EQ	45a264

0x45a22c CMP	X8, #6

0x45a230 B.EQ	45a250

0x45a234 LDR	Q22, [X19, X13]

0x45a238 ADD	X0, X0, #32

0x45a23c LDUR	Q18, [X0, #496]

0x45a240 FMUL	V20.2D, V22.2D, V27.2D

0x45a244 FMUL	V0.2D, V18.2D, V27.2D

0x45a248 STR	Q20, [X19, X13]

0x45a24c STUR	Q0, [X0, #496]

0x45a250 LDP	Q28, Q30, [X0]

0x45a254 ADD	X0, X0, #32

0x45a258 FMUL	V1.2D, V28.2D, V27.2D

0x45a25c FMUL	V25.2D, V30.2D, V27.2D

0x45a260 STP	Q1, Q25, [X0, #2016]

0x45a264 LDP	Q6, Q17, [X0]

0x45a268 ADD	X0, X0, #32

0x45a26c FMUL	V7.2D, V6.2D, V27.2D

0x45a270 FMUL	V26.2D, V17.2D, V27.2D

0x45a274 STP	Q7, Q26, [X0, #2016]

0x45a278 LDP	Q5, Q2, [X0]

0x45a27c ADD	X0, X0, #32

0x45a280 FMUL	V3.2D, V5.2D, V27.2D

0x45a284 FMUL	V4.2D, V2.2D, V27.2D

0x45a288 STP	Q3, Q4, [X0, #2016]

0x45a28c LDP	Q24, Q23, [X0]

0x45a290 ADD	X0, X0, #32

0x45a294 FMUL	V16.2D, V24.2D, V27.2D

0x45a298 FMUL	V19.2D, V23.2D, V27.2D

0x45a29c STP	Q16, Q19, [X0, #2016]

0x45a2a0 LDP	Q29, Q21, [X0]

0x45a2a4 ADD	X0, X0, #32

0x45a2a8 FMUL	V22.2D, V29.2D, V27.2D

0x45a2ac FMUL	V20.2D, V21.2D, V27.2D

0x45a2b0 STP	Q22, Q20, [X0, #2016]

0x45a2b4 LDP	Q18, Q0, [X0]

0x45a2b8 ADD	X0, X0, #32

0x45a2bc FMUL	V28.2D, V18.2D, V27.2D

0x45a2c0 FMUL	V30.2D, V0.2D, V27.2D

0x45a2c4 STP	Q28, Q30, [X0, #2016]

0x45a2c8 CMP	X4, X0

0x45a2cc B.EQ	45a370

0x45a2d0 STP	X26, X15, [SP, #144]

  (699) 0x45a2d4 ORR	X15, XZR, X0

  (699) 0x45a2d8 LDP	Q1, Q25, [X0]

  (699) 0x45a2dc LDP	Q6, Q17, [X0, #32]

  (699) 0x45a2e0 LDP	Q7, Q26, [X0, #64]

  (699) 0x45a2e4 LDP	Q19, Q29, [X0, #96]

  (699) 0x45a2e8 LDP	Q21, Q16, [X0, #128]

  (699) 0x45a2ec FMUL	V2.2D, V25.2D, V27.2D

  (699) 0x45a2f0 LDP	Q22, Q20, [X0, #160]

  (699) 0x45a2f4 FMUL	V5.2D, V1.2D, V27.2D

  (699) 0x45a2f8 LDP	Q0, Q28, [X0, #192]

  (699) 0x45a2fc FMUL	V3.2D, V6.2D, V27.2D

  (699) 0x45a300 LDP	Q30, Q25, [X0, #224]

  (699) 0x45a304 ADD	X0, X0, #256

  (699) 0x45a308 FMUL	V4.2D, V17.2D, V27.2D

  (699) 0x45a30c FMUL	V24.2D, V7.2D, V27.2D

  (699) 0x45a310 FMUL	V23.2D, V26.2D, V27.2D

  (699) 0x45a314 FMUL	V17.2D, V19.2D, V27.2D

  (699) 0x45a318 FMUL	V18.2D, V29.2D, V27.2D

  (699) 0x45a31c FMUL	V7.2D, V21.2D, V27.2D

  (699) 0x45a320 FMUL	V26.2D, V16.2D, V27.2D

  (699) 0x45a324 STUR	Q24, [X0, #320]

  (699) 0x45a328 FMUL	V6.2D, V20.2D, V27.2D

  (699) 0x45a32c STUR	Q23, [X0, #336]

  (699) 0x45a330 FMUL	V1.2D, V30.2D, V27.2D

  (699) 0x45a334 STP	Q5, Q2, [X0, #1792]

  (699) 0x45a338 FMUL	V5.2D, V22.2D, V27.2D

  (699) 0x45a33c STP	Q3, Q4, [X0, #1824]

  (699) 0x45a340 FMUL	V3.2D, V0.2D, V27.2D

  (699) 0x45a344 STUR	Q1, [X0, #480]

  (699) 0x45a348 FMUL	V4.2D, V28.2D, V27.2D

  (699) 0x45a34c FMUL	V2.2D, V25.2D, V27.2D

  (699) 0x45a350 STP	Q17, Q18, [X0, #1888]

  (699) 0x45a354 STP	Q7, Q26, [X0, #1920]

  (699) 0x45a358 STP	Q5, Q6, [X0, #1952]

  (699) 0x45a35c STP	Q3, Q4, [X0, #1984]

  (699) 0x45a360 STR	Q2, [X15, #240]

  (699) 0x45a364 CMP	X4, X0

  (699) 0x45a368 B.NE	45a2d4

0x45a36c LDP	X26, X15, [SP, #144]

0x45a370 AND	X0, X14, #0x0

0x45a374 ANDS	XZR, X14, #0x3

0x45a378 B.EQ	45a3a8

0x45a37c ADD	X3, X3, X0

0x45a380 SUB	X14, X14, X0

0x45a384 DUP	Z27.D, Z31.D[0]

0x45a388 WHILELO	P1.D, XZR, X14

0x45a38c ADD	X13, X19, X3,LSL #3

0x45a390 LD1D	{Z24.D}, P1/Z, [X19, X3,LSL #3]

0x45a394 FMUL	Z23.D, Z24.D, Z27.D

0x45a398 ST1D	{Z23.D}, P1, [X13, MUL VL]

0x45a39c CNTD	X4, ALL

0x45a3a0 WHILELO	P2.D, X4, X14

0x45a3a4 B.NE	45a9f0

0x45a3a8 LDR	X5, [SP, #128]

0x45a3ac LDR	X1, [SP, #256]

0x45a3b0 ADD	X8, X5, #1

0x45a3b4 STR	X8, [SP, #128]

0x45a3b8 CMP	X1, X8

0x45a3bc B.NE	4599e0

  (707) 0x45a3fc STR	X3, [X26, X0]

  (707) 0x45a400 ADD	X1, X1, #1

  (707) 0x45a404 LDR	X13, [X14]

  (707) 0x45a408 CMP	X13, X1

  (707) 0x45a40c B.GT	459e00

0x45a410 B	459e20

  (706) 0x45a414 STR	X3, [X15, X0]

  (706) 0x45a418 ADD	X1, X1, #1

  (706) 0x45a41c LDR	X13, [X14]

  (706) 0x45a420 CMP	X13, X1

  (706) 0x45a424 B.GT	459e40

0x45a428 B	459e60

  (703) 0x45a42c ADD	X13, X5, #8

  (703) 0x45a430 LDR	X6, [X16, X5]

  (703) 0x45a434 LDR	X17, [X16, X13]

  (703) 0x45a438 CMP	X6, X17

  (703) 0x45a43c B.GE	45a5cc

  (703) 0x45a440 SUB	X28, X17, X6

  (703) 0x45a444 ANDS	X28, X28, #0x3

  (703) 0x45a448 B.EQ	45a4f4

  (703) 0x45a44c CMP	X28, #1

  (703) 0x45a450 B.EQ	45a4bc

  (703) 0x45a454 CMP	X28, #2

  (703) 0x45a458 B.EQ	45a48c

  (703) 0x45a45c LDR	X28, [X25, X6,LSL #3]

  (703) 0x45a460 LDR	D17, [X20, X6,LSL #3]

  (703) 0x45a464 ADD	X6, X6, #1

  (703) 0x45a468 LDR	D18, [X21, X0,LSL #3]

  (703) 0x45a46c LDR	X28, [X23, X28,LSL #3]

  (703) 0x45a470 FMUL	D0, D18, D17

  (703) 0x45a474 UBFM	X28, X28, #61, #60

  (703) 0x45a478 LDR	D7, [X20, X28]

  (703) 0x45a47c FADD	D29, D29, D0

  (703) 0x45a480 FADD	D20, D20, D0

  (703) 0x45a484 FADD	D1, D7, D0

  (703) 0x45a488 STR	D1, [X20, X28]

  (703) 0x45a48c LDR	X28, [X25, X6,LSL #3]

  (703) 0x45a490 LDR	D24, [X20, X6,LSL #3]

  (703) 0x45a494 ADD	X6, X6, #1

  (703) 0x45a498 LDR	D25, [X21, X0,LSL #3]

  (703) 0x45a49c LDR	X28, [X23, X28,LSL #3]

  (703) 0x45a4a0 FMUL	D2, D25, D24

  (703) 0x45a4a4 UBFM	X28, X28, #61, #60

  (703) 0x45a4a8 LDR	D6, [X20, X28]

  (703) 0x45a4ac FADD	D29, D29, D2

  (703) 0x45a4b0 FADD	D20, D20, D2

  (703) 0x45a4b4 FADD	D3, D6, D2

  (703) 0x45a4b8 STR	D3, [X20, X28]

  (703) 0x45a4bc LDR	X28, [X25, X6,LSL #3]

  (703) 0x45a4c0 LDR	D4, [X20, X6,LSL #3]

  (703) 0x45a4c4 ADD	X6, X6, #1

  (703) 0x45a4c8 LDR	D5, [X21, X0,LSL #3]

  (703) 0x45a4cc LDR	X28, [X23, X28,LSL #3]

  (703) 0x45a4d0 FMUL	D31, D5, D4

  (703) 0x45a4d4 UBFM	X28, X28, #61, #60

  (703) 0x45a4d8 LDR	D26, [X20, X28]

  (703) 0x45a4dc FADD	D29, D29, D31

  (703) 0x45a4e0 FADD	D20, D20, D31

  (703) 0x45a4e4 FADD	D16, D26, D31

  (703) 0x45a4e8 STR	D16, [X20, X28]

  (703) 0x45a4ec CMP	X6, X17

  (703) 0x45a4f0 B.EQ	45a5cc

  (703) 0x45a4f4 STP	X26, X22, [SP, #168]

  (703) 0x45a4f8 STP	X9, X24, [SP, #184]

    (705) 0x45a4fc ADD	X22, X6, #1

    (705) 0x45a500 ADD	X26, X6, #3

    (705) 0x45a504 ADD	X28, X22, #1

    (705) 0x45a508 LDR	X24, [X25, X6,LSL #3]

    (705) 0x45a50c LDR	D19, [X21, X0,LSL #3]

    (705) 0x45a510 LDR	D21, [X20, X6,LSL #3]

    (705) 0x45a514 ADD	X6, X6, #4

    (705) 0x45a518 LDR	X9, [X23, X24,LSL #3]

    (705) 0x45a51c LDR	X24, [X25, X22,LSL #3]

    (705) 0x45a520 FMUL	D22, D19, D21

    (705) 0x45a524 UBFM	X9, X9, #61, #60

    (705) 0x45a528 LDR	D23, [X20, X9]

    (705) 0x45a52c LDR	X24, [X23, X24,LSL #3]

    (705) 0x45a530 FADD	D31, D20, D22

    (705) 0x45a534 FADD	D30, D29, D22

    (705) 0x45a538 FADD	D27, D23, D22

    (705) 0x45a53c UBFM	X24, X24, #61, #60

    (705) 0x45a540 STR	D27, [X20, X9]

    (705) 0x45a544 LDR	D18, [X20, X22,LSL #3]

    (705) 0x45a548 LDR	D28, [X21, X0,LSL #3]

    (705) 0x45a54c LDR	D17, [X20, X24]

    (705) 0x45a550 LDR	X22, [X25, X28,LSL #3]

    (705) 0x45a554 FMUL	D7, D28, D18

    (705) 0x45a558 LDR	X9, [X25, X26,LSL #3]

    (705) 0x45a55c LDR	X22, [X23, X22,LSL #3]

    (705) 0x45a560 LDR	X9, [X23, X9,LSL #3]

    (705) 0x45a564 FADD	D0, D17, D7

    (705) 0x45a568 FADD	D25, D31, D7

    (705) 0x45a56c FADD	D1, D30, D7

    (705) 0x45a570 UBFM	X22, X22, #61, #60

    (705) 0x45a574 UBFM	X9, X9, #61, #60

    (705) 0x45a578 STR	D0, [X20, X24]

    (705) 0x45a57c LDR	D24, [X21, X0,LSL #3]

    (705) 0x45a580 LDR	D2, [X20, X28,LSL #3]

    (705) 0x45a584 LDR	D6, [X20, X22]

    (705) 0x45a588 FMUL	D3, D24, D2

    (705) 0x45a58c FADD	D5, D6, D3

    (705) 0x45a590 FADD	D4, D1, D3

    (705) 0x45a594 FADD	D26, D25, D3

    (705) 0x45a598 STR	D5, [X20, X22]

    (705) 0x45a59c LDR	D29, [X21, X0,LSL #3]

    (705) 0x45a5a0 LDR	D20, [X20, X26,LSL #3]

    (705) 0x45a5a4 LDR	D16, [X20, X9]

    (705) 0x45a5a8 FMUL	D31, D29, D20

    (705) 0x45a5ac FADD	D19, D16, D31

    (705) 0x45a5b0 FADD	D29, D4, D31

    (705) 0x45a5b4 FADD	D20, D26, D31

    (705) 0x45a5b8 STR	D19, [X20, X9]

    (705) 0x45a5bc CMP	X6, X17

    (705) 0x45a5c0 B.NE	45a4fc

  (703) 0x45a5c4 LDP	X26, X22, [SP, #168]

  (703) 0x45a5c8 LDP	X9, X24, [SP, #184]

  (703) 0x45a5cc LDR	X17, [SP, #120]

  (703) 0x45a5d0 LDR	X5, [X17, X5]

  (703) 0x45a5d4 LDR	X28, [X17, X13]

  (703) 0x45a5d8 CMP	X5, X28

  (703) 0x45a5dc B.GE	459ea8

  (703) 0x45a5e0 SUB	X13, X28, X5

  (703) 0x45a5e4 ANDS	X6, X13, #0x3

  (703) 0x45a5e8 B.EQ	45a694

  (703) 0x45a5ec CMP	X6, #1

  (703) 0x45a5f0 B.EQ	45a65c

  (703) 0x45a5f4 CMP	X6, #2

  (703) 0x45a5f8 B.EQ	45a62c

  (703) 0x45a5fc LDR	X17, [X24, X5,LSL #3]

  (703) 0x45a600 LDR	D22, [X19, X5,LSL #3]

  (703) 0x45a604 ADD	X5, X5, #1

  (703) 0x45a608 LDR	D21, [X21, X0,LSL #3]

  (703) 0x45a60c LDR	X13, [X22, X17,LSL #3]

  (703) 0x45a610 FMUL	D23, D21, D22

  (703) 0x45a614 UBFM	X6, X13, #61, #60

  (703) 0x45a618 LDR	D30, [X19, X6]

  (703) 0x45a61c FADD	D29, D29, D23

  (703) 0x45a620 FADD	D20, D20, D23

  (703) 0x45a624 FADD	D31, D30, D23

  (703) 0x45a628 STR	D31, [X19, X6]

  (703) 0x45a62c LDR	X17, [X24, X5,LSL #3]

  (703) 0x45a630 LDR	D28, [X19, X5,LSL #3]

  (703) 0x45a634 ADD	X5, X5, #1

  (703) 0x45a638 LDR	D27, [X21, X0,LSL #3]

  (703) 0x45a63c LDR	X13, [X22, X17,LSL #3]

  (703) 0x45a640 FMUL	D18, D27, D28

  (703) 0x45a644 UBFM	X6, X13, #61, #60

  (703) 0x45a648 LDR	D17, [X19, X6]

  (703) 0x45a64c FADD	D29, D29, D18

  (703) 0x45a650 FADD	D20, D20, D18

  (703) 0x45a654 FADD	D7, D17, D18

  (703) 0x45a658 STR	D7, [X19, X6]

  (703) 0x45a65c LDR	X17, [X24, X5,LSL #3]

  (703) 0x45a660 LDR	D1, [X19, X5,LSL #3]

  (703) 0x45a664 ADD	X5, X5, #1

  (703) 0x45a668 LDR	D0, [X21, X0,LSL #3]

  (703) 0x45a66c LDR	X13, [X22, X17,LSL #3]

  (703) 0x45a670 FMUL	D31, D0, D1

  (703) 0x45a674 UBFM	X6, X13, #61, #60

  (703) 0x45a678 LDR	D25, [X19, X6]

  (703) 0x45a67c FADD	D29, D29, D31

  (703) 0x45a680 FADD	D20, D20, D31

  (703) 0x45a684 FADD	D24, D25, D31

  (703) 0x45a688 STR	D24, [X19, X6]

  (703) 0x45a68c CMP	X5, X28

  (703) 0x45a690 B.EQ	459ea8

  (703) 0x45a694 STP	X26, X23, [SP, #168]

    (704) 0x45a698 ADD	X13, X5, #1

    (704) 0x45a69c ADD	X23, X5, #3

    (704) 0x45a6a0 LDR	X26, [X24, X5,LSL #3]

    (704) 0x45a6a4 LDR	D2, [X21, X0,LSL #3]

    (704) 0x45a6a8 LDR	D6, [X19, X5,LSL #3]

    (704) 0x45a6ac ADD	X5, X5, #4

    (704) 0x45a6b0 LDR	X17, [X22, X26,LSL #3]

    (704) 0x45a6b4 ADD	X26, X13, #1

    (704) 0x45a6b8 FMUL	D3, D2, D6

    (704) 0x45a6bc UBFM	X6, X17, #61, #60

    (704) 0x45a6c0 LDR	X17, [X24, X13,LSL #3]

    (704) 0x45a6c4 LDR	D5, [X19, X6]

    (704) 0x45a6c8 FADD	D4, D29, D3

    (704) 0x45a6cc LDR	X17, [X22, X17,LSL #3]

    (704) 0x45a6d0 FADD	D26, D20, D3

    (704) 0x45a6d4 FADD	D29, D5, D3

    (704) 0x45a6d8 UBFM	X17, X17, #61, #60

    (704) 0x45a6dc STR	D29, [X19, X6]

    (704) 0x45a6e0 LDR	D20, [X21, X0,LSL #3]

    (704) 0x45a6e4 LDR	D16, [X19, X13,LSL #3]

    (704) 0x45a6e8 LDR	D19, [X19, X17]

    (704) 0x45a6ec LDR	X13, [X24, X26,LSL #3]

    (704) 0x45a6f0 FMUL	D21, D20, D16

    (704) 0x45a6f4 LDR	X6, [X24, X23,LSL #3]

    (704) 0x45a6f8 LDR	X13, [X22, X13,LSL #3]

    (704) 0x45a6fc LDR	X6, [X22, X6,LSL #3]

    (704) 0x45a700 FADD	D22, D19, D21

    (704) 0x45a704 FADD	D23, D4, D21

    (704) 0x45a708 FADD	D30, D26, D21

    (704) 0x45a70c UBFM	X13, X13, #61, #60

    (704) 0x45a710 UBFM	X6, X6, #61, #60

    (704) 0x45a714 STR	D22, [X19, X17]

    (704) 0x45a718 LDR	D31, [X21, X0,LSL #3]

    (704) 0x45a71c LDR	D27, [X19, X26,LSL #3]

    (704) 0x45a720 LDR	D28, [X19, X13]

    (704) 0x45a724 FMUL	D18, D31, D27

    (704) 0x45a728 FADD	D17, D28, D18

    (704) 0x45a72c FADD	D0, D23, D18

    (704) 0x45a730 FADD	D1, D30, D18

    (704) 0x45a734 STR	D17, [X19, X13]

    (704) 0x45a738 LDR	D25, [X21, X0,LSL #3]

    (704) 0x45a73c LDR	D24, [X19, X23,LSL #3]

    (704) 0x45a740 LDR	D7, [X19, X6]

    (704) 0x45a744 FMUL	D31, D25, D24

    (704) 0x45a748 FADD	D2, D7, D31

    (704) 0x45a74c FADD	D29, D0, D31

    (704) 0x45a750 FADD	D20, D1, D31

    (704) 0x45a754 STR	D2, [X19, X6]

    (704) 0x45a758 CMP	X5, X28

    (704) 0x45a75c B.NE	45a698

  (703) 0x45a760 LDP	X26, X23, [SP, #168]

  (703) 0x45a764 B	459ea8

  (701) 0x45a768 LDP	X14, X26, [SP, #312]

  (701) 0x45a76c ADD	X28, X14, X9

  (701) 0x45a770 LDR	X9, [X26, X9]

  (701) 0x45a774 LDR	X14, [X28, #8]

  (701) 0x45a778 ADD	X26, X9, X14

  (701) 0x45a77c CMP	X9, X26

  (701) 0x45a780 B.GE	459f44

  (701) 0x45a784 LDR	X28, [SP, #136]

  (701) 0x45a788 LDR	X14, [SP, #328]

  (701) 0x45a78c LDR	X14, [X14, X28]

  (701) 0x45a790 SUB	X28, X26, X9

  (701) 0x45a794 ANDS	X28, X28, #0x3

  (701) 0x45a798 B.EQ	45a918

  (701) 0x45a79c CMP	X28, #1

  (701) 0x45a7a0 B.EQ	45a814

  (701) 0x45a7a4 CMP	X28, #2

  (701) 0x45a7a8 B.EQ	45a7e0

  (701) 0x45a7ac LDR	D3, [X17, X0,LSL #3]

  (701) 0x45a7b0 LDR	D5, [X24, X9,LSL #3]

  (701) 0x45a7b4 LDR	X28, [X14, X9,LSL #3]

  (701) 0x45a7b8 FMUL	D26, D3, D5

  (701) 0x45a7bc TBNZ	X28, #63, 45aa88

  (701) 0x45a7c0 LDR	X28, [X22, X28,LSL #3]

  (701) 0x45a7c4 UBFM	X28, X28, #61, #60

  (701) 0x45a7c8 LDR	D4, [X19, X28]

  (701) 0x45a7cc FADD	D16, D4, D26

  (701) 0x45a7d0 STR	D16, [X19, X28]

  (701) 0x45a7d4 FADD	D29, D29, D26

  (701) 0x45a7d8 FADD	D20, D20, D26

  (701) 0x45a7dc ADD	X9, X9, #1

  (701) 0x45a7e0 LDR	D22, [X17, X0,LSL #3]

  (701) 0x45a7e4 LDR	D23, [X24, X9,LSL #3]

  (701) 0x45a7e8 LDR	X28, [X14, X9,LSL #3]

  (701) 0x45a7ec FMUL	D30, D22, D23

  (701) 0x45a7f0 TBNZ	X28, #63, 45aa34

  (701) 0x45a7f4 LDR	X28, [X22, X28,LSL #3]

  (701) 0x45a7f8 UBFM	X28, X28, #61, #60

  (701) 0x45a7fc LDR	D31, [X19, X28]

  (701) 0x45a800 FADD	D27, D31, D30

  (701) 0x45a804 STR	D27, [X19, X28]

  (701) 0x45a808 FADD	D29, D29, D30

  (701) 0x45a80c FADD	D20, D20, D30

  (701) 0x45a810 ADD	X9, X9, #1

  (701) 0x45a814 LDR	D17, [X17, X0,LSL #3]

  (701) 0x45a818 LDR	D0, [X24, X9,LSL #3]

  (701) 0x45a81c LDR	X28, [X14, X9,LSL #3]

  (701) 0x45a820 FMUL	D31, D17, D0

  (701) 0x45a824 TBNZ	X28, #63, 45aa18

  (701) 0x45a828 LDR	X28, [X22, X28,LSL #3]

  (701) 0x45a82c UBFM	X28, X28, #61, #60

  (701) 0x45a830 LDR	D1, [X19, X28]

  (701) 0x45a834 FADD	D25, D1, D31

  (701) 0x45a838 STR	D25, [X19, X28]

  (701) 0x45a83c ADD	X9, X9, #1

  (701) 0x45a840 FADD	D29, D29, D31

  (701) 0x45a844 FADD	D20, D20, D31

  (701) 0x45a848 CMP	X26, X9

  (701) 0x45a84c B.NE	45a918

  (701) 0x45a850 B	459f44

    (702) 0x45a854 LDR	X28, [X22, X28,LSL #3]

    (702) 0x45a858 ADD	X9, X9, #1

    (702) 0x45a85c FADD	D29, D29, D3

    (702) 0x45a860 FADD	D20, D20, D3

    (702) 0x45a864 UBFM	X28, X28, #61, #60

    (702) 0x45a868 LDR	D5, [X19, X28]

    (702) 0x45a86c FADD	D26, D5, D3

    (702) 0x45a870 STR	D26, [X19, X28]

    (702) 0x45a874 LDR	D19, [X17, X0,LSL #3]

    (702) 0x45a878 LDR	D21, [X24, X9,LSL #3]

    (702) 0x45a87c LDR	X28, [X14, X9,LSL #3]

    (702) 0x45a880 FMUL	D22, D19, D21

    (702) 0x45a884 TBNZ	X28, #63, 45a964

    (702) 0x45a888 LDR	X28, [X22, X28,LSL #3]

    (702) 0x45a88c FADD	D17, D29, D22

    (702) 0x45a890 FADD	D0, D20, D22

    (702) 0x45a894 UBFM	X28, X28, #61, #60

    (702) 0x45a898 LDR	D23, [X19, X28]

    (702) 0x45a89c FADD	D30, D23, D22

    (702) 0x45a8a0 STR	D30, [X19, X28]

    (702) 0x45a8a4 ADD	X28, X9, #1

    (702) 0x45a8a8 LDR	D18, [X17, X0,LSL #3]

    (702) 0x45a8ac LDR	D28, [X24, X28,LSL #3]

    (702) 0x45a8b0 LDR	X28, [X14, X28,LSL #3]

    (702) 0x45a8b4 FMUL	D1, D18, D28

    (702) 0x45a8b8 TBNZ	X28, #63, 45a99c

    (702) 0x45a8bc LDR	X28, [X22, X28,LSL #3]

    (702) 0x45a8c0 FADD	D3, D17, D1

    (702) 0x45a8c4 FADD	D5, D0, D1

    (702) 0x45a8c8 UBFM	X28, X28, #61, #60

    (702) 0x45a8cc LDR	D25, [X19, X28]

    (702) 0x45a8d0 FADD	D24, D25, D1

    (702) 0x45a8d4 STR	D24, [X19, X28]

    (702) 0x45a8d8 ADD	X28, X9, #2

    (702) 0x45a8dc LDR	D6, [X17, X0,LSL #3]

    (702) 0x45a8e0 LDR	D26, [X24, X28,LSL #3]

    (702) 0x45a8e4 LDR	X28, [X14, X28,LSL #3]

    (702) 0x45a8e8 FMUL	D31, D6, D26

    (702) 0x45a8ec TBNZ	X28, #63, 45a9d4

    (702) 0x45a8f0 LDR	X28, [X22, X28,LSL #3]

    (702) 0x45a8f4 UBFM	X28, X28, #61, #60

    (702) 0x45a8f8 LDR	D4, [X19, X28]

    (702) 0x45a8fc FADD	D16, D4, D31

    (702) 0x45a900 STR	D16, [X19, X28]

    (702) 0x45a904 ADD	X9, X9, #3

    (702) 0x45a908 FADD	D29, D3, D31

    (702) 0x45a90c FADD	D20, D5, D31

    (702) 0x45a910 CMP	X26, X9

    (702) 0x45a914 B.EQ	459f44

    (702) 0x45a918 LDR	D2, [X17, X0,LSL #3]

    (702) 0x45a91c LDR	D6, [X24, X9,LSL #3]

    (702) 0x45a920 LDR	X28, [X14, X9,LSL #3]

    (702) 0x45a924 FMUL	D3, D2, D6

    (702) 0x45a928 TBZ	X28, #63, 45a854

    (702) 0x45a92c ORN	X28, XZR, X28

    (702) 0x45a930 ADD	X9, X9, #1

    (702) 0x45a934 FADD	D29, D29, D3

    (702) 0x45a938 LDR	X28, [X23, X28,LSL #3]

    (702) 0x45a93c FADD	D20, D20, D3

    (702) 0x45a940 UBFM	X28, X28, #61, #60

    (702) 0x45a944 LDR	D4, [X20, X28]

    (702) 0x45a948 FADD	D16, D4, D3

    (702) 0x45a94c STR	D16, [X20, X28]

    (702) 0x45a950 LDR	D19, [X17, X0,LSL #3]

    (702) 0x45a954 LDR	D21, [X24, X9,LSL #3]

    (702) 0x45a958 LDR	X28, [X14, X9,LSL #3]

    (702) 0x45a95c FMUL	D22, D19, D21

    (702) 0x45a960 TBZ	X28, #63, 45a888

    (702) 0x45a964 ORN	X28, XZR, X28

    (702) 0x45a968 FADD	D17, D29, D22

    (702) 0x45a96c FADD	D0, D20, D22

    (702) 0x45a970 LDR	X28, [X23, X28,LSL #3]

    (702) 0x45a974 UBFM	X28, X28, #61, #60

    (702) 0x45a978 LDR	D31, [X20, X28]

    (702) 0x45a97c FADD	D27, D31, D22

    (702) 0x45a980 STR	D27, [X20, X28]

    (702) 0x45a984 ADD	X28, X9, #1

    (702) 0x45a988 LDR	D18, [X17, X0,LSL #3]

    (702) 0x45a98c LDR	D28, [X24, X28,LSL #3]

    (702) 0x45a990 LDR	X28, [X14, X28,LSL #3]

    (702) 0x45a994 FMUL	D1, D18, D28

    (702) 0x45a998 TBZ	X28, #63, 45a8bc

    (702) 0x45a99c ORN	X28, XZR, X28

    (702) 0x45a9a0 FADD	D3, D17, D1

    (702) 0x45a9a4 FADD	D5, D0, D1

    (702) 0x45a9a8 LDR	X28, [X23, X28,LSL #3]

    (702) 0x45a9ac UBFM	X28, X28, #61, #60

    (702) 0x45a9b0 LDR	D7, [X20, X28]

    (702) 0x45a9b4 FADD	D2, D7, D1

    (702) 0x45a9b8 STR	D2, [X20, X28]

    (702) 0x45a9bc ADD	X28, X9, #2

    (702) 0x45a9c0 LDR	D6, [X17, X0,LSL #3]

    (702) 0x45a9c4 LDR	D26, [X24, X28,LSL #3]

    (702) 0x45a9c8 LDR	X28, [X14, X28,LSL #3]

    (702) 0x45a9cc FMUL	D31, D6, D26

    (702) 0x45a9d0 TBZ	X28, #63, 45a8f0

    (702) 0x45a9d4 ORN	X28, XZR, X28

    (702) 0x45a9d8 LDR	X28, [X23, X28,LSL #3]

    (702) 0x45a9dc UBFM	X28, X28, #61, #60

    (702) 0x45a9e0 LDR	D19, [X20, X28]

    (702) 0x45a9e4 FADD	D29, D19, D31

    (702) 0x45a9e8 STR	D29, [X20, X28]

    (702) 0x45a9ec B	45a904

0x45a9f0 LD1D	{Z19.D}, P2/Z, [X13, #1, MUL VL]

0x45a9f4 INCB	X13, ALL

0x45a9f8 FMUL	Z29.D, Z27.D, Z19.D

0x45a9fc ST1D	{Z29.D}, P2, [X13, MUL VL]

0x45aa00 B	45a3a8

0x45aa04 LD1D	{Z29.D}, P0/Z, [X1, #1, MUL VL]

0x45aa08 INCB	X1, ALL

0x45aa0c FMUL	Z21.D, Z23.D, Z29.D

0x45aa10 ST1D	{Z21.D}, P0, [X1, MUL VL]

0x45aa14 B	45a1b4

  (701) 0x45aa18 ORN	X28, XZR, X28

  (701) 0x45aa1c LDR	X28, [X23, X28,LSL #3]

  (701) 0x45aa20 UBFM	X28, X28, #61, #60

  (701) 0x45aa24 LDR	D24, [X20, X28]

  (701) 0x45aa28 FADD	D7, D24, D31

  (701) 0x45aa2c STR	D7, [X20, X28]

  (701) 0x45aa30 B	45a83c

  (701) 0x45aa34 ORN	X28, XZR, X28

  (701) 0x45aa38 LDR	X28, [X23, X28,LSL #3]

  (701) 0x45aa3c UBFM	X28, X28, #61, #60

  (701) 0x45aa40 LDR	D28, [X20, X28]

  (701) 0x45aa44 FADD	D18, D28, D30

  (701) 0x45aa48 STR	D18, [X20, X28]

  (701) 0x45aa4c B	45a808

0x45aa50 LDR	X5, [SP, #112]

0x45aa54 STP	X26, X15, [SP, #144]

0x45aa58 STP	X23, X28, [SP, #160]

0x45aa5c STP	X9, X6, [SP, #176]

0x45aa60 B	459d2c

0x45aa64 LDR	X5, [SP, #104]

0x45aa68 STP	X26, X15, [SP, #144]

0x45aa6c STP	X22, X28, [SP, #160]

0x45aa70 STP	X9, X6, [SP, #176]

0x45aa74 B	459b38

0x45aa78 MOVZ	X13, #0

0x45aa7c B	45a188

0x45aa80 MOVZ	X0, #0

0x45aa84 B	45a37c

  (701) 0x45aa88 ORN	X28, XZR, X28

  (701) 0x45aa8c LDR	X28, [X23, X28,LSL #3]

  (701) 0x45aa90 UBFM	X28, X28, #61, #60

  (701) 0x45aa94 LDR	D19, [X20, X28]

  (701) 0x45aa98 FADD	D21, D19, D26

  (701) 0x45aa9c STR	D21, [X20, X28]

  (701) 0x45aaa0 B	45a7d4

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1774 - 1876

--------------------------------------------------------------------------------

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module
►98.73+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.27+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1884	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.73
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source	par_multi_interp.c:1774-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1840-1840,par_multi_interp.c:1856-1856,par_multi_interp.c:1871-1876
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	63.33
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	63.33
CQA cycles if fully vectorized	45.46
Front-end cycles	53.88
P0 cycles	29.00
P1 cycles	29.00
P2 cycles	35.25
P3 cycles	35.25
P4 cycles	35.25
P5 cycles	35.25
P6 cycles	15.50
P7 cycles	15.50
P8 cycles	15.50
P9 cycles	15.50
P10 cycles	63.33
P11 cycles	63.33
P12 cycles	63.33
P13 cycles	32.00
P14 cycles	32.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	435.00
Nb uops	431.00
Nb loads	NA
Nb stores	84.00
Nb stack references	72.00
FLOP/cycle	1.17
Nb FLOP add-sub	0.00
Nb FLOP mul	73.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.04
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	37.07
Vectorization ratio load	62.50
Vectorization ratio store	23.81
Vectorization ratio mul	96.97
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	7.27
Vector-efficiency ratio all	47.07
Vector-efficiency ratio load	73.44
Vector-efficiency ratio store	46.13
Vector-efficiency ratio mul	55.30
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	28.64

Metric	Value
CQA speedup if no scalar integer	3.73
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source	par_multi_interp.c:1774-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1840-1840,par_multi_interp.c:1856-1856,par_multi_interp.c:1871-1876
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	63.33
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	63.33
CQA cycles if fully vectorized	45.46
Front-end cycles	53.88
P0 cycles	29.00
P1 cycles	29.00
P2 cycles	35.25
P3 cycles	35.25
P4 cycles	35.25
P5 cycles	35.25
P6 cycles	15.50
P7 cycles	15.50
P8 cycles	15.50
P9 cycles	15.50
P10 cycles	63.33
P11 cycles	63.33
P12 cycles	63.33
P13 cycles	32.00
P14 cycles	32.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	435.00
Nb uops	431.00
Nb loads	NA
Nb stores	84.00
Nb stack references	72.00
FLOP/cycle	1.17
Nb FLOP add-sub	0.00
Nb FLOP mul	73.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.04
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	37.07
Vectorization ratio load	62.50
Vectorization ratio store	23.81
Vectorization ratio mul	96.97
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	7.27
Vector-efficiency ratio all	47.07
Vector-efficiency ratio load	73.44
Vector-efficiency ratio store	46.13
Vector-efficiency ratio mul	55.30
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	28.64

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source file and lines	par_multi_interp.c:1774-1876
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1774-1876.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1774-1799,1805,1811,1840,1856,1871-1876.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 63.33 to 17.00 cycles (3.73x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 47% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 63.33 to 45.46 cycles (1.39x speedup).

Details

37% of VPU instructions are used in vector version (process two or more data elements in vector registers):

62% of VPU loads are used in vector version.
23% of VPU stores are used in vector version.
96% of VPU multiply instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
7% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 74 FP arithmetical operations:

73: multiply
1: divide

The binary loop is loading 128 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	435
nb uops	431
loop length	1740
used w registers	0
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	5
used q registers	23
used v registers	24
used z registers	8
nb stack references	72

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	53.88 cycles
front end	53.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	29.00	29.00	35.25	35.25	35.25	35.25	15.50	15.50	15.50	15.50	63.33	63.33	63.33	32.00	32.00
cycles	29.00	29.00	35.25	35.25	35.25	35.25	15.50	15.50	15.50	15.50	63.33	63.33	63.33	32.00	32.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	53.88
Dispatch	63.33
DIV/SQRT	1.75-3.50
Overall L1	63.33

Vectorization ratios

INT

all	26%
load	62%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	86%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	96%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	37%
load	62%
store	23%
mul	96%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	45%
load	73%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	52%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	55%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	47%
load	73%
store	46%
mul	55%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 63.33 cycles. At this rate:

2% of peak load performance is reached (2.02 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.02 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4599e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X0, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X4, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X1, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X16, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X16, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459bec <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X1, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X13, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X5, X5, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X1, XZR, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 45aa64 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459b08 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459af0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459ad8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459ac0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459aa8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459a90 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459bec <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X5, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X9, X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X13, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X0, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X13, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459de0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X13, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X13, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X1, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X5, X5, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD X1, X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 45aa50 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459cfc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x5bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459ce4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x5a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459ccc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459cb4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x574>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459c9c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x55c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459c84 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X0, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459de0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X5, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X9, X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X0, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X0, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X0, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459e20 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X0, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X0, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X0, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459e60 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x720>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X14, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D29, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X1, [X14, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459f04 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x7c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X15, X28, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X15, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X9, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 459eb4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x774>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X6, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X17, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X15, X28, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X5, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X5, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459fa4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x864>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X26, X28, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X24, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X1, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X24, X25, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 459f50 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x810>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X26, X28, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X24, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X1, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D21, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D22, D29, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMP D22, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 459fbc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x87c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FNEG D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FDIV D31, D20, D22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR X3, [X16, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X16, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45a1b4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X1, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 45aa78 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X5, X1, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X20, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V23.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X13, X5, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X14, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X13, X13, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X0, X5,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X13, X13, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X13, X13, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45a0d4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a0b8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x978>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a0a4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a090 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x950>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a07c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x93c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a068 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a054 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x914>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X20, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR Q18, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMUL V27.2D, V30.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V17.2D, V18.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STR Q27, [X20, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STUR Q17, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP Q0, Q28, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V1.2D, V0.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V25.2D, V28.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q1, Q25, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q24, Q7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V2.2D, V24.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V6.2D, V7.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q2, Q6, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q3, Q5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V26.2D, V3.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V4.2D, V5.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q26, Q4, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q16, Q19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V29.2D, V16.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V21.2D, V19.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q29, Q21, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q22, Q20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V30.2D, V22.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V27.2D, V20.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q30, Q27, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q18, Q17, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V0.2D, V18.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V28.2D, V17.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q0, Q28, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a17c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
AND X13, X1, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS XZR, X1, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a1b4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X13, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X14, X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z23.D, Z31.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P7.D, XZR, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X1, X20, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z16.D}, P7/Z, [X20, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FMUL Z19.D, Z16.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z19.D}, P7, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P0.D, X5, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B.NE 45aa04 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x12c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X13, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X13, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45a3a8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X14, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X8, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 45aa80 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X1, X14, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X19, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V27.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X5, X1, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X13, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X8, X5, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X0, X1,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X1, X8, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X8, X5, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45a2d0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a2b4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a2a0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a28c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a278 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a264 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a250 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q22, [X19, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR Q18, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMUL V20.2D, V22.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V0.2D, V18.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STR Q20, [X19, X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STUR Q0, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP Q28, Q30, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V1.2D, V28.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V25.2D, V30.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q1, Q25, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q6, Q17, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V7.2D, V6.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V26.2D, V17.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q7, Q26, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q5, Q2, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V3.2D, V5.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V4.2D, V2.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q3, Q4, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q24, Q23, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V16.2D, V24.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V19.2D, V23.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q16, Q19, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q29, Q21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V22.2D, V29.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V20.2D, V21.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q22, Q20, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q18, Q0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V28.2D, V18.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V30.2D, V0.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q28, Q30, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a370 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
AND X0, X14, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS XZR, X14, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a3a8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X14, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z27.D, Z31.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P1.D, XZR, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X13, X19, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z24.D}, P1/Z, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FMUL Z23.D, Z24.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z23.D}, P1, [X13, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P2.D, X4, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B.NE 45a9f0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x12b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X1, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4599e0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 459e20 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 459e60 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x720>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z19.D}, P2/Z, [X13, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
INCB X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMUL Z29.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z29.D}, P2, [X13, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 45a3a8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z29.D}, P0/Z, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
INCB X1, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMUL Z21.D, Z23.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z21.D}, P0, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 45a1b4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 459d2c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x5ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 459b38 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45a188 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45a37c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source file and lines	par_multi_interp.c:1774-1876
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

37% of VPU instructions are used in vector version (process two or more data elements in vector registers):

62% of VPU loads are used in vector version.
23% of VPU stores are used in vector version.
96% of VPU multiply instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
7% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 74 FP arithmetical operations:

73: multiply
1: divide

The binary loop is loading 128 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	435
nb uops	431
loop length	1740
used w registers	0
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	5
used q registers	23
used v registers	24
used z registers	8
nb stack references	72

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	53.88 cycles
front end	53.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	29.00	29.00	35.25	35.25	35.25	35.25	15.50	15.50	15.50	15.50	63.33	63.33	63.33	32.00	32.00
cycles	29.00	29.00	35.25	35.25	35.25	35.25	15.50	15.50	15.50	15.50	63.33	63.33	63.33	32.00	32.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	53.88
Dispatch	63.33
DIV/SQRT	1.75-3.50
Overall L1	63.33

Vectorization ratios

INT

all	26%
load	62%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	86%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	96%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	37%
load	62%
store	23%
mul	96%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	45%
load	73%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	52%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	55%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	47%
load	73%
store	46%
mul	55%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 63.33 cycles. At this rate:

2% of peak load performance is reached (2.02 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.02 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4599e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X0, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X4, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X1, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X16, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X16, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459bec <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X1, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X13, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X5, X5, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X1, XZR, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 45aa64 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459b08 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459af0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459ad8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459ac0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459aa8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459a90 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459bec <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X5, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X9, X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X13, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X0, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X13, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459de0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X13, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X13, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X1, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X5, X5, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD X1, X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 45aa50 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459cfc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x5bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459ce4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x5a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459ccc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459cb4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x574>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459c9c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x55c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459c84 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X0, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 459de0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X5, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X9, X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X0, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X0, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X0, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459e20 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X0, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X0, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X0, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459e60 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x720>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X14, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D29, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X1, [X14, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459f04 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x7c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X15, X28, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X15, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X9, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 459eb4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x774>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X6, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X17, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X15, X28, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X5, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X5, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 459fa4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x864>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X26, X28, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X24, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X1, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X24, X25, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 459f50 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x810>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X26, X28, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X24, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X1, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D21, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D22, D29, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMP D22, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 459fbc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x87c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FNEG D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FDIV D31, D20, D22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR X3, [X16, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X16, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45a1b4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X1, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 45aa78 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X5, X1, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X20, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V23.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X13, X5, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X14, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X13, X13, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X0, X5,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X13, X13, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X13, X13, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45a0d4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a0b8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x978>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a0a4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a090 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x950>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a07c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x93c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a068 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a054 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x914>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X20, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR Q18, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMUL V27.2D, V30.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V17.2D, V18.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STR Q27, [X20, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STUR Q17, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP Q0, Q28, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V1.2D, V0.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V25.2D, V28.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q1, Q25, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q24, Q7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V2.2D, V24.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V6.2D, V7.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q2, Q6, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q3, Q5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V26.2D, V3.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V4.2D, V5.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q26, Q4, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q16, Q19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V29.2D, V16.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V21.2D, V19.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q29, Q21, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q22, Q20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V30.2D, V22.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V27.2D, V20.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q30, Q27, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q18, Q17, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V0.2D, V18.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V28.2D, V17.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q0, Q28, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a17c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
AND X13, X1, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS XZR, X1, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a1b4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X13, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X14, X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z23.D, Z31.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P7.D, XZR, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X1, X20, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z16.D}, P7/Z, [X20, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FMUL Z19.D, Z16.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z19.D}, P7, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P0.D, X5, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B.NE 45aa04 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x12c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X13, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X13, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45a3a8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X14, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X8, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 45aa80 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X1, X14, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X19, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V27.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X5, X1, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X13, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X8, X5, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X0, X1,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X1, X8, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X8, X5, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45a2d0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a2b4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a2a0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a28c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a278 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a264 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a250 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q22, [X19, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR Q18, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMUL V20.2D, V22.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V0.2D, V18.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STR Q20, [X19, X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STUR Q0, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP Q28, Q30, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V1.2D, V28.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V25.2D, V30.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q1, Q25, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q6, Q17, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V7.2D, V6.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V26.2D, V17.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q7, Q26, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q5, Q2, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V3.2D, V5.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V4.2D, V2.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q3, Q4, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q24, Q23, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V16.2D, V24.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V19.2D, V23.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q16, Q19, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q29, Q21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V22.2D, V29.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V20.2D, V21.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q22, Q20, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q18, Q0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V28.2D, V18.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V30.2D, V0.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q28, Q30, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a370 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
AND X0, X14, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS XZR, X14, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45a3a8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X14, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z27.D, Z31.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P1.D, XZR, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X13, X19, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z24.D}, P1/Z, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FMUL Z23.D, Z24.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z23.D}, P1, [X13, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P2.D, X4, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B.NE 45a9f0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x12b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X1, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4599e0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 459e20 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 459e60 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x720>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z19.D}, P2/Z, [X13, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
INCB X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMUL Z29.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z29.D}, P2, [X13, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 45a3a8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z29.D}, P0/Z, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
INCB X1, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMUL Z21.D, Z23.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z21.D}, P0, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 45a1b4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 459d2c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x5ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X26, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X28, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 459b38 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45a188 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45a37c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code