OV - exec - Loop 786

	Loop Id: 786	Module: exec	Source: par_multi_interp.c:554-557	Coverage: 0.01%

0x45d074 LDR	X18, [X20, X0,LSL #3]    [2]

0x45d078 ADD	X10, X0, #1

0x45d07c ADD	X16, X0, #3

0x45d080 ADD	X15, X0, #4

0x45d084 ADD	X14, X0, #5

0x45d088 ADD	X13, X0, #6

0x45d08c ADD	X17, X0, #7

0x45d090 ADD	X12, X10, #1

0x45d094 ADD	X0, X0, #8

0x45d098 LDR	X1, [X22, X18,LSL #3]    [1]

0x45d09c CMP	X1, X19

0x45d0a0 B.EQ	45d4e8

0x45d0a4 LDR	X10, [X20, X10,LSL #3]    [2]

0x45d0a8 LDR	X18, [X22, X10,LSL #3]    [1]

0x45d0ac CMP	X18, X19

0x45d0b0 B.EQ	45d4e8

0x45d0b4 LDR	X12, [X20, X12,LSL #3]    [2]

0x45d0b8 LDR	X1, [X22, X12,LSL #3]    [1]

0x45d0bc CMP	X1, X19

0x45d0c0 B.EQ	45d4e8

0x45d0c4 LDR	X16, [X20, X16,LSL #3]    [2]

0x45d0c8 LDR	X10, [X22, X16,LSL #3]    [1]

0x45d0cc CMP	X10, X19

0x45d0d0 B.EQ	45d4e8

0x45d0d4 LDR	X15, [X20, X15,LSL #3]    [2]

0x45d0d8 LDR	X18, [X22, X15,LSL #3]    [1]

0x45d0dc CMP	X18, X19

0x45d0e0 B.EQ	45d4e8

0x45d0e4 LDR	X14, [X20, X14,LSL #3]    [2]

0x45d0e8 LDR	X12, [X22, X14,LSL #3]    [1]

0x45d0ec CMP	X12, X19

0x45d0f0 B.EQ	45d4e8

0x45d0f4 LDR	X13, [X20, X13,LSL #3]    [2]

0x45d0f8 LDR	X1, [X22, X13,LSL #3]    [1]

0x45d0fc CMP	X1, X19

0x45d100 B.EQ	45d4e8

0x45d104 LDR	X17, [X20, X17,LSL #3]    [2]

0x45d108 LDR	X16, [X22, X17,LSL #3]    [1]

0x45d10c CMP	X16, X19

0x45d110 B.EQ	45d4e8

0x45d114 CMP	X0, X3

0x45d118 B.NE	45d074

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 554 - 557

--------------------------------------------------------------------------------

554:          for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

555:          {

556:             j1 = S_diag_j[j];

557:             if (assigned[j1] == pass-1)

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:554-557
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.33
Front-end cycles	5.25
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	4.25
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.33
P11 cycles	5.33
P12 cycles	5.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:554-557
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.33
Front-end cycles	5.25
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	4.25
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.33
P11 cycles	5.33
P12 cycles	5.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:554-557
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:554-557.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 1.33 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	42
nb uops	42
loop length	168
used w registers	0
used x registers	14
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	0.00	0.00
cycles	4.50	4.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Dispatch	5.33
Data deps.	1.00
Overall L1	5.33

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45d074

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR X18, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X10, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X16, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X15, X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X14, X0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X13, X0, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X17, X0, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X12, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X1, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X20, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X20, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X1, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X10, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X10, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X12, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X1, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X16, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X16, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
B.NE 45d074 <hypre_BoomerAMGBuildMultipass+0xe94>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:554-557
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 1.33 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	42
nb uops	42
loop length	168
used w registers	0
used x registers	14
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	0.00	0.00
cycles	4.50	4.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Dispatch	5.33
Data deps.	1.00
Overall L1	5.33

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45d074

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR X18, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X10, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X16, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X15, X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X14, X0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X13, X0, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X17, X0, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X12, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X1, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X20, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X20, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X1, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X10, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X10, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X12, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X12, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X1, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X16, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X16, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 45d4e8 <hypre_BoomerAMGBuildMultipass+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
B.NE 45d074 <hypre_BoomerAMGBuildMultipass+0xe94>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code