OV - exec - Loop 796

	Loop Id: 796	Module: exec	Source: par_multi_interp.c:385-410	Coverage: 0.01%

0x45c790 CMN	X9, #1

0x45c794 B.EQ	460880

0x45c798 STR	XZR, [X2, X0,LSL #3]    [7]

0x45c79c STR	XZR, [X4, X0,LSL #3]    [8]

0x45c7a0 STR	X13, [X22, X0,LSL #3]    [3]

0x45c7a4 STR	X13, [X15, X0,LSL #3]    [4]

0x45c7a8 ADD	X0, X0, #1

0x45c7ac LDR	X8, [X16, X0,LSL #3]    [5]

0x45c7b0 CMP	X8, #1

0x45c7b4 B.EQ	45c864

0x45c7b8 CMN	X8, #1

0x45c7bc B.EQ	460864

0x45c7c0 STR	XZR, [X2, X0,LSL #3]    [7]

0x45c7c4 STR	XZR, [X4, X0,LSL #3]    [8]

0x45c7c8 STR	X13, [X22, X0,LSL #3]    [3]

0x45c7cc STR	X13, [X15, X0,LSL #3]    [4]

0x45c7d0 ADD	X7, X0, #1

0x45c7d4 LDR	X10, [X16, X7,LSL #3]    [5]

0x45c7d8 CMP	X10, #1

0x45c7dc B.EQ	45c88c

0x45c7e0 CMN	X10, #1

0x45c7e4 B.EQ	460848

0x45c7e8 STR	XZR, [X2, X7,LSL #3]    [7]

0x45c7ec STR	XZR, [X4, X7,LSL #3]    [8]

0x45c7f0 STR	X13, [X22, X7,LSL #3]    [3]

0x45c7f4 STR	X13, [X15, X7,LSL #3]    [4]

0x45c7f8 ADD	X11, X0, #2

0x45c7fc LDR	X12, [X16, X11,LSL #3]    [5]

0x45c800 CMP	X12, #1

0x45c804 B.EQ	45c8b4

0x45c808 CMN	X12, #1

0x45c80c B.EQ	46082c

0x45c810 STR	XZR, [X2, X11,LSL #3]    [7]

0x45c814 STR	XZR, [X4, X11,LSL #3]    [8]

0x45c818 STR	X13, [X22, X11,LSL #3]    [3]

0x45c81c STR	X13, [X15, X11,LSL #3]    [4]

0x45c820 LDR	X14, [SP, #312]    [1]

0x45c824 ADD	X0, X0, #3

0x45c828 CMP	X14, X0

0x45c82c B.EQ	45c8dc

0x45c830 LDR	X9, [X16, X0,LSL #3]    [5]

0x45c834 CMP	X9, #1

0x45c838 B.NE	45c790

0x45c83c STR	X1, [X15, X0,LSL #3]    [4]

0x45c840 STR	X0, [X17, X1,LSL #3]    [6]

0x45c844 ADD	X1, X1, #1

0x45c848 STR	XZR, [X22, X0,LSL #3]    [3]

0x45c84c STR	X9, [X2, X0,LSL #3]    [7]

0x45c850 STR	XZR, [X4, X0,LSL #3]    [8]

0x45c854 ADD	X0, X0, #1

0x45c858 LDR	X8, [X16, X0,LSL #3]    [5]

0x45c85c CMP	X8, #1

0x45c860 B.NE	45c7b8

0x45c864 STR	X1, [X15, X0,LSL #3]    [4]

0x45c868 ADD	X7, X0, #1

0x45c86c STR	X0, [X17, X1,LSL #3]    [6]

0x45c870 ADD	X1, X1, #1

0x45c874 STR	XZR, [X22, X0,LSL #3]    [3]

0x45c878 STR	X8, [X2, X0,LSL #3]    [7]

0x45c87c STR	XZR, [X4, X0,LSL #3]    [8]

0x45c880 LDR	X10, [X16, X7,LSL #3]    [5]

0x45c884 CMP	X10, #1

0x45c888 B.NE	45c7e0

0x45c88c STR	X1, [X15, X7,LSL #3]    [4]

0x45c890 ADD	X11, X0, #2

0x45c894 STR	X7, [X17, X1,LSL #3]    [6]

0x45c898 ADD	X1, X1, #1

0x45c89c STR	XZR, [X22, X7,LSL #3]    [3]

0x45c8a0 STR	X10, [X2, X7,LSL #3]    [7]

0x45c8a4 STR	XZR, [X4, X7,LSL #3]    [8]

0x45c8a8 LDR	X12, [X16, X11,LSL #3]    [5]

0x45c8ac CMP	X12, #1

0x45c8b0 B.NE	45c808

0x45c8b4 LDR	X14, [SP, #312]    [1]

0x45c8b8 ADD	X0, X0, #3

0x45c8bc STR	X1, [X15, X11,LSL #3]    [4]

0x45c8c0 STR	X11, [X17, X1,LSL #3]    [6]

0x45c8c4 ADD	X1, X1, #1

0x45c8c8 STR	XZR, [X22, X11,LSL #3]    [3]

0x45c8cc STR	X12, [X2, X11,LSL #3]    [7]

0x45c8d0 STR	XZR, [X4, X11,LSL #3]    [8]

0x45c8d4 CMP	X14, X0

0x45c8d8 B.NE	45c830

0x46082c STR	X11, [X30, X3,LSL #3]    [2]

0x460830 SUB	X3, X3, #1

0x460834 STR	XZR, [X2, X11,LSL #3]    [7]

0x460838 STR	XZR, [X4, X11,LSL #3]    [8]

0x46083c STR	X12, [X22, X11,LSL #3]    [3]

0x460840 STR	X12, [X15, X11,LSL #3]    [4]

0x460844 B	45c820

0x460848 STR	X7, [X30, X3,LSL #3]    [2]

0x46084c SUB	X3, X3, #1

0x460850 STR	XZR, [X2, X7,LSL #3]    [7]

0x460854 STR	XZR, [X4, X7,LSL #3]    [8]

0x460858 STR	X10, [X22, X7,LSL #3]    [3]

0x46085c STR	X10, [X15, X7,LSL #3]    [4]

0x460860 B	45c7f8

0x460864 STR	X0, [X30, X3,LSL #3]    [2]

0x460868 SUB	X3, X3, #1

0x46086c STR	XZR, [X2, X0,LSL #3]    [7]

0x460870 STR	XZR, [X4, X0,LSL #3]    [8]

0x460874 STR	X8, [X22, X0,LSL #3]    [3]

0x460878 STR	X8, [X15, X0,LSL #3]    [4]

0x46087c B	45c7d0

0x460880 STR	X0, [X30, X3,LSL #3]    [2]

0x460884 SUB	X3, X3, #1

0x460888 STR	XZR, [X2, X0,LSL #3]    [7]

0x46088c STR	XZR, [X4, X0,LSL #3]    [8]

0x460890 STR	X9, [X22, X0,LSL #3]    [3]

0x460894 STR	X9, [X15, X0,LSL #3]    [4]

0x460898 B	45c7a8

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 385 - 410

--------------------------------------------------------------------------------

385:    for (i = 0; i < n_fine; i++)

386:    {

387:       if (CF_marker[i] == 1)

388:       {

389:          fine_to_coarse[i] = cnt; /* this C point is assigned index

390:                                      coarse_counter on coarse grid,

391:                                      and in column of P */

392:          C_array[cnt++] = i;

393:          assigned[i] = 0;

394:          P_diag_i[i+1] = 1; /* one element in row i1 of P */

395:          P_offd_i[i+1] = 0;

396:       }

397:       else if (CF_marker[i] == -1)

398:       {

399:          pass_array[p_cnt--] = i;

400:          P_diag_i[i+1] = 0;

401:          P_offd_i[i+1] = 0;

402:          assigned[i] = -1;

403:          fine_to_coarse[i] = -1;

404:       }

405:       else

406:       {

407:          P_diag_i[i+1] = 0;

408:          P_offd_i[i+1] = 0;

409:          assigned[i] = -1;

410:          fine_to_coarse[i] = -1;

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.02
Bottlenecks	P10, P11, P13, P14,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:385-410
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	28.00
CQA cycles if FP arith vectorized	28.00
CQA cycles if fully vectorized	7.00
Front-end cycles	13.88
P0 cycles	8.50
P1 cycles	8.50
P2 cycles	7.25
P3 cycles	7.25
P4 cycles	7.25
P5 cycles	7.25
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	28.00
P11 cycles	28.00
P12 cycles	9.00
P13 cycles	28.00
P14 cycles	28.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	111.00
Nb uops	111.00
Nb loads	NA
Nb stores	56.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.02
Bottlenecks	P10, P11, P13, P14,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:385-410
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	28.00
CQA cycles if FP arith vectorized	28.00
CQA cycles if fully vectorized	7.00
Front-end cycles	13.88
P0 cycles	8.50
P1 cycles	8.50
P2 cycles	7.25
P3 cycles	7.25
P4 cycles	7.25
P5 cycles	7.25
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	28.00
P11 cycles	28.00
P12 cycles	9.00
P13 cycles	28.00
P14 cycles	28.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	111.00
Nb uops	111.00
Nb loads	NA
Nb stores	56.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:385-410
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:385-410.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 81 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 28.00 to 7.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	111
nb uops	111
loop length	444
used w registers	0
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.88 cycles
front end	13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00
cycles	8.50	8.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Dispatch	28.00
Overall L1	28.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45c830

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMN X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460880 <hypre_BoomerAMGBuildMultipass+0x46a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X8, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c864 <hypre_BoomerAMGBuildMultipass+0x684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460864 <hypre_BoomerAMGBuildMultipass+0x4684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X10, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c88c <hypre_BoomerAMGBuildMultipass+0x6ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460848 <hypre_BoomerAMGBuildMultipass+0x4668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X11, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X16, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c8b4 <hypre_BoomerAMGBuildMultipass+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 46082c <hypre_BoomerAMGBuildMultipass+0x464c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [SP, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c8dc <hypre_BoomerAMGBuildMultipass+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45c790 <hypre_BoomerAMGBuildMultipass+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X8, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45c7b8 <hypre_BoomerAMGBuildMultipass+0x5d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45c7e0 <hypre_BoomerAMGBuildMultipass+0x600>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X11, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X7, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X16, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45c808 <hypre_BoomerAMGBuildMultipass+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X1, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X22, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [X2, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45c830 <hypre_BoomerAMGBuildMultipass+0x650>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X11, [X30, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [X22, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c820 <hypre_BoomerAMGBuildMultipass+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X7, [X30, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c7f8 <hypre_BoomerAMGBuildMultipass+0x618>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X30, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c7d0 <hypre_BoomerAMGBuildMultipass+0x5f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X30, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c7a8 <hypre_BoomerAMGBuildMultipass+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:385-410
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	111
nb uops	111
loop length	444
used w registers	0
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.88 cycles
front end	13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00
cycles	8.50	8.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Dispatch	28.00
Overall L1	28.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45c830

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMN X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460880 <hypre_BoomerAMGBuildMultipass+0x46a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X8, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c864 <hypre_BoomerAMGBuildMultipass+0x684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460864 <hypre_BoomerAMGBuildMultipass+0x4684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X10, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c88c <hypre_BoomerAMGBuildMultipass+0x6ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 460848 <hypre_BoomerAMGBuildMultipass+0x4668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X11, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X16, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c8b4 <hypre_BoomerAMGBuildMultipass+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 46082c <hypre_BoomerAMGBuildMultipass+0x464c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [SP, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45c8dc <hypre_BoomerAMGBuildMultipass+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45c790 <hypre_BoomerAMGBuildMultipass+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X8, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45c7b8 <hypre_BoomerAMGBuildMultipass+0x5d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X0, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45c7e0 <hypre_BoomerAMGBuildMultipass+0x600>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X11, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X7, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X16, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45c808 <hypre_BoomerAMGBuildMultipass+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X1, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X22, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [X2, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45c830 <hypre_BoomerAMGBuildMultipass+0x650>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X11, [X30, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [X22, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c820 <hypre_BoomerAMGBuildMultipass+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X7, [X30, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c7f8 <hypre_BoomerAMGBuildMultipass+0x618>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X30, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c7d0 <hypre_BoomerAMGBuildMultipass+0x5f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X30, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c7a8 <hypre_BoomerAMGBuildMultipass+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code