OV - exec - Function hypre_BoomerAMGCreate2ndS._omp

	Function: hypre_BoomerAMGCreate2ndS._omp_fn.0	Module: exec	Source: par_strength.c:1253-1278	Coverage (incl. loops): 0.04% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1253 - 1278

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1253: #pragma omp parallel private(i)

1254: #endif

1255:    {

1256:       HYPRE_Int num_coarse_private = 0;

1257:

1258:       HYPRE_Int i_begin, i_end;

1259:       hypre_GetSimpleThreadPartition(&i_begin, &i_end, num_cols_diag_S);

1260:

1261:       for (i = i_begin; i < i_end; i++)

1262:       {

1263:          if (CF_marker[i] > 0) num_coarse_private++;

1264:       }

1265:

1266:       hypre_prefix_sum(&num_coarse_private, &num_coarse, num_coarse_prefix_sum);

1267:

1268:       for (i = i_begin; i < i_end; i++)

1269:       {

1270:          if (CF_marker[i] > 0)

1271:          {

1272:             fine_to_coarse[i] = num_coarse_private;

1273:             coarse_to_fine[num_coarse_private] = i;

1274:             num_coarse_private++;

1275:          }

1276:          else

1277:          {

1278:             fine_to_coarse[i] = -1;

0x4b5820 STP	X29, X30, [SP, #928]!

0x4b5824 ADD	X29, SP, #0

0x4b5828 ADD	X1, SP, #88

0x4b582c STP	X21, X22, [SP, #32]

0x4b5830 ORR	X22, XZR, X0

0x4b5834 ADD	X0, SP, #80

0x4b5838 STP	X19, X20, [SP, #16]

0x4b583c LDP	X19, X2, [X22]

0x4b5840 STR	XZR, [SP, #72]

0x4b5844 LDR	X21, [X22, #16]

0x4b5848 LDR	X20, [X22, #32]

0x4b584c STR	X23, [SP, #48]

0x4b5850 LDR	X23, [X22, #40]

0x4b5854 BL	52c0c0

0x4b5858 LDP	X1, X4, [SP, #80]

0x4b585c CMP	X1, X4

0x4b5860 B.GE	4b5a24

0x4b5864 ADD	X18, X19, X1,LSL #3

0x4b5868 MOVZ	W0, #0

0x4b586c ADD	X5, X19, X4,LSL #3

0x4b5870 SUB	X3, X5, X18

0x4b5874 SUB	X2, X3, #8

0x4b5878 UBFM	X6, X2, #3, #63

0x4b587c LDR	X2, [SP, #72]

0x4b5880 ADD	X7, X6, #1

0x4b5884 ANDS	X8, X7, #0x7

0x4b5888 B.EQ	4b596c

0x4b588c CMP	X8, #1

0x4b5890 B.EQ	4b594c

0x4b5894 CMP	X8, #2

0x4b5898 B.EQ	4b5934

0x4b589c CMP	X8, #3

0x4b58a0 B.EQ	4b591c

0x4b58a4 CMP	X8, #4

0x4b58a8 B.EQ	4b5904

0x4b58ac CMP	X8, #5

0x4b58b0 B.EQ	4b58ec

0x4b58b4 CMP	X8, #6

0x4b58b8 B.EQ	4b58d4

0x4b58bc LDR	X9, [X18]

0x4b58c0 CMP	X9, #0

0x4b58c4 B.LE	4b58d0

0x4b58c8 ADD	X2, X2, #1

0x4b58cc MOVZ	W0, #1

0x4b58d0 ADD	X18, X18, #8

0x4b58d4 LDR	X10, [X18]

0x4b58d8 CMP	X10, #0

0x4b58dc B.LE	4b58e8

0x4b58e0 ADD	X2, X2, #1

0x4b58e4 MOVZ	W0, #1

0x4b58e8 ADD	X18, X18, #8

0x4b58ec LDR	X11, [X18]

0x4b58f0 CMP	X11, #0

0x4b58f4 B.LE	4b5900

0x4b58f8 ADD	X2, X2, #1

0x4b58fc MOVZ	W0, #1

0x4b5900 ADD	X18, X18, #8

0x4b5904 LDR	X12, [X18]

0x4b5908 CMP	X12, #0

0x4b590c B.LE	4b5918

0x4b5910 ADD	X2, X2, #1

0x4b5914 MOVZ	W0, #1

0x4b5918 ADD	X18, X18, #8

0x4b591c LDR	X13, [X18]

0x4b5920 CMP	X13, #0

0x4b5924 B.LE	4b5930

0x4b5928 ADD	X2, X2, #1

0x4b592c MOVZ	W0, #1

0x4b5930 ADD	X18, X18, #8

0x4b5934 LDR	X14, [X18]

0x4b5938 CMP	X14, #0

0x4b593c B.LE	4b5948

0x4b5940 ADD	X2, X2, #1

0x4b5944 MOVZ	W0, #1

0x4b5948 ADD	X18, X18, #8

0x4b594c LDR	X15, [X18]

0x4b5950 CMP	X15, #0

0x4b5954 B.LE	4b5960

0x4b5958 ADD	X2, X2, #1

0x4b595c MOVZ	W0, #1

0x4b5960 ADD	X18, X18, #8

0x4b5964 CMP	X18, X5

0x4b5968 B.EQ	4b5a1c

(2062) 0x4b596c LDR	X16, [X18]

(2062) 0x4b5970 CMP	X16, #0

(2062) 0x4b5974 B.LE	4b5980

(2062) 0x4b5978 ADD	X2, X2, #1

(2062) 0x4b597c MOVZ	W0, #1

(2062) 0x4b5980 LDR	X17, [X18, #8]

(2062) 0x4b5984 ADD	X18, X18, #8

(2062) 0x4b5988 CMP	X17, #0

(2062) 0x4b598c B.LE	4b5998

(2062) 0x4b5990 ADD	X2, X2, #1

(2062) 0x4b5994 MOVZ	W0, #1

(2062) 0x4b5998 LDR	X30, [X18, #8]

(2062) 0x4b599c CMP	X30, #0

(2062) 0x4b59a0 B.LE	4b59ac

(2062) 0x4b59a4 ADD	X2, X2, #1

(2062) 0x4b59a8 MOVZ	W0, #1

(2062) 0x4b59ac LDR	X1, [X18, #16]

(2062) 0x4b59b0 CMP	X1, #0

(2062) 0x4b59b4 B.LE	4b59c0

(2062) 0x4b59b8 ADD	X2, X2, #1

(2062) 0x4b59bc MOVZ	W0, #1

(2062) 0x4b59c0 LDR	X4, [X18, #24]

(2062) 0x4b59c4 CMP	X4, #0

(2062) 0x4b59c8 B.LE	4b59d4

(2062) 0x4b59cc ADD	X2, X2, #1

(2062) 0x4b59d0 MOVZ	W0, #1

(2062) 0x4b59d4 LDR	X3, [X18, #32]

(2062) 0x4b59d8 CMP	X3, #0

(2062) 0x4b59dc B.LE	4b59e8

(2062) 0x4b59e0 ADD	X2, X2, #1

(2062) 0x4b59e4 MOVZ	W0, #1

(2062) 0x4b59e8 LDR	X6, [X18, #40]

(2062) 0x4b59ec CMP	X6, #0

(2062) 0x4b59f0 B.LE	4b59fc

(2062) 0x4b59f4 ADD	X2, X2, #1

(2062) 0x4b59f8 MOVZ	W0, #1

(2062) 0x4b59fc LDR	X7, [X18, #48]

(2062) 0x4b5a00 CMP	X7, #0

(2062) 0x4b5a04 B.LE	4b5a10

(2062) 0x4b5a08 ADD	X2, X2, #1

(2062) 0x4b5a0c MOVZ	W0, #1

(2062) 0x4b5a10 ADD	X18, X18, #56

(2062) 0x4b5a14 CMP	X18, X5

(2062) 0x4b5a18 B.NE	4b596c

0x4b5a1c CBZ	W0, 4b5a24

0x4b5a20 STR	X2, [SP, #72]

0x4b5a24 LDR	X1, [X22, #24]

0x4b5a28 ORR	X2, XZR, X20

0x4b5a2c ADD	X0, SP, #72

0x4b5a30 BL	52d060

0x4b5a34 LDP	X4, X8, [SP, #80]

0x4b5a38 CMP	X4, X8

0x4b5a3c B.GE	4b5b50

0x4b5a40 SUB	X5, X8, X4

0x4b5a44 LDR	X1, [SP, #72]

0x4b5a48 MOVN	X9, #0

0x4b5a4c ANDS	X10, X5, #0x7

0x4b5a50 B.EQ	4b5c40

0x4b5a54 CMP	X10, #1

0x4b5a58 B.EQ	4b5b2c

0x4b5a5c CMP	X10, #2

0x4b5a60 B.EQ	4b5b10

0x4b5a64 CMP	X10, #3

0x4b5a68 B.EQ	4b5af4

0x4b5a6c CMP	X10, #4

0x4b5a70 B.EQ	4b5ad8

0x4b5a74 CMP	X10, #5

0x4b5a78 B.EQ	4b5abc

0x4b5a7c CMP	X10, #6

0x4b5a80 B.EQ	4b5aa0

0x4b5a84 LDR	X11, [X19, X4,LSL #3]

0x4b5a88 CMP	X11, #0

0x4b5a8c B.LE	4b5d24

0x4b5a90 STR	X1, [X21, X4,LSL #3]

0x4b5a94 STR	X4, [X23, X1,LSL #3]

0x4b5a98 ADD	X1, X1, #1

0x4b5a9c ADD	X4, X4, #1

0x4b5aa0 LDR	X12, [X19, X4,LSL #3]

0x4b5aa4 CMP	X12, #0

0x4b5aa8 B.LE	4b5d0c

0x4b5aac STR	X1, [X21, X4,LSL #3]

0x4b5ab0 STR	X4, [X23, X1,LSL #3]

0x4b5ab4 ADD	X1, X1, #1

0x4b5ab8 ADD	X4, X4, #1

0x4b5abc LDR	X13, [X19, X4,LSL #3]

0x4b5ac0 CMP	X13, #0

0x4b5ac4 B.LE	4b5d00

0x4b5ac8 STR	X1, [X21, X4,LSL #3]

0x4b5acc STR	X4, [X23, X1,LSL #3]

0x4b5ad0 ADD	X1, X1, #1

0x4b5ad4 ADD	X4, X4, #1

0x4b5ad8 LDR	X14, [X19, X4,LSL #3]

0x4b5adc CMP	X14, #0

0x4b5ae0 B.LE	4b5d18

0x4b5ae4 STR	X1, [X21, X4,LSL #3]

0x4b5ae8 STR	X4, [X23, X1,LSL #3]

0x4b5aec ADD	X1, X1, #1

0x4b5af0 ADD	X4, X4, #1

0x4b5af4 LDR	X15, [X19, X4,LSL #3]

0x4b5af8 CMP	X15, #0

0x4b5afc B.LE	4b5cf4

0x4b5b00 STR	X1, [X21, X4,LSL #3]

0x4b5b04 STR	X4, [X23, X1,LSL #3]

0x4b5b08 ADD	X1, X1, #1

0x4b5b0c ADD	X4, X4, #1

0x4b5b10 LDR	X16, [X19, X4,LSL #3]

0x4b5b14 CMP	X16, #0

0x4b5b18 B.LE	4b5ce8

0x4b5b1c STR	X1, [X21, X4,LSL #3]

0x4b5b20 STR	X4, [X23, X1,LSL #3]

0x4b5b24 ADD	X1, X1, #1

0x4b5b28 ADD	X4, X4, #1

0x4b5b2c LDR	X17, [X19, X4,LSL #3]

0x4b5b30 CMP	X17, #0

0x4b5b34 B.LE	4b5ce0

0x4b5b38 STR	X1, [X21, X4,LSL #3]

0x4b5b3c STR	X4, [X23, X1,LSL #3]

0x4b5b40 ADD	X1, X1, #1

0x4b5b44 ADD	X4, X4, #1

0x4b5b48 CMP	X8, X4

0x4b5b4c B.NE	4b5c40

0x4b5b50 LDR	X23, [SP, #48]

0x4b5b54 LDP	X19, X20, [SP, #16]

0x4b5b58 LDP	X21, X22, [SP, #32]

0x4b5b5c LDP	X29, X30, [SP], #96

0x4b5b60 RET

(2061) 0x4b5b64 STR	X1, [X21, X4,LSL #3]

(2061) 0x4b5b68 STR	X4, [X23, X1,LSL #3]

(2061) 0x4b5b6c ADD	X4, X4, #1

(2061) 0x4b5b70 ADD	X1, X1, #1

(2061) 0x4b5b74 LDR	X3, [X19, X4,LSL #3]

(2061) 0x4b5b78 CMP	X3, #0

(2061) 0x4b5b7c B.LE	4b5c60

(2061) 0x4b5b80 ADD	X6, X4, #1

(2061) 0x4b5b84 STR	X1, [X21, X4,LSL #3]

(2061) 0x4b5b88 STR	X4, [X23, X1,LSL #3]

(2061) 0x4b5b8c ADD	X1, X1, #1

(2061) 0x4b5b90 LDR	X7, [X19, X6,LSL #3]

(2061) 0x4b5b94 CMP	X7, #0

(2061) 0x4b5b98 B.LE	4b5c74

(2061) 0x4b5b9c ADD	X2, X4, #2

(2061) 0x4b5ba0 STR	X1, [X21, X6,LSL #3]

(2061) 0x4b5ba4 STR	X6, [X23, X1,LSL #3]

(2061) 0x4b5ba8 ADD	X1, X1, #1

(2061) 0x4b5bac LDR	X0, [X19, X2,LSL #3]

(2061) 0x4b5bb0 CMP	X0, #0

(2061) 0x4b5bb4 B.LE	4b5c88

(2061) 0x4b5bb8 ADD	X18, X4, #3

(2061) 0x4b5bbc STR	X1, [X21, X2,LSL #3]

(2061) 0x4b5bc0 STR	X2, [X23, X1,LSL #3]

(2061) 0x4b5bc4 ADD	X1, X1, #1

(2061) 0x4b5bc8 LDR	X20, [X19, X18,LSL #3]

(2061) 0x4b5bcc CMP	X20, #0

(2061) 0x4b5bd0 B.LE	4b5c9c

(2061) 0x4b5bd4 ADD	X22, X4, #4

(2061) 0x4b5bd8 STR	X1, [X21, X18,LSL #3]

(2061) 0x4b5bdc STR	X18, [X23, X1,LSL #3]

(2061) 0x4b5be0 ADD	X1, X1, #1

(2061) 0x4b5be4 LDR	X5, [X19, X22,LSL #3]

(2061) 0x4b5be8 CMP	X5, #0

(2061) 0x4b5bec B.LE	4b5cb0

(2061) 0x4b5bf0 ADD	X10, X4, #5

(2061) 0x4b5bf4 STR	X1, [X21, X22,LSL #3]

(2061) 0x4b5bf8 STR	X22, [X23, X1,LSL #3]

(2061) 0x4b5bfc ADD	X1, X1, #1

(2061) 0x4b5c00 LDR	X11, [X19, X10,LSL #3]

(2061) 0x4b5c04 CMP	X11, #0

(2061) 0x4b5c08 B.LE	4b5cc4

(2061) 0x4b5c0c ADD	X12, X4, #6

(2061) 0x4b5c10 STR	X1, [X21, X10,LSL #3]

(2061) 0x4b5c14 STR	X10, [X23, X1,LSL #3]

(2061) 0x4b5c18 ADD	X1, X1, #1

(2061) 0x4b5c1c LDR	X13, [X19, X12,LSL #3]

(2061) 0x4b5c20 CMP	X13, #0

(2061) 0x4b5c24 B.LE	4b5cd8

(2061) 0x4b5c28 STR	X1, [X21, X12,LSL #3]

(2061) 0x4b5c2c STR	X12, [X23, X1,LSL #3]

(2061) 0x4b5c30 ADD	X1, X1, #1

(2061) 0x4b5c34 ADD	X4, X4, #7

(2061) 0x4b5c38 CMP	X8, X4

(2061) 0x4b5c3c B.EQ	4b5b50

(2061) 0x4b5c40 LDR	X30, [X19, X4,LSL #3]

(2061) 0x4b5c44 CMP	X30, #0

(2061) 0x4b5c48 B.GT	4b5b64

(2061) 0x4b5c4c STR	X9, [X21, X4,LSL #3]

(2061) 0x4b5c50 ADD	X4, X4, #1

(2061) 0x4b5c54 LDR	X3, [X19, X4,LSL #3]

(2061) 0x4b5c58 CMP	X3, #0

(2061) 0x4b5c5c B.GT	4b5b80

(2061) 0x4b5c60 ADD	X6, X4, #1

(2061) 0x4b5c64 STR	X9, [X21, X4,LSL #3]

(2061) 0x4b5c68 LDR	X7, [X19, X6,LSL #3]

(2061) 0x4b5c6c CMP	X7, #0

(2061) 0x4b5c70 B.GT	4b5b9c

(2061) 0x4b5c74 ADD	X2, X4, #2

(2061) 0x4b5c78 STR	X9, [X21, X6,LSL #3]

(2061) 0x4b5c7c LDR	X0, [X19, X2,LSL #3]

(2061) 0x4b5c80 CMP	X0, #0

(2061) 0x4b5c84 B.GT	4b5bb8

(2061) 0x4b5c88 ADD	X18, X4, #3

(2061) 0x4b5c8c STR	X9, [X21, X2,LSL #3]

(2061) 0x4b5c90 LDR	X20, [X19, X18,LSL #3]

(2061) 0x4b5c94 CMP	X20, #0

(2061) 0x4b5c98 B.GT	4b5bd4

(2061) 0x4b5c9c ADD	X22, X4, #4

(2061) 0x4b5ca0 STR	X9, [X21, X18,LSL #3]

(2061) 0x4b5ca4 LDR	X5, [X19, X22,LSL #3]

(2061) 0x4b5ca8 CMP	X5, #0

(2061) 0x4b5cac B.GT	4b5bf0

(2061) 0x4b5cb0 ADD	X10, X4, #5

(2061) 0x4b5cb4 STR	X9, [X21, X22,LSL #3]

(2061) 0x4b5cb8 LDR	X11, [X19, X10,LSL #3]

(2061) 0x4b5cbc CMP	X11, #0

(2061) 0x4b5cc0 B.GT	4b5c0c

(2061) 0x4b5cc4 ADD	X12, X4, #6

(2061) 0x4b5cc8 STR	X9, [X21, X10,LSL #3]

(2061) 0x4b5ccc LDR	X13, [X19, X12,LSL #3]

(2061) 0x4b5cd0 CMP	X13, #0

(2061) 0x4b5cd4 B.GT	4b5c28

(2061) 0x4b5cd8 STR	X9, [X21, X12,LSL #3]

(2061) 0x4b5cdc B	4b5c34

0x4b5ce0 STR	X9, [X21, X4,LSL #3]

0x4b5ce4 B	4b5b44

0x4b5ce8 STR	X9, [X21, X4,LSL #3]

0x4b5cec ADD	X4, X4, #1

0x4b5cf0 B	4b5b2c

0x4b5cf4 STR	X9, [X21, X4,LSL #3]

0x4b5cf8 ADD	X4, X4, #1

0x4b5cfc B	4b5b10

0x4b5d00 STR	X9, [X21, X4,LSL #3]

0x4b5d04 ADD	X4, X4, #1

0x4b5d08 B	4b5ad8

0x4b5d0c STR	X9, [X21, X4,LSL #3]

0x4b5d10 ADD	X4, X4, #1

0x4b5d14 B	4b5abc

0x4b5d18 STR	X9, [X21, X4,LSL #3]

0x4b5d1c ADD	X4, X4, #1

0x4b5d20 B	4b5af4

0x4b5d24 STR	X9, [X21, X4,LSL #3]

0x4b5d28 ADD	X4, X4, #1

0x4b5d2c B	4b5aa0

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCreate2ndS	par_strength.c:1283	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:622	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►56.52+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►43.48+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCreate2ndS	par_strength.c:1283	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:622	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►62.50+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►37.50+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCreate2ndS	par_strength.c:1283	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:622	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►91.30+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►8.70+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCreate2ndS	par_strength.c:1283	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:622	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►91.30+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►8.70+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCreate2ndS	par_strength.c:1283	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:622	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Source Location	Module
►88.24+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►11.76+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCreate2ndS	par_strength.c:1283	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:622	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Source Location	Module
►96.55+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.45+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCreate2ndS	par_strength.c:1283	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:622	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►97.56+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.44+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCreate2ndS	par_strength.c:1283	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:622	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►97.56+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.44+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCreate2ndS	par_strength.c:1283	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:622	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 23.13 to 4.47 cycles (5.17x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1259
hypre_prefix_sum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1266

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	185
nb uops	185
loop length	740
used w registers	1
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.13 cycles
front end	23.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	21.50	21.50	22.75	22.75	22.75	22.75	0.00	0.00	0.00	0.00	18.17	17.83	18.00	13.50	13.50
cycles	21.50	21.50	22.75	22.75	22.75	22.75	0.00	0.00	0.00	0.00	18.17	17.83	18.00	13.50	13.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.13
Dispatch	22.75
Overall L1	23.13

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	26%
store	27%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.13 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4b5820

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X2, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR XZR, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X22, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X22, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X23, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [X22, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 52c0c0 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X4, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4b5a24 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X19, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X5, X19, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X2, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X6, X2, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X2, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X7, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X8, X7, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b596c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b594c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5934 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b591c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5904 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b58ec <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b58d4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b58d0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X10, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b58e8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X11, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5900 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5918 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5930 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5948 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X15, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5960 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X18, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5a1c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 4b5a24 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X2, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X22, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
BL 52d060 <hypre_prefix_sum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X8, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4b5b50 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X8, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X10, X5, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5c40 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5b2c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5b10 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5af4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5ad8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5abc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5aa0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5d24 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5d0c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5d00 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5d18 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X15, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5cf4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5ce8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X17, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5ce0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X8, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b5c40 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 4b5b44 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b5b2c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b5b10 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b5ad8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b5abc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b5af4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b5aa0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1259
hypre_prefix_sum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1266

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	185
nb uops	185
loop length	740
used w registers	1
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.13 cycles
front end	23.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	21.50	21.50	22.75	22.75	22.75	22.75	0.00	0.00	0.00	0.00	18.17	17.83	18.00	13.50	13.50
cycles	21.50	21.50	22.75	22.75	22.75	22.75	0.00	0.00	0.00	0.00	18.17	17.83	18.00	13.50	13.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.13
Dispatch	22.75
Overall L1	23.13

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	26%
store	27%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.13 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4b5820

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X2, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR XZR, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X22, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X22, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X23, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [X22, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 52c0c0 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X4, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4b5a24 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X19, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X5, X19, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X2, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X6, X2, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X2, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X7, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X8, X7, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b596c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b594c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5934 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b591c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5904 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b58ec <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b58d4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b58d0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X10, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b58e8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X11, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5900 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5918 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5930 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5948 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X15, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5960 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X18, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5a1c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 4b5a24 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X2, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X22, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
BL 52d060 <hypre_prefix_sum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X8, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4b5b50 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X8, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X10, X5, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5c40 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5b2c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5b10 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5af4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5ad8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5abc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b5aa0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5d24 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5d0c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5d00 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5d18 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X15, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5cf4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5ce8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X17, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b5ce0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X8, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b5c40 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 4b5b44 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b5b2c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b5b10 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b5ad8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b5abc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b5af4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b5aa0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	2.18	0	3.9	0	7.34	0	13.85	0	16.99	0	35.03	0	24.03	0	30	0	25.04	0	28.14	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.13000001013279	0.037561468780041
1x2	2	2.18	2.18	2	0.064999997615814	0.031851403415203
1x4	4	3.9	3.9	4	0.045000001788139	0.03251039609313
1x8	8	7.34	7.34	8	0.024999998509884	0.028638947755098
1x16	13	13.85	13.85	16	0.019999999552965	0.017855748534203
1x24	17	16.99	16.99	24	0.02000000141561	0.015322309918702
1x32	14	35.03	35.03	32	0.010000000707805	0.0079418709501624
1x40	24	24.03	24.03	40	0.014999999664724	0.012248114682734
1x48	24	30	30	48	0.015000000596046	0.0097785266116261
1x56	33	25.04	25.04	56	0.010000000707805	0.011909077875316
1x64	38	28.14	28.14	64	0.0099999997764826	0.010400807484984

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreate2ndS._omp_fn.0–	0.04	0.13
○Loop 2061 - par_strength.c:1268-1278 - exec	0.02	0.08
○Loop 2062 - par_strength.c:1261-1263 - exec	0.02	0.06

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency