OV - exec - Function hypre_BoomerAMGCorrectCFMarker

	Function: hypre_BoomerAMGCorrectCFMarker	Module: exec	Source: par_strength.c:2310-2321	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 2310 - 2321

--------------------------------------------------------------------------------

2310:    cnt = 0;

2311:    for (i=0; i < num_var; i++)

2312:    {

2313:       if (CF_marker[i] > 0 )

2314:       {

2315:          if (CF_marker[i] == 1) CF_marker[i] = new_CF_marker[cnt++];

2316:          else { CF_marker[i] = 1; cnt++;}

2317:       }

2318:    }

2319:

2320:    return 0;

2321: }

0x4b9524 CMP	X1, #0

0x4b9528 B.LE	4b97a8

0x4b952c UBFM	X3, X1, #61, #60

0x4b9530 ADD	X5, X0, X1,LSL #3

0x4b9534 MOVZ	X4, #0

0x4b9538 SUB	X6, X3, #8

0x4b953c ORR	X1, XZR, X0

0x4b9540 UBFM	X7, X6, #3, #63

0x4b9544 ADD	X8, X7, #1

0x4b9548 ANDS	X9, X8, #0x7

0x4b954c B.EQ	4b9698

0x4b9550 CMP	X9, #1

0x4b9554 B.EQ	4b9668

0x4b9558 CMP	X9, #2

0x4b955c B.EQ	4b9640

0x4b9560 CMP	X9, #3

0x4b9564 B.EQ	4b9618

0x4b9568 CMP	X9, #4

0x4b956c B.EQ	4b95f4

0x4b9570 CMP	X9, #5

0x4b9574 B.EQ	4b95cc

0x4b9578 CMP	X9, #6

0x4b957c B.EQ	4b95a4

0x4b9580 LDR	X1, [X0]

0x4b9584 CMP	X1, #0

0x4b9588 B.LE	4b95a0

0x4b958c MOVZ	X10, #1

0x4b9590 CMP	X1, X10

0x4b9594 B.EQ	4b9838

0x4b9598 MOVZ	X4, #1

0x4b959c STR	X10, [X0]

0x4b95a0 ADD	X1, X0, #8

0x4b95a4 LDR	X0, [X1]

0x4b95a8 CMP	X0, #0

0x4b95ac B.LE	4b95c8

0x4b95b0 MOVZ	X11, #1

0x4b95b4 CMP	X0, X11

0x4b95b8 B.NE	4b95c0

0x4b95bc LDR	X11, [X2, X4,LSL #3]

0x4b95c0 ADD	X4, X4, #1

0x4b95c4 STR	X11, [X1]

0x4b95c8 ADD	X1, X1, #8

0x4b95cc LDR	X12, [X1]

0x4b95d0 CMP	X12, #0

0x4b95d4 B.LE	4b95f0

0x4b95d8 MOVZ	X13, #1

0x4b95dc CMP	X12, X13

0x4b95e0 B.NE	4b95e8

0x4b95e4 LDR	X13, [X2, X4,LSL #3]

0x4b95e8 ADD	X4, X4, #1

0x4b95ec STR	X13, [X1]

0x4b95f0 ADD	X1, X1, #8

0x4b95f4 LDR	X14, [X1]

0x4b95f8 CMP	X14, #0

0x4b95fc B.LE	4b9614

0x4b9600 MOVZ	X15, #1

0x4b9604 CMP	X14, X15

0x4b9608 B.EQ	4b9830

0x4b960c ADD	X4, X4, #1

0x4b9610 STR	X15, [X1]

0x4b9614 ADD	X1, X1, #8

0x4b9618 LDR	X16, [X1]

0x4b961c CMP	X16, #0

0x4b9620 B.LE	4b963c

0x4b9624 MOVZ	X17, #1

0x4b9628 CMP	X16, X17

0x4b962c B.NE	4b9634

0x4b9630 LDR	X17, [X2, X4,LSL #3]

0x4b9634 ADD	X4, X4, #1

0x4b9638 STR	X17, [X1]

0x4b963c ADD	X1, X1, #8

0x4b9640 LDR	X18, [X1]

0x4b9644 CMP	X18, #0

0x4b9648 B.LE	4b9664

0x4b964c MOVZ	X3, #1

0x4b9650 CMP	X18, X3

0x4b9654 B.NE	4b965c

0x4b9658 LDR	X3, [X2, X4,LSL #3]

0x4b965c ADD	X4, X4, #1

0x4b9660 STR	X3, [X1]

0x4b9664 ADD	X1, X1, #8

0x4b9668 LDR	X6, [X1]

0x4b966c CMP	X6, #0

0x4b9670 B.LE	4b968c

0x4b9674 MOVZ	X7, #1

0x4b9678 CMP	X6, X7

0x4b967c B.NE	4b9684

0x4b9680 LDR	X7, [X2, X4,LSL #3]

0x4b9684 ADD	X4, X4, #1

0x4b9688 STR	X7, [X1]

0x4b968c ADD	X1, X1, #8

0x4b9690 CMP	X1, X5

0x4b9694 B.EQ	4b97a8

(2114) 0x4b9698 LDR	X8, [X1]

(2114) 0x4b969c CMP	X8, #0

(2114) 0x4b96a0 B.LE	4b96b8

(2114) 0x4b96a4 MOVZ	X9, #1

(2114) 0x4b96a8 CMP	X8, X9

(2114) 0x4b96ac B.EQ	4b9810

(2114) 0x4b96b0 ADD	X4, X4, #1

(2114) 0x4b96b4 STR	X9, [X1]

(2114) 0x4b96b8 LDR	X10, [X1, #8]

(2114) 0x4b96bc ADD	X1, X1, #8

(2114) 0x4b96c0 CMP	X10, #0

(2114) 0x4b96c4 B.LE	4b96dc

(2114) 0x4b96c8 MOVZ	X0, #1

(2114) 0x4b96cc CMP	X10, X0

(2114) 0x4b96d0 B.EQ	4b97f0

(2114) 0x4b96d4 ADD	X4, X4, #1

(2114) 0x4b96d8 STR	X0, [X1]

(2114) 0x4b96dc LDR	X11, [X1, #8]

(2114) 0x4b96e0 CMP	X11, #0

(2114) 0x4b96e4 B.LE	4b96fc

(2114) 0x4b96e8 MOVZ	X12, #1

(2114) 0x4b96ec CMP	X11, X12

(2114) 0x4b96f0 B.EQ	4b97b0

(2114) 0x4b96f4 ADD	X4, X4, #1

(2114) 0x4b96f8 STR	X12, [X1, #8]

(2114) 0x4b96fc LDR	X13, [X1, #16]

(2114) 0x4b9700 CMP	X13, #0

(2114) 0x4b9704 B.LE	4b971c

(2114) 0x4b9708 MOVZ	X14, #1

(2114) 0x4b970c CMP	X13, X14

(2114) 0x4b9710 B.EQ	4b97c0

(2114) 0x4b9714 ADD	X4, X4, #1

(2114) 0x4b9718 STR	X14, [X1, #16]

(2114) 0x4b971c LDR	X15, [X1, #24]

(2114) 0x4b9720 CMP	X15, #0

(2114) 0x4b9724 B.LE	4b973c

(2114) 0x4b9728 MOVZ	X16, #1

(2114) 0x4b972c CMP	X15, X16

(2114) 0x4b9730 B.EQ	4b97d0

(2114) 0x4b9734 ADD	X4, X4, #1

(2114) 0x4b9738 STR	X16, [X1, #24]

(2114) 0x4b973c LDR	X17, [X1, #32]

(2114) 0x4b9740 CMP	X17, #0

(2114) 0x4b9744 B.LE	4b975c

(2114) 0x4b9748 MOVZ	X18, #1

(2114) 0x4b974c CMP	X17, X18

(2114) 0x4b9750 B.EQ	4b9820

(2114) 0x4b9754 ADD	X4, X4, #1

(2114) 0x4b9758 STR	X18, [X1, #32]

(2114) 0x4b975c LDR	X6, [X1, #40]

(2114) 0x4b9760 CMP	X6, #0

(2114) 0x4b9764 B.LE	4b977c

(2114) 0x4b9768 MOVZ	X3, #1

(2114) 0x4b976c CMP	X6, X3

(2114) 0x4b9770 B.EQ	4b97e0

(2114) 0x4b9774 ADD	X4, X4, #1

(2114) 0x4b9778 STR	X3, [X1, #40]

(2114) 0x4b977c LDR	X7, [X1, #48]

(2114) 0x4b9780 CMP	X7, #0

(2114) 0x4b9784 B.LE	4b979c

(2114) 0x4b9788 MOVZ	X8, #1

(2114) 0x4b978c CMP	X7, X8

(2114) 0x4b9790 B.EQ	4b9800

(2114) 0x4b9794 ADD	X4, X4, #1

(2114) 0x4b9798 STR	X8, [X1, #48]

(2114) 0x4b979c ADD	X1, X1, #56

(2114) 0x4b97a0 CMP	X1, X5

(2114) 0x4b97a4 B.NE	4b9698

0x4b97a8 MOVZ	X0, #0

0x4b97ac RET

(2114) 0x4b97b0 LDR	X12, [X2, X4,LSL #3]

(2114) 0x4b97b4 ADD	X4, X4, #1

(2114) 0x4b97b8 STR	X12, [X1, #8]

(2114) 0x4b97bc B	4b96fc

(2114) 0x4b97c0 LDR	X14, [X2, X4,LSL #3]

(2114) 0x4b97c4 ADD	X4, X4, #1

(2114) 0x4b97c8 STR	X14, [X1, #16]

(2114) 0x4b97cc B	4b971c

(2114) 0x4b97d0 LDR	X16, [X2, X4,LSL #3]

(2114) 0x4b97d4 ADD	X4, X4, #1

(2114) 0x4b97d8 STR	X16, [X1, #24]

(2114) 0x4b97dc B	4b973c

(2114) 0x4b97e0 LDR	X3, [X2, X4,LSL #3]

(2114) 0x4b97e4 ADD	X4, X4, #1

(2114) 0x4b97e8 STR	X3, [X1, #40]

(2114) 0x4b97ec B	4b977c

(2114) 0x4b97f0 LDR	X0, [X2, X4,LSL #3]

(2114) 0x4b97f4 ADD	X4, X4, #1

(2114) 0x4b97f8 STR	X0, [X1]

(2114) 0x4b97fc B	4b96dc

(2114) 0x4b9800 LDR	X8, [X2, X4,LSL #3]

(2114) 0x4b9804 ADD	X4, X4, #1

(2114) 0x4b9808 STR	X8, [X1, #48]

(2114) 0x4b980c B	4b979c

(2114) 0x4b9810 LDR	X9, [X2, X4,LSL #3]

(2114) 0x4b9814 ADD	X4, X4, #1

(2114) 0x4b9818 STR	X9, [X1]

(2114) 0x4b981c B	4b96b8

(2114) 0x4b9820 LDR	X18, [X2, X4,LSL #3]

(2114) 0x4b9824 ADD	X4, X4, #1

(2114) 0x4b9828 STR	X18, [X1, #32]

(2114) 0x4b982c B	4b975c

0x4b9830 LDR	X15, [X2, X4,LSL #3]

0x4b9834 B	4b960c

0x4b9838 LDR	X10, [X2]

0x4b983c B	4b9598

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_strength.c:2310-2321
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2310-2321.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 13.00 to 3.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	99
nb uops	99
loop length	396
used w registers	0
used x registers	20
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.38 cycles
front end	12.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	13.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	7.17	6.83	7.00	3.50	3.50
cycles	13.00	13.00	13.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	7.17	6.83	7.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.38
Dispatch	13.00
Overall L1	13.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4b9524

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMP X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b97a8 <hypre_BoomerAMGCorrectCFMarker+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X0, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X6, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X7, X6, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X9, X8, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b9698 <hypre_BoomerAMGCorrectCFMarker+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b9668 <hypre_BoomerAMGCorrectCFMarker+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b9640 <hypre_BoomerAMGCorrectCFMarker+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b9618 <hypre_BoomerAMGCorrectCFMarker+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b95f4 <hypre_BoomerAMGCorrectCFMarker+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b95cc <hypre_BoomerAMGCorrectCFMarker+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b95a4 <hypre_BoomerAMGCorrectCFMarker+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b95a0 <hypre_BoomerAMGCorrectCFMarker+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b9838 <hypre_BoomerAMGCorrectCFMarker+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X10, [X0]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b95c8 <hypre_BoomerAMGCorrectCFMarker+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b95c0 <hypre_BoomerAMGCorrectCFMarker+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X11, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b95f0 <hypre_BoomerAMGCorrectCFMarker+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b95e8 <hypre_BoomerAMGCorrectCFMarker+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X13, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b9614 <hypre_BoomerAMGCorrectCFMarker+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b9830 <hypre_BoomerAMGCorrectCFMarker+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X15, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b963c <hypre_BoomerAMGCorrectCFMarker+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b9634 <hypre_BoomerAMGCorrectCFMarker+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X17, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b9664 <hypre_BoomerAMGCorrectCFMarker+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b965c <hypre_BoomerAMGCorrectCFMarker+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X3, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X6, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b968c <hypre_BoomerAMGCorrectCFMarker+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X6, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b9684 <hypre_BoomerAMGCorrectCFMarker+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X7, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 4b97a8 <hypre_BoomerAMGCorrectCFMarker+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 4b960c <hypre_BoomerAMGCorrectCFMarker+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 4b9598 <hypre_BoomerAMGCorrectCFMarker+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	par_strength.c:2310-2321
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2310-2321.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	99
nb uops	99
loop length	396
used w registers	0
used x registers	20
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.38 cycles
front end	12.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	13.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	7.17	6.83	7.00	3.50	3.50
cycles	13.00	13.00	13.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	7.17	6.83	7.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.38
Dispatch	13.00
Overall L1	13.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4b9524

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMP X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b97a8 <hypre_BoomerAMGCorrectCFMarker+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X3, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X0, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X6, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X7, X6, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X9, X8, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b9698 <hypre_BoomerAMGCorrectCFMarker+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b9668 <hypre_BoomerAMGCorrectCFMarker+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b9640 <hypre_BoomerAMGCorrectCFMarker+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b9618 <hypre_BoomerAMGCorrectCFMarker+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b95f4 <hypre_BoomerAMGCorrectCFMarker+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b95cc <hypre_BoomerAMGCorrectCFMarker+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b95a4 <hypre_BoomerAMGCorrectCFMarker+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b95a0 <hypre_BoomerAMGCorrectCFMarker+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b9838 <hypre_BoomerAMGCorrectCFMarker+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X10, [X0]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b95c8 <hypre_BoomerAMGCorrectCFMarker+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b95c0 <hypre_BoomerAMGCorrectCFMarker+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X11, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b95f0 <hypre_BoomerAMGCorrectCFMarker+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b95e8 <hypre_BoomerAMGCorrectCFMarker+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X13, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b9614 <hypre_BoomerAMGCorrectCFMarker+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b9830 <hypre_BoomerAMGCorrectCFMarker+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X15, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b963c <hypre_BoomerAMGCorrectCFMarker+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b9634 <hypre_BoomerAMGCorrectCFMarker+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X17, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b9664 <hypre_BoomerAMGCorrectCFMarker+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b965c <hypre_BoomerAMGCorrectCFMarker+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X3, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X6, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b968c <hypre_BoomerAMGCorrectCFMarker+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X6, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b9684 <hypre_BoomerAMGCorrectCFMarker+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X7, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 4b97a8 <hypre_BoomerAMGCorrectCFMarker+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X2, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 4b960c <hypre_BoomerAMGCorrectCFMarker+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 4b9598 <hypre_BoomerAMGCorrectCFMarker+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	1.93	0	3.6	0	6	0	12.25	0	17.65	0	22.9	0	26.45	0	33.47	0	39.48	0	44.37	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.060000002384186	0.017336063086987
1x2	1	1.93	1.93	2	0.059999994933605	0.016618123278022
1x4	1	3.6	3.6	4	0.059999998658895	0.016255198046565
1x8	1	6	6	8	0.064999997615814	0.01618723012507
1x16	1	12.25	12.25	16	0.060000002384186	0.0093160420656204
1x24	1	17.65	17.65	24	0.059999998658895	0.0068099154159427
1x32	1	22.9	22.9	32	0.060000002384186	0.0056060268543661
1x40	1	26.45	26.45	40	0.064999997615814	0.0051363059319556
1x48	1	33.47	33.47	48	0.059999998658895	0.0040462869219482
1x56	1	39.48	39.48	56	0.059999998658895	0.003485583467409
1x64	1	44.37	44.37	64	0.059999994933605	0.0030441384296864

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCorrectCFMarker–	0.02	0.06
○Loop 2114 - par_strength.c:2311-2316 - exec	0.02	0.06

Report Configuration

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency