OV - exec - Function hypre_ParCSRRelaxThreads._omp

	Function: hypre_ParCSRRelaxThreads._omp_fn.1	Module: exec	Source: ams.c:3662-3682 [...]	Coverage (incl. loops): NA% \| (excl. loops): NA%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

[...]

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

0x4c954c STP	X29, X30, [SP, #976]!

0x4c9550 ADD	X29, SP, #0

0x4c9554 STP	X19, X20, [SP, #16]

0x4c9558 ORR	X19, XZR, X0

0x4c955c STR	X21, [SP, #32]

0x4c9560 LDR	X21, [X0, #64]

0x4c9564 BL	4101b0

0x4c9568 SBFM	X20, X0, #0, #31

0x4c956c BL	4101c0

0x4c9570 SBFM	X1, X0, #0, #31

0x4c9574 SDIV	X7, X21, X20

0x4c9578 MSUB	X0, X7, X20, X21

0x4c957c CMP	X1, X0

0x4c9580 B.LT	4c96b8

0x4c9584 MADD	X1, X7, X1, X0

0x4c9588 ADD	X30, X7, X1

0x4c958c CMP	X1, X30

0x4c9590 B.GE	4c96a8

0x4c9594 LDP	X10, X11, [X19, #16]

0x4c9598 CNTD	X4, ALL

0x4c959c PTRUE	P6.B, ALL

0x4c95a0 LDP	X21, X13, [X19, #32]

0x4c95a4 ADD	X17, X11, #8

0x4c95a8 LDP	X20, X18, [X19, #48]

0x4c95ac ADD	X16, X13, #8

0x4c95b0 LDP	X12, X14, [X19, #72]

0x4c95b4 LDP	X9, X8, [X19, #88]

0x4c95b8 LDR	X15, [X19]

0x4c95bc LDR	D30, [X19, #8]

0x4c95c0 LDR	D31, [X19, #104]

0x4c95c4 B	4c95d4

(2299) 0x4c95c8 ADD	X1, X1, #1

(2299) 0x4c95cc CMP	X30, X1

(2299) 0x4c95d0 B.EQ	4c96a8

(2299) 0x4c95d4 LDR	X5, [X11, X1,LSL #3]

(2299) 0x4c95d8 UBFM	X3, X5, #61, #60

(2299) 0x4c95dc ADD	X6, X10, X5,LSL #3

(2299) 0x4c95e0 LDR	D6, [X10, X3]

(2299) 0x4c95e4 FCMP	D31, D6

(2299) 0x4c95e8 B.EQ	4c95c8

(2299) 0x4c95ec LDR	X2, [X17, X1,LSL #3]

(2299) 0x4c95f0 LDR	D0, [X14, X1,LSL #3]

(2299) 0x4c95f4 CMP	X5, X2

(2299) 0x4c95f8 B.GE	4c9634

(2299) 0x4c95fc MOVZ	X0, #0

(2299) 0x4c9600 ADD	X19, X21, X3

(2299) 0x4c9604 DUP	Z2.D, #0

(2299) 0x4c9608 SUB	X7, X2, X5

(2299) 0x4c960c WHILELO	P7.D, XZR, X7

  (2301) 0x4c9610 LD1D	{Z5.D}, P7/Z, [X19, X0,LSL #3]

  (2301) 0x4c9614 LD1D	{Z4.D}, P7/Z, [X6, X0,LSL #3]

  (2301) 0x4c9618 LD1D	{Z3.D}, P7/Z, [X9, Z5.D,LSL #3]

  (2301) 0x4c961c ADD	X0, X0, X4

  (2301) 0x4c9620 FMLS	Z2.D, P7/M, Z3.D, Z4.D

  (2301) 0x4c9624 WHILELO	P7.D, X0, X7

  (2301) 0x4c9628 B.NE	4c9610

(2299) 0x4c962c FADDV	D1, P6, Z2.D

(2299) 0x4c9630 FADD	D0, D0, D1

(2299) 0x4c9634 LDR	X3, [X13, X1,LSL #3]

(2299) 0x4c9638 LDR	X6, [X16, X1,LSL #3]

(2299) 0x4c963c CMP	X3, X6

(2299) 0x4c9640 B.GE	4c9684

(2299) 0x4c9644 ADD	X5, X18, X3,LSL #3

(2299) 0x4c9648 MOVZ	X7, #0

(2299) 0x4c964c SUB	X2, X6, X3

(2299) 0x4c9650 ADD	X19, X20, X3,LSL #3

(2299) 0x4c9654 WHILELO	P0.D, XZR, X2

(2299) 0x4c9658 DUP	Z7.D, #0

(2299) 0x4c965c HINT	#0

  (2300) 0x4c9660 LD1D	{Z25.D}, P0/Z, [X5, X7,LSL #3]

  (2300) 0x4c9664 LD1D	{Z29.D}, P0/Z, [X19, X7,LSL #3]

  (2300) 0x4c9668 LD1D	{Z27.D}, P0/Z, [X8, Z25.D,LSL #3]

  (2300) 0x4c966c ADD	X7, X7, X4

  (2300) 0x4c9670 FMLS	Z7.D, P0/M, Z27.D, Z29.D

  (2300) 0x4c9674 WHILELO	P0.D, X7, X2

  (2300) 0x4c9678 B.NE	4c9660

(2299) 0x4c967c FADDV	D16, P6, Z7.D

(2299) 0x4c9680 FADD	D0, D0, D16

(2299) 0x4c9684 LDR	D26, [X15, X1,LSL #3]

(2299) 0x4c9688 FMUL	D17, D30, D0

(2299) 0x4c968c LDR	D28, [X12, X1,LSL #3]

(2299) 0x4c9690 FDIV	D18, D17, D26

(2299) 0x4c9694 FADD	D19, D28, D18

(2299) 0x4c9698 STR	D19, [X12, X1,LSL #3]

(2299) 0x4c969c ADD	X1, X1, #1

(2299) 0x4c96a0 CMP	X30, X1

(2299) 0x4c96a4 B.NE	4c95d4

0x4c96a8 LDR	X21, [SP, #32]

0x4c96ac LDP	X19, X20, [SP, #16]

0x4c96b0 LDP	X29, X30, [SP], #48

0x4c96b4 RET

0x4c96b8 ADD	X7, X7, #1

0x4c96bc MOVZ	X0, #0

0x4c96c0 B	4c9584

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 42% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 5.17 cycles (3.87x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	38
nb uops	38
loop length	152
used w registers	0
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	4.75	4.75	5.00	4.50	0.00	0.00	0.00	0.00	5.17	4.83	5.00	1.50	1.50
cycles	3.50	3.50	4.75	4.75	5.00	4.50	0.00	0.00	0.00	0.00	5.17	4.83	5.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	4.75
Dispatch	5.17
DIV/SQRT	5.00-20.00
Overall L1	5.17-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	42%
load	38%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	62%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4c954c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X20, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X7, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X0, X7, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4c96b8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X7, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X30, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4c96a8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X11, [X19, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CNTD X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
LDP X21, X13, [X19, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X17, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X18, [X19, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X16, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X14, [X19, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X8, [X19, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X15, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D30, [X19, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D31, [X19, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 4c95d4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4c9584 <hypre_ParCSRRelaxThreads._omp_fn.1+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 42% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 5.17 cycles (3.87x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	38
nb uops	38
loop length	152
used w registers	0
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	4.75	4.75	5.00	4.50	0.00	0.00	0.00	0.00	5.17	4.83	5.00	1.50	1.50
cycles	3.50	3.50	4.75	4.75	5.00	4.50	0.00	0.00	0.00	0.00	5.17	4.83	5.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	4.75
Dispatch	5.17
DIV/SQRT	5.00-20.00
Overall L1	5.17-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	42%
load	38%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	62%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4c954c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X20, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X7, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X0, X7, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4c96b8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X7, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X30, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4c96a8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X11, [X19, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CNTD X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
LDP X21, X13, [X19, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X17, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X18, [X19, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X16, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X14, [X19, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X8, [X19, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X15, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D30, [X19, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D31, [X19, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 4c95d4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4c9584 <hypre_ParCSRRelaxThreads._omp_fn.1+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
		1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1
1x2	2	1	1	2	55.240001678467	30.423631668091
1x4	4	1	1	4	27.955003738403	30.194030761719
1x8	8	1	1	8	14.904998779297	29.478191375732
1x16	16	1	1	16	15.065001487732	36.826313018799
1x24	24	1	1	24	14.68000125885	39.509994506836
1x32	32	1	1	32	13.110000610352	38.737182617188
1x40	40	1	1	40	12.095000267029	37.877098083496
1x48	48	1	1	48	11.635000228882	37.229209899902
1x56	56	1	1	56	11.375002861023	36.649753570557
1x64	64	1	1	64	11.244999885559	36.188972473145

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads._omp_fn.1–	0.00	0.00
▼Loop 2299 - ams.c:3662-3682 - exec–	0.00	0.00
○Loop 2300 - ams.c:3677-3680 - exec	0.00	0.00
○Loop 2301 - ams.c:3672-3675 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency