OV - exec - Function hypre

	Function: hypre_ParCSRRelax	Module: exec	Source: ams.c:63-331 [...]	Coverage (incl. loops): 1.72% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 63 - 331

--------------------------------------------------------------------------------

63: {

64:    HYPRE_Int sweep;

65:

66:    HYPRE_Real *u_data = hypre_VectorData(hypre_ParVectorLocalVector(u));

67:    HYPRE_Real *f_data = hypre_VectorData(hypre_ParVectorLocalVector(f));

68:    HYPRE_Real *v_data = hypre_VectorData(hypre_ParVectorLocalVector(v));

69:

70:    for (sweep = 0; sweep < relax_times; sweep++)

71:    {

72:       if (relax_type == 1) /* l1-scaled Jacobi */

73:       {

74: 	 HYPRE_Int i, num_rows = hypre_ParCSRMatrixNumRows(A);

75:          hypre_ParVectorCopy(f,v);

76:          hypre_ParCSRMatrixMatvec(-relax_weight, A, u, relax_weight, v);

77:          /* u += w D^{-1}(f - A u), where D_ii = ||A(i,:)||_1 */

78:          for (i = 0; i < num_rows; i++)

79:             u_data[i] += v_data[i] / l1_norms[i];

80:       }

81:       else if (relax_type == 2 || relax_type == 4) /* offd-l1-scaled block GS */

82:       {

83:          hypre_CSRMatrix *A_diag = hypre_ParCSRMatrixDiag(A);

84:          HYPRE_Real *A_diag_data = hypre_CSRMatrixData(A_diag);

85:          HYPRE_Int *A_diag_I = hypre_CSRMatrixI(A_diag);

86:          HYPRE_Int *A_diag_J = hypre_CSRMatrixJ(A_diag);

87:

88:          hypre_CSRMatrix *A_offd = hypre_ParCSRMatrixOffd(A);

89:          HYPRE_Int *A_offd_I = hypre_CSRMatrixI(A_offd);

90:          HYPRE_Int *A_offd_J = hypre_CSRMatrixJ(A_offd);

91:          HYPRE_Real *A_offd_data = hypre_CSRMatrixData(A_offd);

92:

93:          HYPRE_Int i, j;

94:          HYPRE_Int num_rows = hypre_CSRMatrixNumRows(A_diag);

95:          HYPRE_Int num_cols_offd = hypre_CSRMatrixNumCols(A_offd);

96:          HYPRE_Real *u_offd_data = hypre_TAlloc(HYPRE_Real,num_cols_offd);

97:

98:          HYPRE_Real res;

99:

100:          HYPRE_Int num_procs;

101:          hypre_MPI_Comm_size(hypre_ParCSRMatrixComm(A), &num_procs);

102:

103:          /* Copy off-diagonal values of u to the current processor */

104:          if (num_procs > 1)

105:          {

106:             hypre_ParCSRCommPkg *comm_pkg = hypre_ParCSRMatrixCommPkg(A);

107:             HYPRE_Int num_sends;

108:             HYPRE_Real *u_buf_data;

109:             hypre_ParCSRCommHandle *comm_handle;

110:

111:             HYPRE_Int index = 0, start;

112:

113:             if (!comm_pkg)

114:             {

115:                hypre_MatvecCommPkgCreate(A);

116:                comm_pkg = hypre_ParCSRMatrixCommPkg(A);

117:             }

118:

119:             num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg);

120:             u_buf_data = hypre_TAlloc(HYPRE_Real,

121:                                       hypre_ParCSRCommPkgSendMapStart(comm_pkg, num_sends));

122:

123:             for (i = 0; i < num_sends; i++)

124:             {

125:                start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

126:                for (j = start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg,i+1); j++)

127:                   u_buf_data[index++] = u_data[hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j)];

128:             }

129:             comm_handle = hypre_ParCSRCommHandleCreate(1,comm_pkg,u_buf_data,u_offd_data);

130:             hypre_ParCSRCommHandleDestroy(comm_handle);

131:

132:             hypre_TFree(u_buf_data);

133:          }

134:

135:          if (relax_weight == 1.0 && omega == 1.0) /* symmetric Gauss-Seidel */

136:          {

137:             /* Forward local pass */

138:             for (i = 0; i < num_rows; i++)

139:             {

140:                res = f_data[i];

141:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

142:                   res -= A_diag_data[j] * u_data[A_diag_J[j]];

143:                if (num_cols_offd)

144:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

145:                      res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

146:                u_data[i] += res / l1_norms[i];

147:             }

148:             /* Backward local pass */

149:             for (i = num_rows-1; i > -1; i--)

150:             {

151:                res = f_data[i];

152:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

153:                   res -= A_diag_data[j] * u_data[A_diag_J[j]];

154:                if (num_cols_offd)

155:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

156:                      res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

157:                u_data[i] += res / l1_norms[i];

158:             }

159:          }

160:          else if (relax_weight == 1.0) /* SSOR */

161:          {

162:             /* Forward local pass */

163:             for (i = 0; i < num_rows; i++)

164:             {

165:                res = f_data[i];

166:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

167:                   res -= A_diag_data[j] * u_data[A_diag_J[j]];

168:                if (num_cols_offd)

169:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

170:                      res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

171:                u_data[i] += omega * res / l1_norms[i];

172:             }

173:             /* Backward local pass */

174:             for (i = num_rows-1; i > -1; i--)

175:             {

176:                res = f_data[i];

177:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

178:                   res -= A_diag_data[j] * u_data[A_diag_J[j]];

179:                if (num_cols_offd)

180:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

181:                      res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

182:                u_data[i] += omega * res / l1_norms[i];

[...]

188:             HYPRE_Real c1 = omega * relax_weight;

189:             HYPRE_Real c2 = omega * (1.0 - relax_weight);

190:

191:             /* Forward local pass (save initial guess in v_data) */

192:             for (i = 0; i < num_rows; i++)

193:             {

194:                dif = 0.0;

195:                v_data[i] = u_data[i];

196:                res = f_data[i];

197:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

198:                {

199:                   res -= A_diag_data[j] * u_data[A_diag_J[j]];

200:                   if (A_diag_J[j] < i)

201:                      dif += A_diag_data[j] * (v_data[A_diag_J[j]] - u_data[A_diag_J[j]]);

202:                }

203:                if (num_cols_offd)

204:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

205:                      res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

206:                u_data[i] += (c1 * res + c2 * dif) / l1_norms[i];

207:             }

208:             /* Backward local pass */

209:             for (i = num_rows-1; i > -1; i--)

210:             {

211:                dif = 0.0;

212:                res = f_data[i];

213:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

214:                {

215:                   res -= A_diag_data[j] * u_data[A_diag_J[j]];

216:                   if (A_diag_J[j] > i)

217:                      dif += A_diag_data[j] * (v_data[A_diag_J[j]] - u_data[A_diag_J[j]]);

218:                }

219:                if (num_cols_offd)

220:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

221:                      res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

222:                u_data[i] += (c1 * res + c2 * dif) / l1_norms[i];

223:             }

224:          }

225:

226:          hypre_TFree(u_offd_data);

227:       }

228:       else if (relax_type == 3) /* Kaczmarz */

229:       {

230:          hypre_CSRMatrix *A_diag = hypre_ParCSRMatrixDiag(A);

231:          HYPRE_Real *A_diag_data = hypre_CSRMatrixData(A_diag);

232:          HYPRE_Int *A_diag_I = hypre_CSRMatrixI(A_diag);

233:          HYPRE_Int *A_diag_J = hypre_CSRMatrixJ(A_diag);

234:

235:          hypre_CSRMatrix *A_offd = hypre_ParCSRMatrixOffd(A);

236:          HYPRE_Int *A_offd_I = hypre_CSRMatrixI(A_offd);

237:          HYPRE_Int *A_offd_J = hypre_CSRMatrixJ(A_offd);

238:          HYPRE_Real *A_offd_data = hypre_CSRMatrixData(A_offd);

239:

240:          HYPRE_Int i, j;

241:          HYPRE_Int num_rows = hypre_CSRMatrixNumRows(A_diag);

242:          HYPRE_Int num_cols_offd = hypre_CSRMatrixNumCols(A_offd);

243:          HYPRE_Real *u_offd_data = hypre_TAlloc(HYPRE_Real,num_cols_offd);

244:

245:          HYPRE_Real res;

246:

247:          HYPRE_Int num_procs;

248:          hypre_MPI_Comm_size(hypre_ParCSRMatrixComm(A), &num_procs);

249:

250:          /* Copy off-diagonal values of u to the current processor */

251:          if (num_procs > 1)

252:          {

253:             hypre_ParCSRCommPkg *comm_pkg = hypre_ParCSRMatrixCommPkg(A);

254:             HYPRE_Int num_sends;

255:             HYPRE_Real *u_buf_data;

256:             hypre_ParCSRCommHandle *comm_handle;

257:

258:             HYPRE_Int index = 0, start;

259:

260:             if (!comm_pkg)

261:             {

262:                hypre_MatvecCommPkgCreate(A);

263:                comm_pkg = hypre_ParCSRMatrixCommPkg(A);

264:             }

265:

266:             num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg);

267:             u_buf_data = hypre_TAlloc(HYPRE_Real,

268:                                       hypre_ParCSRCommPkgSendMapStart(comm_pkg, num_sends));

269:

270:             for (i = 0; i < num_sends; i++)

271:             {

272:                start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

273:                for (j = start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg,i+1); j++)

274:                   u_buf_data[index++] = u_data[hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j)];

275:             }

276:             comm_handle = hypre_ParCSRCommHandleCreate(1,comm_pkg,u_buf_data,u_offd_data);

277:             hypre_ParCSRCommHandleDestroy(comm_handle);

278:

279:             hypre_TFree(u_buf_data);

280:          }

281:

282:          /* Forward local pass */

283:          for (i = 0; i < num_rows; i++)

284:          {

285:             res = f_data[i];

286:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

287:                res -= A_diag_data[j] * u_data[A_diag_J[j]];

288:             if (num_cols_offd)

289:                for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

290:                   res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

291:             res /= l1_norms[i];

292:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

293:                u_data[A_diag_J[j]] += omega * res * A_diag_data[j];

294:          }

295:

296:          /* Backward local pass */

297:          for (i = num_rows-1; i > -1; i--)

298:          {

299:             res = f_data[i];

300:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

301:                res -= A_diag_data[j] * u_data[A_diag_J[j]];

302:             if (num_cols_offd)

303:                for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

304:                   res -= A_offd_data[j] * u_offd_data[A_offd_J[j]];

305:             res /= l1_norms[i];

306:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

307:                u_data[A_diag_J[j]] += omega * res * A_diag_data[j];

308:          }

309:

310:          hypre_TFree(u_offd_data);

311:       }

312:       else /* call BoomerAMG relaxation */

313:       {

314:          if (relax_type == 16)

315:          {

316:             hypre_ParCSRRelax_Cheby(A,

[...]

326:             hypre_BoomerAMGRelax(A, f, NULL, hypre_abs(relax_type), 0, relax_weight,

327:                                  omega, l1_norms, u, v, z);

328:       }

329:    }

330:    return hypre_error_flag;

331: }

0x4cbf28 SUB	SP, SP, #288

0x4cbf2c STP	X29, X30, [SP, #16]

0x4cbf30 ADD	X29, SP, #16

0x4cbf34 STP	X23, X24, [SP, #64]

0x4cbf38 ORR	X23, XZR, X7

0x4cbf3c ORR	X24, XZR, X1

0x4cbf40 STP	X19, X20, [SP, #32]

0x4cbf44 STP	X21, X22, [SP, #48]

0x4cbf48 STP	X27, X28, [SP, #96]

0x4cbf4c ORR	X28, XZR, X6

0x4cbf50 LDR	X7, [X1, #48]

0x4cbf54 STR	X0, [SP, #184]

0x4cbf58 LDR	X6, [X6, #48]

0x4cbf5c LDR	X1, [X23, #48]

0x4cbf60 LDR	X27, [X7]

0x4cbf64 LDR	X19, [X6]

0x4cbf68 LDR	X22, [X1]

0x4cbf6c LDR	X20, [SP, #288]

0x4cbf70 CMP	X3, #0

0x4cbf74 B.LE	4cc07c

0x4cbf78 ORR	X21, XZR, X2

0x4cbf7c SUB	X0, X2, #2

0x4cbf80 STP	X25, X26, [SP, #80]

0x4cbf84 AND	X2, X0, #0x1fffffffc

0x4cbf88 ORR	X26, XZR, X4

0x4cbf8c STP	D11, D12, [SP, #128]

0x4cbf90 FMOV	D12, D0

0x4cbf94 CMP	X21, #1

0x4cbf98 B.EQ	4cd914

0x4cbf9c STP	D13, D14, [SP, #144]

0x4cbfa0 FMOV	D11, D1

0x4cbfa4 MOVZ	X25, #0

0x4cbfa8 CBZ	X2, 4cc394

0x4cbfac LDR	X22, [SP, #184]

0x4cbfb0 FMOV	D14, D3

0x4cbfb4 FMOV	D13, D4

0x4cbfb8 STR	D15, [SP, #160]

0x4cbfbc FMOV	D15, D2

0x4cbfc0 STP	X19, X27, [SP, #192]

0x4cbfc4 ORR	X19, XZR, X25

0x4cbfc8 ORR	X27, XZR, X3

0x4cbfcc ORR	X25, XZR, X21

0x4cbfd0 ORR	X21, XZR, X5

0x4cbfd4 HINT	#0

0x4cbfd8 HINT	#0

0x4cbfdc HINT	#0

(2377) 0x4cbfe0 CMP	X25, #3

(2377) 0x4cbfe4 B.EQ	4cd05c

(2377) 0x4cbfe8 SUB	X3, X27, X19

(2377) 0x4cbfec ANDS	X4, X3, #0x7

(2377) 0x4cbff0 B.EQ	4cc1e8

(2377) 0x4cbff4 CMP	X4, #1

(2377) 0x4cbff8 B.EQ	4cd908

(2377) 0x4cbffc CMP	X4, #2

(2377) 0x4cc000 B.EQ	4cd8fc

(2377) 0x4cc004 CMP	X4, #3

(2377) 0x4cc008 B.EQ	4cd8d0

(2377) 0x4cc00c CMP	X4, #4

(2377) 0x4cc010 B.EQ	4cd030

(2377) 0x4cc014 CMP	X4, #5

(2377) 0x4cc018 B.EQ	4cc388

(2377) 0x4cc01c CMP	X4, #6

(2377) 0x4cc020 B.EQ	4cc0a0

(2377) 0x4cc024 CMP	X25, #16

(2377) 0x4cc028 B.EQ	4ccff8

(2377) 0x4cc02c CMP	X25, #0

(2377) 0x4cc030 FMOV	D1, D11

(2377) 0x4cc034 FMOV	D0, D12

(2377) 0x4cc038 ORR	X7, XZR, X23

(2377) 0x4cc03c ORR	X6, XZR, X28

(2377) 0x4cc040 STR	X20, [SP]

(2377) 0x4cc044 ORR	X5, XZR, X26

(2377) 0x4cc048 MOVZ	X4, #0

(2377) 0x4cc04c CSNEG	X3, X25, X25, #10

(2377) 0x4cc050 MOVZ	X2, #0

(2377) 0x4cc054 ORR	X1, XZR, X24

(2377) 0x4cc058 ORR	X0, XZR, X22

(2377) 0x4cc05c ADD	X19, X19, #1

(2377) 0x4cc060 BL	4a1d40

(2377) 0x4cc064 CMP	X27, X19

(2377) 0x4cc068 B.NE	4cbfe0

0x4cc06c LDR	D15, [SP, #160]

0x4cc070 LDP	X25, X26, [SP, #80]

0x4cc074 LDP	D11, D12, [SP, #128]

0x4cc078 LDP	D13, D14, [SP, #144]

0x4cc07c ADRP	X22,

0x4cc080 LDP	X29, X30, [SP, #16]

0x4cc084 LDP	X19, X20, [SP, #32]

0x4cc088 LDP	X23, X24, [SP, #64]

0x4cc08c LDP	X27, X28, [SP, #96]

0x4cc090 LDR	X0, [X22, #3856]

0x4cc094 LDP	X21, X22, [SP, #48]

0x4cc098 ADD	SP, SP, #288

0x4cc09c RET

(2377) 0x4cc0a0 CMP	X25, #16

(2377) 0x4cc0a4 B.NE	4cc02c

(2377) 0x4cc0a8 FMOV	D2, D13

(2377) 0x4cc0ac FMOV	D1, D14

(2377) 0x4cc0b0 ORR	X7, XZR, X20

(2377) 0x4cc0b4 FMOV	D0, D15

(2377) 0x4cc0b8 ORR	X6, XZR, X23

(2377) 0x4cc0bc ORR	X5, XZR, X28

(2377) 0x4cc0c0 MOVZ	X4, #0

(2377) 0x4cc0c4 MOVZ	X3, #1

(2377) 0x4cc0c8 ORR	X2, XZR, X21

(2377) 0x4cc0cc ORR	X1, XZR, X24

(2377) 0x4cc0d0 ORR	X0, XZR, X22

(2377) 0x4cc0d4 ADD	X19, X19, #1

(2377) 0x4cc0d8 BL	4aac2c

(2377) 0x4cc0dc FMOV	D2, D13

(2377) 0x4cc0e0 FMOV	D1, D14

(2377) 0x4cc0e4 ORR	X7, XZR, X20

(2377) 0x4cc0e8 FMOV	D0, D15

(2377) 0x4cc0ec ORR	X6, XZR, X23

(2377) 0x4cc0f0 ORR	X5, XZR, X28

(2377) 0x4cc0f4 MOVZ	X4, #0

(2377) 0x4cc0f8 MOVZ	X3, #1

(2377) 0x4cc0fc ORR	X2, XZR, X21

(2377) 0x4cc100 ORR	X1, XZR, X24

(2377) 0x4cc104 ORR	X0, XZR, X22

(2377) 0x4cc108 ADD	X19, X19, #1

(2377) 0x4cc10c BL	4aac2c

(2377) 0x4cc110 FMOV	D2, D13

(2377) 0x4cc114 FMOV	D1, D14

(2377) 0x4cc118 ORR	X7, XZR, X20

(2377) 0x4cc11c FMOV	D0, D15

(2377) 0x4cc120 ORR	X6, XZR, X23

(2377) 0x4cc124 ORR	X5, XZR, X28

(2377) 0x4cc128 MOVZ	X4, #0

(2377) 0x4cc12c MOVZ	X3, #1

(2377) 0x4cc130 ORR	X2, XZR, X21

(2377) 0x4cc134 ORR	X1, XZR, X24

(2377) 0x4cc138 ORR	X0, XZR, X22

(2377) 0x4cc13c ADD	X19, X19, #1

(2377) 0x4cc140 BL	4aac2c

(2377) 0x4cc144 FMOV	D2, D13

(2377) 0x4cc148 FMOV	D1, D14

(2377) 0x4cc14c ORR	X7, XZR, X20

(2377) 0x4cc150 FMOV	D0, D15

(2377) 0x4cc154 ORR	X6, XZR, X23

(2377) 0x4cc158 ORR	X5, XZR, X28

(2377) 0x4cc15c MOVZ	X4, #0

(2377) 0x4cc160 MOVZ	X3, #1

(2377) 0x4cc164 ORR	X2, XZR, X21

(2377) 0x4cc168 ORR	X1, XZR, X24

(2377) 0x4cc16c ORR	X0, XZR, X22

(2377) 0x4cc170 ADD	X19, X19, #1

(2377) 0x4cc174 BL	4aac2c

(2377) 0x4cc178 FMOV	D2, D13

(2377) 0x4cc17c FMOV	D1, D14

(2377) 0x4cc180 ORR	X7, XZR, X20

(2377) 0x4cc184 FMOV	D0, D15

(2377) 0x4cc188 ORR	X6, XZR, X23

(2377) 0x4cc18c ORR	X5, XZR, X28

(2377) 0x4cc190 MOVZ	X4, #0

(2377) 0x4cc194 MOVZ	X3, #1

(2377) 0x4cc198 ORR	X2, XZR, X21

(2377) 0x4cc19c ORR	X1, XZR, X24

(2377) 0x4cc1a0 ORR	X0, XZR, X22

(2377) 0x4cc1a4 ADD	X19, X19, #1

(2377) 0x4cc1a8 BL	4aac2c

(2377) 0x4cc1ac FMOV	D2, D13

(2377) 0x4cc1b0 FMOV	D1, D14

(2377) 0x4cc1b4 ORR	X7, XZR, X20

(2377) 0x4cc1b8 FMOV	D0, D15

(2377) 0x4cc1bc ORR	X6, XZR, X23

(2377) 0x4cc1c0 ORR	X5, XZR, X28

(2377) 0x4cc1c4 MOVZ	X4, #0

(2377) 0x4cc1c8 MOVZ	X3, #1

(2377) 0x4cc1cc ORR	X2, XZR, X21

(2377) 0x4cc1d0 ORR	X1, XZR, X24

(2377) 0x4cc1d4 ORR	X0, XZR, X22

(2377) 0x4cc1d8 ADD	X19, X19, #1

(2377) 0x4cc1dc BL	4aac2c

(2377) 0x4cc1e0 CMP	X19, X27

(2377) 0x4cc1e4 B.EQ	4cc06c

(2377) 0x4cc1e8 CMP	X25, #16

(2377) 0x4cc1ec B.NE	4cc02c

0x4cc1f0 ORR	X25, XZR, X19

0x4cc1f4 ORR	X26, XZR, X22

(2378) 0x4cc1f8 FMOV	D2, D13

(2378) 0x4cc1fc FMOV	D1, D14

(2378) 0x4cc200 ORR	X7, XZR, X20

(2378) 0x4cc204 FMOV	D0, D15

(2378) 0x4cc208 ORR	X6, XZR, X23

(2378) 0x4cc20c ORR	X5, XZR, X28

(2378) 0x4cc210 MOVZ	X4, #0

(2378) 0x4cc214 MOVZ	X3, #1

(2378) 0x4cc218 ORR	X2, XZR, X21

(2378) 0x4cc21c ORR	X1, XZR, X24

(2378) 0x4cc220 ORR	X0, XZR, X26

(2378) 0x4cc224 ADD	X25, X25, #8

(2378) 0x4cc228 BL	4aac2c

(2378) 0x4cc22c FMOV	D2, D13

(2378) 0x4cc230 FMOV	D1, D14

(2378) 0x4cc234 ORR	X7, XZR, X20

(2378) 0x4cc238 FMOV	D0, D15

(2378) 0x4cc23c ORR	X6, XZR, X23

(2378) 0x4cc240 ORR	X5, XZR, X28

(2378) 0x4cc244 ORR	X2, XZR, X21

(2378) 0x4cc248 ORR	X1, XZR, X24

(2378) 0x4cc24c MOVZ	X4, #0

(2378) 0x4cc250 MOVZ	X3, #1

(2378) 0x4cc254 ORR	X0, XZR, X26

(2378) 0x4cc258 BL	4aac2c

(2378) 0x4cc25c FMOV	D2, D13

(2378) 0x4cc260 FMOV	D1, D14

(2378) 0x4cc264 ORR	X7, XZR, X20

(2378) 0x4cc268 FMOV	D0, D15

(2378) 0x4cc26c ORR	X6, XZR, X23

(2378) 0x4cc270 ORR	X5, XZR, X28

(2378) 0x4cc274 ORR	X2, XZR, X21

(2378) 0x4cc278 ORR	X1, XZR, X24

(2378) 0x4cc27c MOVZ	X4, #0

(2378) 0x4cc280 MOVZ	X3, #1

(2378) 0x4cc284 ORR	X0, XZR, X26

(2378) 0x4cc288 BL	4aac2c

(2378) 0x4cc28c FMOV	D2, D13

(2378) 0x4cc290 FMOV	D1, D14

(2378) 0x4cc294 ORR	X7, XZR, X20

(2378) 0x4cc298 FMOV	D0, D15

(2378) 0x4cc29c ORR	X6, XZR, X23

(2378) 0x4cc2a0 ORR	X5, XZR, X28

(2378) 0x4cc2a4 ORR	X2, XZR, X21

(2378) 0x4cc2a8 ORR	X1, XZR, X24

(2378) 0x4cc2ac MOVZ	X4, #0

(2378) 0x4cc2b0 MOVZ	X3, #1

(2378) 0x4cc2b4 ORR	X0, XZR, X26

(2378) 0x4cc2b8 BL	4aac2c

(2378) 0x4cc2bc FMOV	D2, D13

(2378) 0x4cc2c0 FMOV	D1, D14

(2378) 0x4cc2c4 ORR	X7, XZR, X20

(2378) 0x4cc2c8 FMOV	D0, D15

(2378) 0x4cc2cc ORR	X6, XZR, X23

(2378) 0x4cc2d0 ORR	X5, XZR, X28

(2378) 0x4cc2d4 ORR	X2, XZR, X21

(2378) 0x4cc2d8 ORR	X1, XZR, X24

(2378) 0x4cc2dc MOVZ	X4, #0

(2378) 0x4cc2e0 MOVZ	X3, #1

(2378) 0x4cc2e4 ORR	X0, XZR, X26

(2378) 0x4cc2e8 BL	4aac2c

(2378) 0x4cc2ec FMOV	D2, D13

(2378) 0x4cc2f0 FMOV	D1, D14

(2378) 0x4cc2f4 ORR	X7, XZR, X20

(2378) 0x4cc2f8 FMOV	D0, D15

(2378) 0x4cc2fc ORR	X6, XZR, X23

(2378) 0x4cc300 ORR	X5, XZR, X28

(2378) 0x4cc304 ORR	X2, XZR, X21

(2378) 0x4cc308 ORR	X1, XZR, X24

(2378) 0x4cc30c MOVZ	X4, #0

(2378) 0x4cc310 MOVZ	X3, #1

(2378) 0x4cc314 ORR	X0, XZR, X26

(2378) 0x4cc318 BL	4aac2c

(2378) 0x4cc31c FMOV	D2, D13

(2378) 0x4cc320 FMOV	D1, D14

(2378) 0x4cc324 ORR	X7, XZR, X20

(2378) 0x4cc328 FMOV	D0, D15

(2378) 0x4cc32c ORR	X6, XZR, X23

(2378) 0x4cc330 ORR	X5, XZR, X28

(2378) 0x4cc334 ORR	X2, XZR, X21

(2378) 0x4cc338 ORR	X1, XZR, X24

(2378) 0x4cc33c MOVZ	X4, #0

(2378) 0x4cc340 MOVZ	X3, #1

(2378) 0x4cc344 ORR	X0, XZR, X26

(2378) 0x4cc348 BL	4aac2c

(2378) 0x4cc34c FMOV	D2, D13

(2378) 0x4cc350 FMOV	D1, D14

(2378) 0x4cc354 ORR	X7, XZR, X20

(2378) 0x4cc358 FMOV	D0, D15

(2378) 0x4cc35c ORR	X6, XZR, X23

(2378) 0x4cc360 ORR	X5, XZR, X28

(2378) 0x4cc364 ORR	X2, XZR, X21

(2378) 0x4cc368 ORR	X1, XZR, X24

(2378) 0x4cc36c ORR	X0, XZR, X26

(2378) 0x4cc370 MOVZ	X4, #0

(2378) 0x4cc374 MOVZ	X3, #1

(2378) 0x4cc378 BL	4aac2c

(2378) 0x4cc37c CMP	X25, X27

(2378) 0x4cc380 B.NE	4cc1f8

0x4cc384 B	4cc06c

(2377) 0x4cc388 CMP	X25, #16

(2377) 0x4cc38c B.NE	4cc02c

(2377) 0x4cc390 B	4cc0dc

0x4cc394 FMOV	D20, #1.0000000

0x4cc398 STP	D9, D10, [SP, #112]

0x4cc39c FMUL	D9, D0, D1

0x4cc3a0 LDR	X25, [SP, #184]

0x4cc3a4 CNTD	X20, ALL

0x4cc3a8 STP	X27, X4, [SP, #192]

0x4cc3ac FSUB	D22, D20, S0

0x4cc3b0 FCMP	D0, D20

0x4cc3b4 STR	XZR, [SP, #208]

0x4cc3b8 STR	X3, [SP, #240]

0x4cc3bc FMUL	D14, D22, D1

0x4cc3c0 FCCMP	D1, D20, #0, #0

0x4cc3c4 CSINC	W24, WZR, WZR, #1

0x4cc3c8 STR	W24, [SP, #232]

(2342) 0x4cc3cc LDP	X26, X11, [X25, #56]

(2342) 0x4cc3d0 LDR	X21, [X26, #16]

(2342) 0x4cc3d4 LDP	X27, X24, [X26]

(2342) 0x4cc3d8 LDP	X9, X10, [X11]

(2342) 0x4cc3dc LDR	X23, [X26, #48]

(2342) 0x4cc3e0 LDR	X26, [X11, #24]

(2342) 0x4cc3e4 LDR	X12, [X11, #48]

(2342) 0x4cc3e8 STP	X10, X9, [SP, #216]

(2342) 0x4cc3ec UBFM	X0, X26, #61, #60

(2342) 0x4cc3f0 STR	X12, [SP, #184]

(2342) 0x4cc3f4 BL	5293e8

(2342) 0x4cc3f8 ORR	X28, XZR, X0

(2342) 0x4cc3fc LDR	X0, [X25]

(2342) 0x4cc400 ADD	X1, SP, #280

(2342) 0x4cc404 BL	52b320

(2342) 0x4cc408 LDR	X6, [SP, #280]

(2342) 0x4cc40c CNTD	X8, ALL

(2342) 0x4cc410 LDP	X10, X9, [SP, #216]

(2342) 0x4cc414 ADD	X18, X8, #2

(2342) 0x4cc418 CMP	X6, #1

(2342) 0x4cc41c LDR	X11, [SP, #184]

(2342) 0x4cc420 B.GT	4ccbe8

(2342) 0x4cc424 LDR	W7, [SP, #232]

(2342) 0x4cc428 CBNZ	W7, 4cce00

(2342) 0x4cc42c FMOV	D7, #1.0000000

(2342) 0x4cc430 FCMP	D12, D7

(2342) 0x4cc434 B.NE	4cc648

(2342) 0x4cc438 CMP	X21, #0

(2342) 0x4cc43c B.LE	4cc56c

(2342) 0x4cc440 LDP	X12, X30, [SP, #192]

(2342) 0x4cc444 MOVZ	X5, #0

(2342) 0x4cc448 ADD	X18, X27, #8

(2342) 0x4cc44c ADD	X17, X9, #8

(2342) 0x4cc450 PTRUE	P2.B, ALL

(2342) 0x4cc454 HINT	#0

(2342) 0x4cc458 HINT	#0

(2342) 0x4cc45c HINT	#0

  (2352) 0x4cc460 LDR	X8, [X27, X5,LSL #3]

  (2352) 0x4cc464 LDR	X13, [X18, X5,LSL #3]

  (2352) 0x4cc468 LDR	D5, [X12, X5,LSL #3]

  (2352) 0x4cc46c CMP	X8, X13

  (2352) 0x4cc470 B.GE	4cc4b0

  (2352) 0x4cc474 ADD	X14, X23, X8,LSL #3

  (2352) 0x4cc478 MOVZ	X16, #0

  (2352) 0x4cc47c SUB	X6, X13, X8

  (2352) 0x4cc480 ADD	X3, X24, X8,LSL #3

  (2352) 0x4cc484 WHILELO	P3.D, XZR, X6

  (2352) 0x4cc488 DUP	Z26.D, #0

    (2357) 0x4cc48c LD1D	{Z28.D}, P3/Z, [X3, X16,LSL #3]

    (2357) 0x4cc490 LD1D	{Z27.D}, P3/Z, [X14, X16,LSL #3]

    (2357) 0x4cc494 LD1D	{Z30.D}, P3/Z, [X19, Z28.D,LSL #3]

    (2357) 0x4cc498 ADD	X16, X16, X20

    (2357) 0x4cc49c FMLS	Z26.D, P3/M, Z30.D, Z27.D

    (2357) 0x4cc4a0 WHILELO	P3.D, X16, X6

    (2357) 0x4cc4a4 B.NE	4cc48c

  (2352) 0x4cc4a8 FADDV	D0, P2, Z26.D

  (2352) 0x4cc4ac FADD	D5, D5, D0

  (2352) 0x4cc4b0 CBNZ	X26, 4cc5a0

  (2352) 0x4cc4b4 LDR	D13, [X30, X5,LSL #3]

  (2352) 0x4cc4b8 FMUL	D10, D5, D11

  (2352) 0x4cc4bc LDR	D7, [X19, X5,LSL #3]

  (2352) 0x4cc4c0 FDIV	D17, D10, D13

  (2352) 0x4cc4c4 FADD	D4, D7, D17

  (2352) 0x4cc4c8 STR	D4, [X19, X5,LSL #3]

  (2352) 0x4cc4cc ADD	X5, X5, #1

  (2352) 0x4cc4d0 CMP	X21, X5

  (2352) 0x4cc4d4 B.NE	4cc460

(2342) 0x4cc4d8 LDP	X12, X30, [SP, #192]

(2342) 0x4cc4dc SUB	X21, X21, #1

(2342) 0x4cc4e0 ADD	X17, X9, #8

(2342) 0x4cc4e4 PTRUE	P5.B, ALL

  (2353) 0x4cc4e8 LDR	X8, [X27, X21,LSL #3]

  (2353) 0x4cc4ec LDR	X13, [X18, X21,LSL #3]

  (2353) 0x4cc4f0 LDR	D23, [X12, X21,LSL #3]

  (2353) 0x4cc4f4 CMP	X8, X13

  (2353) 0x4cc4f8 B.GE	4cc544

  (2353) 0x4cc4fc ADD	X14, X23, X8,LSL #3

  (2353) 0x4cc500 MOVZ	X16, #0

  (2353) 0x4cc504 SUB	X6, X13, X8

  (2353) 0x4cc508 ADD	X3, X24, X8,LSL #3

  (2353) 0x4cc50c WHILELO	P7.D, XZR, X6

  (2353) 0x4cc510 DUP	Z16.D, #0

  (2353) 0x4cc514 HINT	#0

  (2353) 0x4cc518 HINT	#0

  (2353) 0x4cc51c HINT	#0

    (2355) 0x4cc520 LD1D	{Z18.D}, P7/Z, [X3, X16,LSL #3]

    (2355) 0x4cc524 LD1D	{Z19.D}, P7/Z, [X14, X16,LSL #3]

    (2355) 0x4cc528 LD1D	{Z31.D}, P7/Z, [X19, Z18.D,LSL #3]

    (2355) 0x4cc52c ADD	X16, X16, X20

    (2355) 0x4cc530 FMLS	Z16.D, P7/M, Z31.D, Z19.D

    (2355) 0x4cc534 WHILELO	P7.D, X16, X6

    (2355) 0x4cc538 B.NE	4cc520

  (2353) 0x4cc53c FADDV	D22, P5, Z16.D

  (2353) 0x4cc540 FADD	D23, D23, D22

  (2353) 0x4cc544 CBNZ	X26, 4cc5f0

  (2353) 0x4cc548 LDR	D28, [X30, X21,LSL #3]

  (2353) 0x4cc54c FMUL	D27, D23, D11

  (2353) 0x4cc550 LDR	D0, [X19, X21,LSL #3]

  (2353) 0x4cc554 FDIV	D30, D27, D28

  (2353) 0x4cc558 FADD	D21, D0, D30

  (2353) 0x4cc55c STR	D21, [X19, X21,LSL #3]

  (2353) 0x4cc560 SUB	X21, X21, #1

  (2353) 0x4cc564 CMN	X21, #1

  (2353) 0x4cc568 B.NE	4cc4e8

(2342) 0x4cc56c ORR	X0, XZR, X28

(2342) 0x4cc570 BL	5294c0

(2342) 0x4cc574 LDR	X27, [SP, #208]

(2342) 0x4cc578 LDR	X24, [SP, #240]

(2342) 0x4cc57c ADD	X23, X27, #1

(2342) 0x4cc580 STR	X23, [SP, #208]

(2342) 0x4cc584 CMP	X24, X23

(2342) 0x4cc588 B.NE	4cc3cc

0x4cc58c LDP	D9, D10, [SP, #112]

0x4cc590 LDP	X25, X26, [SP, #80]

0x4cc594 LDP	D11, D12, [SP, #128]

0x4cc598 LDP	D13, D14, [SP, #144]

0x4cc59c B	4cc07c

  (2352) 0x4cc5a0 LDR	X15, [X9, X5,LSL #3]

  (2352) 0x4cc5a4 LDR	X7, [X17, X5,LSL #3]

  (2352) 0x4cc5a8 CMP	X15, X7

  (2352) 0x4cc5ac B.GE	4cc4b4

  (2352) 0x4cc5b0 ADD	X4, X11, X15,LSL #3

  (2352) 0x4cc5b4 MOVZ	X0, #0

  (2352) 0x4cc5b8 SUB	X1, X7, X15

  (2352) 0x4cc5bc ADD	X2, X10, X15,LSL #3

  (2352) 0x4cc5c0 WHILELO	P4.D, XZR, X1

  (2352) 0x4cc5c4 DUP	Z21.D, #0

    (2356) 0x4cc5c8 LD1D	{Z2.D}, P4/Z, [X2, X0,LSL #3]

    (2356) 0x4cc5cc LD1D	{Z1.D}, P4/Z, [X4, X0,LSL #3]

    (2356) 0x4cc5d0 LD1D	{Z3.D}, P4/Z, [X28, Z2.D,LSL #3]

    (2356) 0x4cc5d4 ADD	X0, X0, X20

    (2356) 0x4cc5d8 FMLS	Z21.D, P4/M, Z3.D, Z1.D

    (2356) 0x4cc5dc WHILELO	P4.D, X0, X1

    (2356) 0x4cc5e0 B.NE	4cc5c8

  (2352) 0x4cc5e4 FADDV	D6, P2, Z21.D

  (2352) 0x4cc5e8 FADD	D5, D5, D6

  (2352) 0x4cc5ec B	4cc4b4

  (2353) 0x4cc5f0 LDR	X15, [X9, X21,LSL #3]

  (2353) 0x4cc5f4 LDR	X7, [X17, X21,LSL #3]

  (2353) 0x4cc5f8 CMP	X7, X15

  (2353) 0x4cc5fc B.LE	4cc548

  (2353) 0x4cc600 ADD	X4, X11, X15,LSL #3

  (2353) 0x4cc604 MOVZ	X0, #0

  (2353) 0x4cc608 SUB	X1, X7, X15

  (2353) 0x4cc60c ADD	X2, X10, X15,LSL #3

  (2353) 0x4cc610 WHILELO	P0.D, XZR, X1

  (2353) 0x4cc614 DUP	Z20.D, #0

  (2353) 0x4cc618 HINT	#0

  (2353) 0x4cc61c HINT	#0

    (2354) 0x4cc620 LD1D	{Z29.D}, P0/Z, [X2, X0,LSL #3]

    (2354) 0x4cc624 LD1D	{Z24.D}, P0/Z, [X4, X0,LSL #3]

    (2354) 0x4cc628 LD1D	{Z25.D}, P0/Z, [X28, Z29.D,LSL #3]

    (2354) 0x4cc62c ADD	X0, X0, X20

    (2354) 0x4cc630 FMLS	Z20.D, P0/M, Z25.D, Z24.D

    (2354) 0x4cc634 WHILELO	P0.D, X0, X1

    (2354) 0x4cc638 B.NE	4cc620

  (2353) 0x4cc63c FADDV	D26, P5, Z20.D

  (2353) 0x4cc640 FADD	D23, D23, D26

  (2353) 0x4cc644 B	4cc548

(2342) 0x4cc648 CMP	X21, #0

(2342) 0x4cc64c B.LE	4cc56c

(2342) 0x4cc650 LDP	X30, X8, [SP, #192]

(2342) 0x4cc654 MOVZ	X6, #0

(2342) 0x4cc658 ADD	X17, X27, #8

(2342) 0x4cc65c ADD	X12, X9, #8

(2342) 0x4cc660 PTRUE	P4.B, ALL

  (2343) 0x4cc664 LDR	D31, [X19, X6,LSL #3]

  (2343) 0x4cc668 LDR	X16, [X27, X6,LSL #3]

  (2343) 0x4cc66c LDR	X13, [X17, X6,LSL #3]

  (2343) 0x4cc670 STR	D31, [X22, X6,LSL #3]

  (2343) 0x4cc674 LDR	D21, [X30, X6,LSL #3]

  (2343) 0x4cc678 CMP	X16, X13

  (2343) 0x4cc67c B.GE	4ccf3c

  (2343) 0x4cc680 SUB	X3, X13, #1

  (2343) 0x4cc684 SUB	X14, X13, X16

  (2343) 0x4cc688 SUB	X2, X3, X16

  (2343) 0x4cc68c CMP	X2, X18

  (2343) 0x4cc690 B.CC	4ccfe8

  (2343) 0x4cc694 ADD	X15, X23, X16,LSL #3

  (2343) 0x4cc698 MOVZ	X0, #0

  (2343) 0x4cc69c SUB	X5, X14, X20

  (2343) 0x4cc6a0 ADD	X4, X24, X16,LSL #3

  (2343) 0x4cc6a4 DUP	Z10.D, #0

  (2343) 0x4cc6a8 DUP	Z16.D, X6

  (2343) 0x4cc6ac ORR	Z17.D, Z10.D, Z10.D

    (2351) 0x4cc6b0 LD1D	{Z18.D}, P4/Z, [X4, X0,LSL #3]

    (2351) 0x4cc6b4 LD1D	{Z19.D}, P4/Z, [X15, X0,LSL #3]

    (2351) 0x4cc6b8 CMPGT	P5.D, P4/Z, Z16.D, Z18.D

    (2351) 0x4cc6bc ADD	X0, X0, X20

    (2351) 0x4cc6c0 LD1D	{Z22.D}, P4/Z, [X19, Z18.D,LSL #3]

    (2351) 0x4cc6c4 LD1D	{Z20.D}, P5/Z, [X22, Z18.D,LSL #3]

    (2351) 0x4cc6c8 FMLS	Z17.D, P4/M, Z22.D, Z19.D

    (2351) 0x4cc6cc FSUB	Z23.D, Z20.D, Z22.D

    (2351) 0x4cc6d0 FMLA	Z10.D, P5/M, Z23.D, Z19.D

    (2351) 0x4cc6d4 CMP	X0, X5

    (2351) 0x4cc6d8 B.LS	4cc6b0

  (2343) 0x4cc6dc FADDV	D29, P4, Z17.D

  (2343) 0x4cc6e0 ADD	X16, X16, X0

  (2343) 0x4cc6e4 FADD	D21, D21, D29

  (2343) 0x4cc6e8 FADDV	D6, P4, Z10.D

  (2343) 0x4cc6ec CMP	X0, X14

  (2343) 0x4cc6f0 B.EQ	4cc88c

  (2343) 0x4cc6f4 LDR	X1, [X24, X16,LSL #3]

  (2343) 0x4cc6f8 ORN	X7, XZR, X16

  (2343) 0x4cc6fc ADD	X3, X7, X13

  (2343) 0x4cc700 LDR	D24, [X23, X16,LSL #3]

  (2343) 0x4cc704 AND	X14, X3, #0x3

  (2343) 0x4cc708 UBFM	X2, X1, #61, #60

  (2343) 0x4cc70c LDR	D25, [X19, X2]

  (2343) 0x4cc710 FMSUB	D21, D25, D24, D21

  (2343) 0x4cc714 CMP	X6, X1

  (2343) 0x4cc718 B.LE	4cc728

  (2343) 0x4cc71c LDR	D26, [X22, X2]

  (2343) 0x4cc720 FSUB	D28, D26, S25

  (2343) 0x4cc724 FMADD	D6, D28, D24, D6

  (2343) 0x4cc728 ADD	X0, X16, #1

  (2343) 0x4cc72c CMP	X13, X0

  (2343) 0x4cc730 B.LE	4cc88c

  (2343) 0x4cc734 CBZ	X14, 4cc7d4

  (2343) 0x4cc738 CMP	X14, #1

  (2343) 0x4cc73c B.EQ	4cc7a0

  (2343) 0x4cc740 CMP	X14, #2

  (2343) 0x4cc744 B.EQ	4cc774

  (2343) 0x4cc748 LDR	X16, [X24, X0,LSL #3]

  (2343) 0x4cc74c LDR	D27, [X23, X0,LSL #3]

  (2343) 0x4cc750 UBFM	X15, X16, #61, #60

  (2343) 0x4cc754 LDR	D30, [X19, X15]

  (2343) 0x4cc758 FMSUB	D21, D30, D27, D21

  (2343) 0x4cc75c CMP	X6, X16

  (2343) 0x4cc760 B.LE	4cc770

  (2343) 0x4cc764 LDR	D13, [X22, X15]

  (2343) 0x4cc768 FSUB	D0, D13, S30

  (2343) 0x4cc76c FMADD	D6, D0, D27, D6

  (2343) 0x4cc770 ADD	X0, X0, #1

  (2343) 0x4cc774 LDR	X5, [X24, X0,LSL #3]

  (2343) 0x4cc778 LDR	D1, [X23, X0,LSL #3]

  (2343) 0x4cc77c UBFM	X4, X5, #61, #60

  (2343) 0x4cc780 LDR	D2, [X19, X4]

  (2343) 0x4cc784 FMSUB	D21, D2, D1, D21

  (2343) 0x4cc788 CMP	X6, X5

  (2343) 0x4cc78c B.LE	4cc79c

  (2343) 0x4cc790 LDR	D3, [X22, X4]

  (2343) 0x4cc794 FSUB	D4, D3, S2

  (2343) 0x4cc798 FMADD	D6, D4, D1, D6

  (2343) 0x4cc79c ADD	X0, X0, #1

  (2343) 0x4cc7a0 LDR	X1, [X24, X0,LSL #3]

  (2343) 0x4cc7a4 LDR	D5, [X23, X0,LSL #3]

  (2343) 0x4cc7a8 UBFM	X7, X1, #61, #60

  (2343) 0x4cc7ac LDR	D7, [X19, X7]

  (2343) 0x4cc7b0 FMSUB	D21, D7, D5, D21

  (2343) 0x4cc7b4 CMP	X6, X1

  (2343) 0x4cc7b8 B.LE	4cc7c8

  (2343) 0x4cc7bc LDR	D10, [X22, X7]

  (2343) 0x4cc7c0 FSUB	D16, D10, S7

  (2343) 0x4cc7c4 FMADD	D6, D16, D5, D6

  (2343) 0x4cc7c8 ADD	X0, X0, #1

  (2343) 0x4cc7cc CMP	X13, X0

  (2343) 0x4cc7d0 B.LE	4cc88c

    (2350) 0x4cc7d4 LDR	X3, [X24, X0,LSL #3]

    (2350) 0x4cc7d8 LDR	D17, [X23, X0,LSL #3]

    (2350) 0x4cc7dc UBFM	X14, X3, #61, #60

    (2350) 0x4cc7e0 LDR	D18, [X19, X14]

    (2350) 0x4cc7e4 FMSUB	D21, D18, D17, D21

    (2350) 0x4cc7e8 CMP	X6, X3

    (2350) 0x4cc7ec B.LE	4cc7fc

    (2350) 0x4cc7f0 LDR	D19, [X22, X14]

    (2350) 0x4cc7f4 FSUB	D20, D19, S18

    (2350) 0x4cc7f8 FMADD	D6, D20, D17, D6

    (2350) 0x4cc7fc ADD	X0, X0, #1

    (2350) 0x4cc800 LDR	X16, [X24, X0,LSL #3]

    (2350) 0x4cc804 LDR	D22, [X23, X0,LSL #3]

    (2350) 0x4cc808 UBFM	X2, X16, #61, #60

    (2350) 0x4cc80c LDR	D29, [X19, X2]

    (2350) 0x4cc810 FMSUB	D23, D29, D22, D21

    (2350) 0x4cc814 CMP	X6, X16

    (2350) 0x4cc818 B.LE	4cc828

    (2350) 0x4cc81c LDR	D24, [X22, X2]

    (2350) 0x4cc820 FSUB	D25, D24, S29

    (2350) 0x4cc824 FMADD	D6, D25, D22, D6

    (2350) 0x4cc828 ADD	X15, X0, #1

    (2350) 0x4cc82c ADD	X5, X0, #2

    (2350) 0x4cc830 LDR	X4, [X24, X15,LSL #3]

    (2350) 0x4cc834 ADD	X0, X0, #3

    (2350) 0x4cc838 LDR	D26, [X23, X15,LSL #3]

    (2350) 0x4cc83c UBFM	X1, X4, #61, #60

    (2350) 0x4cc840 LDR	D28, [X19, X1]

    (2350) 0x4cc844 FMSUB	D27, D28, D26, D23

    (2350) 0x4cc848 CMP	X6, X4

    (2350) 0x4cc84c B.LE	4cc85c

    (2350) 0x4cc850 LDR	D30, [X22, X1]

    (2350) 0x4cc854 FSUB	D13, D30, S28

    (2350) 0x4cc858 FMADD	D6, D13, D26, D6

    (2350) 0x4cc85c LDR	X7, [X24, X5,LSL #3]

    (2350) 0x4cc860 LDR	D0, [X23, X5,LSL #3]

    (2350) 0x4cc864 UBFM	X3, X7, #61, #60

    (2350) 0x4cc868 LDR	D1, [X19, X3]

    (2350) 0x4cc86c FMSUB	D21, D1, D0, D27

    (2350) 0x4cc870 CMP	X6, X7

    (2350) 0x4cc874 B.LE	4cc884

    (2350) 0x4cc878 LDR	D2, [X22, X3]

    (2350) 0x4cc87c FSUB	D3, D2, S1

    (2350) 0x4cc880 FMADD	D6, D3, D0, D6

    (2350) 0x4cc884 CMP	X13, X0

    (2350) 0x4cc888 B.GT	4cc7d4

  (2343) 0x4cc88c FMUL	D6, D14, D6

  (2343) 0x4cc890 CBNZ	X26, 4ccb90

  (2343) 0x4cc894 FMADD	D17, D21, D9, D6

  (2343) 0x4cc898 LDR	D18, [X8, X6,LSL #3]

  (2343) 0x4cc89c FDIV	D19, D17, D18

  (2343) 0x4cc8a0 FADD	D31, D19, D31

  (2343) 0x4cc8a4 STR	D31, [X19, X6,LSL #3]

  (2343) 0x4cc8a8 ADD	X6, X6, #1

  (2343) 0x4cc8ac CMP	X21, X6

  (2343) 0x4cc8b0 B.NE	4cc664

(2342) 0x4cc8b4 SUB	X21, X21, #1

(2342) 0x4cc8b8 LDP	X30, X8, [SP, #192]

(2342) 0x4cc8bc ADD	X12, X9, #8

(2342) 0x4cc8c0 PTRUE	P0.B, ALL

(2342) 0x4cc8c4 LDR	X4, [X27, X21,LSL #3]

(2342) 0x4cc8c8 LDR	X7, [X17, X21,LSL #3]

(2342) 0x4cc8cc LDR	D13, [X30, X21,LSL #3]

(2342) 0x4cc8d0 CMP	X4, X7

(2342) 0x4cc8d4 B.GE	4ccb2c

(2342) 0x4cc8d8 HINT	#0

(2342) 0x4cc8dc HINT	#0

  (2344) 0x4cc8e0 SUB	X0, X7, #1

  (2344) 0x4cc8e4 SUB	X1, X7, X4

  (2344) 0x4cc8e8 SUB	X3, X0, X4

  (2344) 0x4cc8ec CMP	X3, X18

  (2344) 0x4cc8f0 B.CC	4ccff0

  (2344) 0x4cc8f4 ADD	X13, X23, X4,LSL #3

  (2344) 0x4cc8f8 MOVZ	X15, #0

  (2344) 0x4cc8fc SUB	X14, X1, X20

  (2344) 0x4cc900 ADD	X16, X24, X4,LSL #3

  (2344) 0x4cc904 DUP	Z22.D, #0

  (2344) 0x4cc908 DUP	Z29.D, X21

  (2344) 0x4cc90c ORR	Z23.D, Z22.D, Z22.D

    (2347) 0x4cc910 LD1D	{Z24.D}, P0/Z, [X16, X15,LSL #3]

    (2347) 0x4cc914 LD1D	{Z25.D}, P0/Z, [X13, X15,LSL #3]

    (2347) 0x4cc918 CMPGT	P6.D, P0/Z, Z24.D, Z29.D

    (2347) 0x4cc91c ADD	X15, X15, X20

    (2347) 0x4cc920 LD1D	{Z28.D}, P0/Z, [X19, Z24.D,LSL #3]

    (2347) 0x4cc924 LD1D	{Z26.D}, P6/Z, [X22, Z24.D,LSL #3]

    (2347) 0x4cc928 FMLS	Z23.D, P0/M, Z28.D, Z25.D

    (2347) 0x4cc92c FSUB	Z27.D, Z26.D, Z28.D

    (2347) 0x4cc930 FMLA	Z22.D, P6/M, Z27.D, Z25.D

    (2347) 0x4cc934 CMP	X15, X14

    (2347) 0x4cc938 B.LS	4cc910

  (2344) 0x4cc93c FADDV	D30, P0, Z23.D

  (2344) 0x4cc940 ADD	X4, X4, X15

  (2344) 0x4cc944 FADD	D13, D13, D30

  (2344) 0x4cc948 FADDV	D4, P0, Z22.D

  (2344) 0x4cc94c CMP	X15, X1

  (2344) 0x4cc950 B.EQ	4ccaec

  (2344) 0x4cc954 LDR	X5, [X24, X4,LSL #3]

  (2344) 0x4cc958 ORN	X2, XZR, X4

  (2344) 0x4cc95c ADD	X6, X2, X7

  (2344) 0x4cc960 LDR	D0, [X23, X4,LSL #3]

  (2344) 0x4cc964 AND	X1, X6, #0x3

  (2344) 0x4cc968 UBFM	X0, X5, #61, #60

  (2344) 0x4cc96c LDR	D1, [X19, X0]

  (2344) 0x4cc970 FMSUB	D13, D1, D0, D13

  (2344) 0x4cc974 CMP	X21, X5

  (2344) 0x4cc978 B.GE	4cc988

  (2344) 0x4cc97c LDR	D21, [X22, X0]

  (2344) 0x4cc980 FSUB	D2, D21, S1

  (2344) 0x4cc984 FMADD	D4, D2, D0, D4

  (2344) 0x4cc988 ADD	X6, X4, #1

  (2344) 0x4cc98c CMP	X7, X6

  (2344) 0x4cc990 B.LE	4ccaec

  (2344) 0x4cc994 CBZ	X1, 4cca34

  (2344) 0x4cc998 CMP	X1, #1

  (2344) 0x4cc99c B.EQ	4cca00

  (2344) 0x4cc9a0 CMP	X1, #2

  (2344) 0x4cc9a4 B.EQ	4cc9d4

  (2344) 0x4cc9a8 LDR	X4, [X24, X6,LSL #3]

  (2344) 0x4cc9ac LDR	D3, [X23, X6,LSL #3]

  (2344) 0x4cc9b0 UBFM	X3, X4, #61, #60

  (2344) 0x4cc9b4 LDR	D6, [X19, X3]

  (2344) 0x4cc9b8 FMSUB	D13, D6, D3, D13

  (2344) 0x4cc9bc CMP	X21, X4

  (2344) 0x4cc9c0 B.GE	4cc9d0

  (2344) 0x4cc9c4 LDR	D5, [X22, X3]

  (2344) 0x4cc9c8 FSUB	D7, D5, S6

  (2344) 0x4cc9cc FMADD	D4, D7, D3, D4

  (2344) 0x4cc9d0 ADD	X6, X6, #1

  (2344) 0x4cc9d4 LDR	X13, [X24, X6,LSL #3]

  (2344) 0x4cc9d8 LDR	D10, [X23, X6,LSL #3]

  (2344) 0x4cc9dc UBFM	X14, X13, #61, #60

  (2344) 0x4cc9e0 LDR	D17, [X19, X14]

  (2344) 0x4cc9e4 FMSUB	D13, D17, D10, D13

  (2344) 0x4cc9e8 CMP	X21, X13

  (2344) 0x4cc9ec B.GE	4cc9fc

  (2344) 0x4cc9f0 LDR	D16, [X22, X14]

  (2344) 0x4cc9f4 FSUB	D18, D16, S17

  (2344) 0x4cc9f8 FMADD	D4, D18, D10, D4

  (2344) 0x4cc9fc ADD	X6, X6, #1

  (2344) 0x4cca00 LDR	X16, [X24, X6,LSL #3]

  (2344) 0x4cca04 LDR	D19, [X23, X6,LSL #3]

  (2344) 0x4cca08 UBFM	X15, X16, #61, #60

  (2344) 0x4cca0c LDR	D31, [X19, X15]

  (2344) 0x4cca10 FMSUB	D13, D31, D19, D13

  (2344) 0x4cca14 CMP	X21, X16

  (2344) 0x4cca18 B.GE	4cca28

  (2344) 0x4cca1c LDR	D20, [X22, X15]

  (2344) 0x4cca20 FSUB	D22, D20, S31

  (2344) 0x4cca24 FMADD	D4, D22, D19, D4

  (2344) 0x4cca28 ADD	X6, X6, #1

  (2344) 0x4cca2c CMP	X7, X6

  (2344) 0x4cca30 B.LE	4ccaec

    (2346) 0x4cca34 LDR	X5, [X24, X6,LSL #3]

    (2346) 0x4cca38 LDR	D29, [X23, X6,LSL #3]

    (2346) 0x4cca3c UBFM	X2, X5, #61, #60

    (2346) 0x4cca40 LDR	D23, [X19, X2]

    (2346) 0x4cca44 FMSUB	D13, D23, D29, D13

    (2346) 0x4cca48 CMP	X21, X5

    (2346) 0x4cca4c B.GE	4cca5c

    (2346) 0x4cca50 LDR	D24, [X22, X2]

    (2346) 0x4cca54 FSUB	D25, D24, S23

    (2346) 0x4cca58 FMADD	D4, D25, D29, D4

    (2346) 0x4cca5c ADD	X6, X6, #1

    (2346) 0x4cca60 LDR	X1, [X24, X6,LSL #3]

    (2346) 0x4cca64 LDR	D26, [X23, X6,LSL #3]

    (2346) 0x4cca68 UBFM	X0, X1, #61, #60

    (2346) 0x4cca6c LDR	D28, [X19, X0]

    (2346) 0x4cca70 FMSUB	D27, D28, D26, D13

    (2346) 0x4cca74 CMP	X21, X1

    (2346) 0x4cca78 B.GE	4cca88

    (2346) 0x4cca7c LDR	D30, [X22, X0]

    (2346) 0x4cca80 FSUB	D0, D30, S28

    (2346) 0x4cca84 FMADD	D4, D0, D26, D4

    (2346) 0x4cca88 ADD	X4, X6, #1

    (2346) 0x4cca8c ADD	X13, X6, #2

    (2346) 0x4cca90 LDR	X14, [X24, X4,LSL #3]

    (2346) 0x4cca94 ADD	X6, X6, #3

    (2346) 0x4cca98 LDR	D21, [X23, X4,LSL #3]

    (2346) 0x4cca9c UBFM	X3, X14, #61, #60

    (2346) 0x4ccaa0 LDR	D2, [X19, X3]

    (2346) 0x4ccaa4 FMSUB	D1, D2, D21, D27

    (2346) 0x4ccaa8 CMP	X21, X14

    (2346) 0x4ccaac B.GE	4ccabc

    (2346) 0x4ccab0 LDR	D3, [X22, X3]

    (2346) 0x4ccab4 FSUB	D6, D3, S2

    (2346) 0x4ccab8 FMADD	D4, D6, D21, D4

    (2346) 0x4ccabc LDR	X16, [X24, X13,LSL #3]

    (2346) 0x4ccac0 LDR	D5, [X23, X13,LSL #3]

    (2346) 0x4ccac4 UBFM	X15, X16, #61, #60

    (2346) 0x4ccac8 LDR	D7, [X19, X15]

    (2346) 0x4ccacc FMSUB	D13, D7, D5, D1

    (2346) 0x4ccad0 CMP	X21, X16

    (2346) 0x4ccad4 B.GE	4ccae4

    (2346) 0x4ccad8 LDR	D10, [X22, X15]

    (2346) 0x4ccadc FSUB	D17, D10, S7

    (2346) 0x4ccae0 FMADD	D4, D17, D5, D4

    (2346) 0x4ccae4 CMP	X7, X6

    (2346) 0x4ccae8 B.GT	4cca34

  (2344) 0x4ccaec FMUL	D20, D14, D4

  (2344) 0x4ccaf0 CBNZ	X26, 4ccb40

  (2344) 0x4ccaf4 FMADD	D20, D13, D9, D20

  (2344) 0x4ccaf8 LDR	D29, [X8, X21,LSL #3]

  (2344) 0x4ccafc LDR	D23, [X19, X21,LSL #3]

  (2344) 0x4ccb00 FDIV	D24, D20, D29

  (2344) 0x4ccb04 FADD	D25, D24, D23

  (2344) 0x4ccb08 STR	D25, [X19, X21,LSL #3]

  (2344) 0x4ccb0c SUB	X21, X21, #1

  (2344) 0x4ccb10 CMN	X21, #1

  (2344) 0x4ccb14 B.EQ	4cc56c

  (2344) 0x4ccb18 LDR	X4, [X27, X21,LSL #3]

  (2344) 0x4ccb1c LDR	X7, [X17, X21,LSL #3]

  (2344) 0x4ccb20 LDR	D13, [X30, X21,LSL #3]

  (2344) 0x4ccb24 CMP	X4, X7

  (2344) 0x4ccb28 B.LT	4cc8e0

  (2348) 0x4ccb2c MOVI	D20, #0

  (2348) 0x4ccb30 CBZ	X26, 4ccaf4

(2342) 0x4ccb34 HINT	#0

(2342) 0x4ccb38 HINT	#0

(2342) 0x4ccb3c HINT	#0

  (2344) 0x4ccb40 LDR	X7, [X9, X21,LSL #3]

  (2344) 0x4ccb44 LDR	X5, [X12, X21,LSL #3]

  (2344) 0x4ccb48 CMP	X7, X5

  (2344) 0x4ccb4c B.GE	4ccaf4

  (2344) 0x4ccb50 ADD	X4, X11, X7,LSL #3

  (2344) 0x4ccb54 MOVZ	X0, #0

  (2344) 0x4ccb58 SUB	X1, X5, X7

  (2344) 0x4ccb5c ADD	X2, X10, X7,LSL #3

  (2344) 0x4ccb60 WHILELO	P1.D, XZR, X1

  (2344) 0x4ccb64 DUP	Z16.D, #0

    (2345) 0x4ccb68 LD1D	{Z18.D}, P1/Z, [X2, X0,LSL #3]

    (2345) 0x4ccb6c LD1D	{Z19.D}, P1/Z, [X4, X0,LSL #3]

    (2345) 0x4ccb70 LD1D	{Z31.D}, P1/Z, [X28, Z18.D,LSL #3]

    (2345) 0x4ccb74 ADD	X0, X0, X20

    (2345) 0x4ccb78 FMLS	Z16.D, P1/M, Z31.D, Z19.D

    (2345) 0x4ccb7c WHILELO	P1.D, X0, X1

    (2345) 0x4ccb80 B.NE	4ccb68

  (2344) 0x4ccb84 FADDV	D22, P0, Z16.D

  (2344) 0x4ccb88 FADD	D13, D13, D22

  (2344) 0x4ccb8c B	4ccaf4

  (2343) 0x4ccb90 LDR	X13, [X9, X6,LSL #3]

  (2343) 0x4ccb94 LDR	X14, [X12, X6,LSL #3]

  (2343) 0x4ccb98 CMP	X13, X14

  (2343) 0x4ccb9c B.GE	4cc894

  (2343) 0x4ccba0 ADD	X16, X11, X13,LSL #3

  (2343) 0x4ccba4 MOVZ	X5, #0

  (2343) 0x4ccba8 SUB	X15, X14, X13

  (2343) 0x4ccbac ADD	X2, X10, X13,LSL #3

  (2343) 0x4ccbb0 WHILELO	P7.D, XZR, X15

  (2343) 0x4ccbb4 DUP	Z4.D, #0

  (2343) 0x4ccbb8 HINT	#0

  (2343) 0x4ccbbc HINT	#0

    (2349) 0x4ccbc0 LD1D	{Z5.D}, P7/Z, [X2, X5,LSL #3]

    (2349) 0x4ccbc4 LD1D	{Z7.D}, P7/Z, [X16, X5,LSL #3]

    (2349) 0x4ccbc8 LD1D	{Z10.D}, P7/Z, [X28, Z5.D,LSL #3]

    (2349) 0x4ccbcc ADD	X5, X5, X20

    (2349) 0x4ccbd0 FMLS	Z4.D, P7/M, Z10.D, Z7.D

    (2349) 0x4ccbd4 WHILELO	P7.D, X5, X15

    (2349) 0x4ccbd8 B.NE	4ccbc0

  (2343) 0x4ccbdc FADDV	D16, P4, Z4.D

  (2343) 0x4ccbe0 FADD	D21, D21, D16

  (2343) 0x4ccbe4 B	4cc894

(2342) 0x4ccbe8 LDR	X5, [X25, #112]

(2342) 0x4ccbec CBZ	X5, 4cd03c

(2342) 0x4ccbf0 LDR	X1, [X5, #8]

(2342) 0x4ccbf4 STR	X11, [SP, #264]

(2342) 0x4ccbf8 LDR	X16, [X5, #24]

(2342) 0x4ccbfc UBFM	X15, X1, #61, #60

(2342) 0x4ccc00 LDR	X14, [X16, X15]

(2342) 0x4ccc04 STR	X15, [SP, #184]

(2342) 0x4ccc08 STP	X1, X5, [SP, #216]

(2342) 0x4ccc0c UBFM	X0, X14, #61, #60

(2342) 0x4ccc10 STP	X9, X10, [SP, #248]

(2342) 0x4ccc14 BL	5293e8

(2342) 0x4ccc18 LDP	X4, X1, [SP, #216]

(2342) 0x4ccc1c ORR	X7, XZR, X0

(2342) 0x4ccc20 LDP	X9, X10, [SP, #248]

(2342) 0x4ccc24 LDR	X18, [SP, #184]

(2342) 0x4ccc28 LDR	X11, [SP, #264]

(2342) 0x4ccc2c CMP	X4, #0

(2342) 0x4ccc30 B.LE	4ccdc0

(2342) 0x4ccc34 MOVZ	X5, #0

(2342) 0x4ccc38 LDR	X4, [X1, #24]

(2342) 0x4ccc3c ADD	X15, X18, X4

  (2364) 0x4ccc40 LDP	X0, X12, [X4]

  (2364) 0x4ccc44 CMP	X0, X12

  (2364) 0x4ccc48 B.GE	4ccdb4

  (2364) 0x4ccc4c UBFM	X30, X5, #61, #60

  (2364) 0x4ccc50 SUB	X3, X12, X0

  (2364) 0x4ccc54 LDR	X8, [X1, #32]

  (2364) 0x4ccc58 SUB	X2, X30, X0,LSL #3

  (2364) 0x4ccc5c ANDS	X17, X3, #0x7

  (2364) 0x4ccc60 ORR	X13, XZR, X0

  (2364) 0x4ccc64 ADD	X6, X7, X2

  (2364) 0x4ccc68 B.EQ	4ccd14

  (2364) 0x4ccc6c CMP	X17, #1

  (2364) 0x4ccc70 B.EQ	4cccfc

  (2364) 0x4ccc74 CMP	X17, #2

  (2364) 0x4ccc78 B.EQ	4cccec

  (2364) 0x4ccc7c CMP	X17, #3

  (2364) 0x4ccc80 B.EQ	4cccdc

  (2364) 0x4ccc84 CMP	X17, #4

  (2364) 0x4ccc88 B.EQ	4ccccc

  (2364) 0x4ccc8c CMP	X17, #5

  (2364) 0x4ccc90 B.EQ	4cccbc

  (2364) 0x4ccc94 CMP	X17, #6

  (2364) 0x4ccc98 B.EQ	4cccac

  (2364) 0x4ccc9c LDR	X16, [X8, X0,LSL #3]

  (2364) 0x4ccca0 LDR	D23, [X19, X16,LSL #3]

  (2364) 0x4ccca4 STR	D23, [X6, X0,LSL #3]

  (2364) 0x4ccca8 ADD	X0, X0, #1

  (2364) 0x4cccac LDR	X14, [X8, X0,LSL #3]

  (2364) 0x4cccb0 LDR	D29, [X19, X14,LSL #3]

  (2364) 0x4cccb4 STR	D29, [X6, X0,LSL #3]

  (2364) 0x4cccb8 ADD	X0, X0, #1

  (2364) 0x4cccbc LDR	X18, [X8, X0,LSL #3]

  (2364) 0x4cccc0 LDR	D24, [X19, X18,LSL #3]

  (2364) 0x4cccc4 STR	D24, [X6, X0,LSL #3]

  (2364) 0x4cccc8 ADD	X0, X0, #1

  (2364) 0x4ccccc LDR	X30, [X8, X0,LSL #3]

  (2364) 0x4cccd0 LDR	D25, [X19, X30,LSL #3]

  (2364) 0x4cccd4 STR	D25, [X6, X0,LSL #3]

  (2364) 0x4cccd8 ADD	X0, X0, #1

  (2364) 0x4cccdc LDR	X3, [X8, X0,LSL #3]

  (2364) 0x4ccce0 LDR	D26, [X19, X3,LSL #3]

  (2364) 0x4ccce4 STR	D26, [X6, X0,LSL #3]

  (2364) 0x4ccce8 ADD	X0, X0, #1

  (2364) 0x4cccec LDR	X2, [X8, X0,LSL #3]

  (2364) 0x4cccf0 LDR	D28, [X19, X2,LSL #3]

  (2364) 0x4cccf4 STR	D28, [X6, X0,LSL #3]

  (2364) 0x4cccf8 ADD	X0, X0, #1

  (2364) 0x4cccfc LDR	X17, [X8, X0,LSL #3]

  (2364) 0x4ccd00 LDR	D27, [X19, X17,LSL #3]

  (2364) 0x4ccd04 STR	D27, [X6, X0,LSL #3]

  (2364) 0x4ccd08 ADD	X0, X0, #1

  (2364) 0x4ccd0c CMP	X0, X12

  (2364) 0x4ccd10 B.EQ	4ccdac

  (2364) 0x4ccd14 ORR	X18, XZR, X4

  (2364) 0x4ccd18 STR	X15, [SP, #184]

    (2365) 0x4ccd1c LDR	X30, [X8, X0,LSL #3]

    (2365) 0x4ccd20 ADD	X4, X0, #1

    (2365) 0x4ccd24 ADD	X16, X0, #2

    (2365) 0x4ccd28 ADD	X15, X0, #3

    (2365) 0x4ccd2c ADD	X14, X0, #4

    (2365) 0x4ccd30 LDR	X3, [X8, X4,LSL #3]

    (2365) 0x4ccd34 LDR	X2, [X8, X16,LSL #3]

    (2365) 0x4ccd38 LDR	D30, [X19, X30,LSL #3]

    (2365) 0x4ccd3c LDR	X17, [X8, X15,LSL #3]

    (2365) 0x4ccd40 LDR	X30, [X8, X14,LSL #3]

    (2365) 0x4ccd44 STR	D30, [X6, X0,LSL #3]

    (2365) 0x4ccd48 LDR	D13, [X19, X3,LSL #3]

    (2365) 0x4ccd4c STR	D13, [X6, X4,LSL #3]

    (2365) 0x4ccd50 ADD	X4, X0, #5

    (2365) 0x4ccd54 LDR	D0, [X19, X2,LSL #3]

    (2365) 0x4ccd58 LDR	X3, [X8, X4,LSL #3]

    (2365) 0x4ccd5c STR	D0, [X6, X16,LSL #3]

    (2365) 0x4ccd60 ADD	X16, X0, #6

    (2365) 0x4ccd64 LDR	D1, [X19, X17,LSL #3]

    (2365) 0x4ccd68 LDR	X2, [X8, X16,LSL #3]

    (2365) 0x4ccd6c STR	D1, [X6, X15,LSL #3]

    (2365) 0x4ccd70 ADD	X15, X0, #7

    (2365) 0x4ccd74 ADD	X0, X0, #8

    (2365) 0x4ccd78 LDR	D2, [X19, X30,LSL #3]

    (2365) 0x4ccd7c STR	D2, [X6, X14,LSL #3]

    (2365) 0x4ccd80 LDR	D3, [X19, X3,LSL #3]

    (2365) 0x4ccd84 LDR	X14, [X8, X15,LSL #3]

    (2365) 0x4ccd88 STR	D3, [X6, X4,LSL #3]

    (2365) 0x4ccd8c LDR	D4, [X19, X2,LSL #3]

    (2365) 0x4ccd90 STR	D4, [X6, X16,LSL #3]

    (2365) 0x4ccd94 LDR	D5, [X19, X14,LSL #3]

    (2365) 0x4ccd98 STR	D5, [X6, X15,LSL #3]

    (2365) 0x4ccd9c CMP	X0, X12

    (2365) 0x4ccda0 B.NE	4ccd1c

  (2364) 0x4ccda4 LDR	X15, [SP, #184]

  (2364) 0x4ccda8 ORR	X4, XZR, X18

  (2364) 0x4ccdac ADD	X5, X0, X5

  (2364) 0x4ccdb0 SUB	X5, X5, X13

  (2364) 0x4ccdb4 ADD	X4, X4, #8

  (2364) 0x4ccdb8 CMP	X4, X15

  (2364) 0x4ccdbc B.NE	4ccc40

(2342) 0x4ccdc0 ORR	X2, XZR, X7

(2342) 0x4ccdc4 ORR	X3, XZR, X28

(2342) 0x4ccdc8 STR	X7, [SP, #184]

(2342) 0x4ccdcc MOVZ	X0, #1

(2342) 0x4ccdd0 STP	X9, X10, [SP, #216]

(2342) 0x4ccdd4 STR	X11, [SP, #248]

(2342) 0x4ccdd8 BL	4e4f44

(2342) 0x4ccddc BL	4e574c

(2342) 0x4ccde0 LDR	X0, [SP, #184]

(2342) 0x4ccde4 BL	5294c0

(2342) 0x4ccde8 CNTD	X1, ALL

(2342) 0x4ccdec LDR	W7, [SP, #232]

(2342) 0x4ccdf0 LDP	X9, X10, [SP, #216]

(2342) 0x4ccdf4 ADD	X18, X1, #2

(2342) 0x4ccdf8 LDR	X11, [SP, #248]

(2342) 0x4ccdfc CBZ	W7, 4cc42c

(2342) 0x4cce00 MOVZ	X4, #0

(2342) 0x4cce04 ADD	X18, X27, #8

(2342) 0x4cce08 PTRUE	P6.B, ALL

(2342) 0x4cce0c ADD	X17, X9, #8

(2342) 0x4cce10 CMP	X21, #0

(2342) 0x4cce14 B.LE	4cc56c

(2342) 0x4cce18 LDP	X12, X30, [SP, #192]

(2342) 0x4cce1c HINT	#0

  (2358) 0x4cce20 LDR	X8, [X27, X4,LSL #3]

  (2358) 0x4cce24 LDR	X13, [X18, X4,LSL #3]

  (2358) 0x4cce28 LDR	D16, [X12, X4,LSL #3]

  (2358) 0x4cce2c CMP	X8, X13

  (2358) 0x4cce30 B.GE	4cce70

  (2358) 0x4cce34 ADD	X5, X23, X8,LSL #3

  (2358) 0x4cce38 MOVZ	X3, #0

  (2358) 0x4cce3c SUB	X14, X13, X8

  (2358) 0x4cce40 ADD	X6, X24, X8,LSL #3

  (2358) 0x4cce44 WHILELO	P1.D, XZR, X14

  (2358) 0x4cce48 DUP	Z2.D, #0

    (2363) 0x4cce4c LD1D	{Z1.D}, P1/Z, [X6, X3,LSL #3]

    (2363) 0x4cce50 LD1D	{Z3.D}, P1/Z, [X5, X3,LSL #3]

    (2363) 0x4cce54 LD1D	{Z6.D}, P1/Z, [X19, Z1.D,LSL #3]

    (2363) 0x4cce58 ADD	X3, X3, X20

    (2363) 0x4cce5c FMLS	Z2.D, P1/M, Z6.D, Z3.D

    (2363) 0x4cce60 WHILELO	P1.D, X3, X14

    (2363) 0x4cce64 B.NE	4cce4c

  (2358) 0x4cce68 FADDV	D5, P6, Z2.D

  (2358) 0x4cce6c FADD	D16, D16, D5

  (2358) 0x4cce70 CBNZ	X26, 4ccf44

  (2358) 0x4cce74 LDR	D18, [X30, X4,LSL #3]

  (2358) 0x4cce78 LDR	D19, [X19, X4,LSL #3]

  (2358) 0x4cce7c FDIV	D31, D16, D18

  (2358) 0x4cce80 FADD	D22, D19, D31

  (2358) 0x4cce84 STR	D22, [X19, X4,LSL #3]

  (2358) 0x4cce88 ADD	X4, X4, #1

  (2358) 0x4cce8c CMP	X21, X4

  (2358) 0x4cce90 B.NE	4cce20

(2342) 0x4cce94 LDP	X12, X30, [SP, #192]

(2342) 0x4cce98 SUB	X21, X21, #1

(2342) 0x4cce9c ADD	X17, X9, #8

(2342) 0x4ccea0 PTRUE	P3.B, ALL

  (2359) 0x4ccea4 LDR	X8, [X27, X21,LSL #3]

  (2359) 0x4ccea8 LDR	X13, [X18, X21,LSL #3]

  (2359) 0x4cceac LDR	D21, [X12, X21,LSL #3]

  (2359) 0x4cceb0 CMP	X8, X13

  (2359) 0x4cceb4 B.GE	4ccef4

  (2359) 0x4cceb8 ADD	X5, X23, X8,LSL #3

  (2359) 0x4ccebc MOVZ	X3, #0

  (2359) 0x4ccec0 SUB	X14, X13, X8

  (2359) 0x4ccec4 ADD	X6, X24, X8,LSL #3

  (2359) 0x4ccec8 WHILELO	P4.D, XZR, X14

  (2359) 0x4ccecc DUP	Z20.D, #0

    (2361) 0x4cced0 LD1D	{Z29.D}, P4/Z, [X6, X3,LSL #3]

    (2361) 0x4cced4 LD1D	{Z24.D}, P4/Z, [X5, X3,LSL #3]

    (2361) 0x4cced8 LD1D	{Z25.D}, P4/Z, [X19, Z29.D,LSL #3]

    (2361) 0x4ccedc ADD	X3, X3, X20

    (2361) 0x4ccee0 FMLS	Z20.D, P4/M, Z25.D, Z24.D

    (2361) 0x4ccee4 WHILELO	P4.D, X3, X14

    (2361) 0x4ccee8 B.NE	4cced0

  (2359) 0x4cceec FADDV	D26, P3, Z20.D

  (2359) 0x4ccef0 FADD	D21, D21, D26

  (2359) 0x4ccef4 CBNZ	X26, 4ccf94

  (2359) 0x4ccef8 LDR	D2, [X30, X21,LSL #3]

  (2359) 0x4ccefc LDR	D1, [X19, X21,LSL #3]

  (2359) 0x4ccf00 FDIV	D3, D21, D2

  (2359) 0x4ccf04 FADD	D6, D1, D3

  (2359) 0x4ccf08 STR	D6, [X19, X21,LSL #3]

  (2359) 0x4ccf0c SUB	X21, X21, #1

  (2359) 0x4ccf10 CMN	X21, #1

  (2359) 0x4ccf14 B.NE	4ccea4

(2342) 0x4ccf18 ORR	X0, XZR, X28

(2342) 0x4ccf1c BL	5294c0

(2342) 0x4ccf20 LDR	X27, [SP, #208]

(2342) 0x4ccf24 LDR	X24, [SP, #240]

(2342) 0x4ccf28 ADD	X23, X27, #1

(2342) 0x4ccf2c STR	X23, [SP, #208]

(2342) 0x4ccf30 CMP	X24, X23

(2342) 0x4ccf34 B.NE	4cc3cc

0x4ccf38 B	4cc58c

  (2343) 0x4ccf3c MOVI	D6, #0

  (2343) 0x4ccf40 B	4cc890

  (2358) 0x4ccf44 LDR	X16, [X9, X4,LSL #3]

  (2358) 0x4ccf48 LDR	X15, [X17, X4,LSL #3]

  (2358) 0x4ccf4c CMP	X16, X15

  (2358) 0x4ccf50 B.GE	4cce74

  (2358) 0x4ccf54 ADD	X7, X11, X16,LSL #3

  (2358) 0x4ccf58 MOVZ	X0, #0

  (2358) 0x4ccf5c SUB	X1, X15, X16

  (2358) 0x4ccf60 ADD	X2, X10, X16,LSL #3

  (2358) 0x4ccf64 WHILELO	P2.D, XZR, X1

  (2358) 0x4ccf68 DUP	Z13.D, #0

    (2362) 0x4ccf6c LD1D	{Z10.D}, P2/Z, [X2, X0,LSL #3]

    (2362) 0x4ccf70 LD1D	{Z7.D}, P2/Z, [X7, X0,LSL #3]

    (2362) 0x4ccf74 LD1D	{Z17.D}, P2/Z, [X28, Z10.D,LSL #3]

    (2362) 0x4ccf78 ADD	X0, X0, X20

    (2362) 0x4ccf7c FMLS	Z13.D, P2/M, Z17.D, Z7.D

    (2362) 0x4ccf80 WHILELO	P2.D, X0, X1

    (2362) 0x4ccf84 B.NE	4ccf6c

  (2358) 0x4ccf88 FADDV	D4, P6, Z13.D

  (2358) 0x4ccf8c FADD	D16, D16, D4

  (2358) 0x4ccf90 B	4cce74

  (2359) 0x4ccf94 LDR	X16, [X9, X21,LSL #3]

  (2359) 0x4ccf98 LDR	X15, [X17, X21,LSL #3]

  (2359) 0x4ccf9c CMP	X16, X15

  (2359) 0x4ccfa0 B.GE	4ccef8

  (2359) 0x4ccfa4 ADD	X7, X11, X16,LSL #3

  (2359) 0x4ccfa8 MOVZ	X0, #0

  (2359) 0x4ccfac SUB	X1, X15, X16

  (2359) 0x4ccfb0 ADD	X2, X10, X16,LSL #3

  (2359) 0x4ccfb4 WHILELO	P5.D, XZR, X1

  (2359) 0x4ccfb8 DUP	Z23.D, #0

  (2359) 0x4ccfbc HINT	#0

    (2360) 0x4ccfc0 LD1D	{Z28.D}, P5/Z, [X2, X0,LSL #3]

    (2360) 0x4ccfc4 LD1D	{Z27.D}, P5/Z, [X7, X0,LSL #3]

    (2360) 0x4ccfc8 LD1D	{Z0.D}, P5/Z, [X28, Z28.D,LSL #3]

    (2360) 0x4ccfcc ADD	X0, X0, X20

    (2360) 0x4ccfd0 FMLS	Z23.D, P5/M, Z0.D, Z27.D

    (2360) 0x4ccfd4 WHILELO	P5.D, X0, X1

    (2360) 0x4ccfd8 B.NE	4ccfc0

  (2359) 0x4ccfdc FADDV	D30, P3, Z23.D

  (2359) 0x4ccfe0 FADD	D21, D21, D30

  (2359) 0x4ccfe4 B	4ccef8

  (2343) 0x4ccfe8 MOVI	D6, #0

  (2343) 0x4ccfec B	4cc6f4

  (2344) 0x4ccff0 MOVI	D4, #0

  (2344) 0x4ccff4 B	4cc954

(2377) 0x4ccff8 FMOV	D2, D13

(2377) 0x4ccffc FMOV	D1, D14

(2377) 0x4cd000 ORR	X7, XZR, X20

(2377) 0x4cd004 FMOV	D0, D15

(2377) 0x4cd008 ORR	X6, XZR, X23

(2377) 0x4cd00c ORR	X5, XZR, X28

(2377) 0x4cd010 MOVZ	X4, #0

(2377) 0x4cd014 MOVZ	X3, #1

(2377) 0x4cd018 ORR	X2, XZR, X21

(2377) 0x4cd01c ORR	X1, XZR, X24

(2377) 0x4cd020 ORR	X0, XZR, X22

(2377) 0x4cd024 ADD	X19, X19, #1

(2377) 0x4cd028 BL	4aac2c

(2377) 0x4cd02c B	4cc0a8

(2377) 0x4cd030 CMP	X25, #16

(2377) 0x4cd034 B.NE	4cc02c

(2377) 0x4cd038 B	4cc110

(2342) 0x4cd03c ORR	X0, XZR, X25

(2342) 0x4cd040 STR	X9, [SP, #184]

(2342) 0x4cd044 STR	X11, [SP, #224]

(2342) 0x4cd048 BL	4e6b60

(2342) 0x4cd04c LDR	X5, [X25, #112]

(2342) 0x4cd050 LDP	X10, X11, [SP, #216]

(2342) 0x4cd054 LDR	X9, [SP, #184]

(2342) 0x4cd058 B	4ccbf0

0x4cd05c ORR	X8, XZR, X27

0x4cd060 LDR	X27, [SP, #200]

0x4cd064 ORR	X5, XZR, X19

0x4cd068 CNTD	X22, ALL

0x4cd06c LDP	X24, X19, [SP, #184]

0x4cd070 STP	D9, D10, [SP, #112]

0x4cd074 STP	X26, X5, [SP, #184]

0x4cd078 STR	X8, [SP, #224]

(2366) 0x4cd07c LDP	X9, X11, [X24, #56]

(2366) 0x4cd080 LDR	X26, [X11, #24]

(2366) 0x4cd084 LDP	X12, X10, [X11]

(2366) 0x4cd088 LDP	X28, X21, [X9]

(2366) 0x4cd08c UBFM	X0, X26, #61, #60

(2366) 0x4cd090 STR	X12, [SP, #216]

(2366) 0x4cd094 LDR	X13, [X11, #48]

(2366) 0x4cd098 LDR	X23, [X9, #16]

(2366) 0x4cd09c LDR	X20, [X9, #48]

(2366) 0x4cd0a0 STP	X13, X10, [SP, #200]

(2366) 0x4cd0a4 BL	5293e8

(2366) 0x4cd0a8 ORR	X25, XZR, X0

(2366) 0x4cd0ac LDR	X0, [X24]

(2366) 0x4cd0b0 ADD	X1, SP, #280

(2366) 0x4cd0b4 BL	52b320

(2366) 0x4cd0b8 LDR	X15, [SP, #280]

(2366) 0x4cd0bc LDP	X11, X10, [SP, #200]

(2366) 0x4cd0c0 LDR	X9, [SP, #216]

(2366) 0x4cd0c4 CMP	X15, #1

(2366) 0x4cd0c8 B.GT	4cd6d8

(2366) 0x4cd0cc MOVZ	X1, #0

(2366) 0x4cd0d0 ADD	X12, X28, #8

(2366) 0x4cd0d4 PTRUE	P6.B, ALL

(2366) 0x4cd0d8 ADD	X13, X9, #8

(2366) 0x4cd0dc CMP	X23, #0

(2366) 0x4cd0e0 B.LE	4cd5c0

(2366) 0x4cd0e4 LDR	X8, [SP, #184]

  (2367) 0x4cd0e8 LDR	X2, [X28, X1,LSL #3]

  (2367) 0x4cd0ec LDR	X6, [X12, X1,LSL #3]

  (2367) 0x4cd0f0 LDR	D21, [X27, X1,LSL #3]

  (2367) 0x4cd0f4 CMP	X2, X6

  (2367) 0x4cd0f8 B.GE	4cd5f8

  (2367) 0x4cd0fc ADD	X14, X20, X2,LSL #3

  (2367) 0x4cd100 MOVZ	X30, #0

  (2367) 0x4cd104 SUB	X3, X6, X2

  (2367) 0x4cd108 ADD	X7, X21, X2,LSL #3

  (2367) 0x4cd10c WHILELO	P7.D, XZR, X3

  (2367) 0x4cd110 DUP	Z20.D, #0

  (2367) 0x4cd114 HINT	#0

  (2367) 0x4cd118 HINT	#0

  (2367) 0x4cd11c HINT	#0

    (2374) 0x4cd120 LD1D	{Z22.D}, P7/Z, [X7, X30,LSL #3]

    (2374) 0x4cd124 LD1D	{Z23.D}, P7/Z, [X14, X30,LSL #3]

    (2374) 0x4cd128 LD1D	{Z29.D}, P7/Z, [X19, Z22.D,LSL #3]

    (2374) 0x4cd12c ADD	X30, X30, X22

    (2374) 0x4cd130 FMLS	Z20.D, P7/M, Z29.D, Z23.D

    (2374) 0x4cd134 WHILELO	P7.D, X30, X3

    (2374) 0x4cd138 B.NE	4cd120

  (2367) 0x4cd13c FADDV	D24, P6, Z20.D

  (2367) 0x4cd140 FADD	D21, D21, D24

  (2367) 0x4cd144 CBNZ	X26, 4cd600

  (2367) 0x4cd148 LDR	D25, [X8, X1,LSL #3]

  (2367) 0x4cd14c FDIV	D26, D21, D25

  (2367) 0x4cd150 SUB	X0, X6, X2

  (2367) 0x4cd154 FMUL	D31, D26, D11

  (2367) 0x4cd158 ANDS	X14, X0, #0x7

  (2367) 0x4cd15c B.EQ	4cd25c

  (2367) 0x4cd160 CMP	X14, #1

  (2367) 0x4cd164 B.EQ	4cd238

  (2367) 0x4cd168 CMP	X14, #2

  (2367) 0x4cd16c B.EQ	4cd21c

  (2367) 0x4cd170 CMP	X14, #3

  (2367) 0x4cd174 B.EQ	4cd200

  (2367) 0x4cd178 CMP	X14, #4

  (2367) 0x4cd17c B.EQ	4cd1e4

  (2367) 0x4cd180 CMP	X14, #5

  (2367) 0x4cd184 B.EQ	4cd1c8

  (2367) 0x4cd188 CMP	X14, #6

  (2367) 0x4cd18c B.EQ	4cd1ac

  (2367) 0x4cd190 LDR	X3, [X21, X2,LSL #3]

  (2367) 0x4cd194 LDR	D15, [X20, X2,LSL #3]

  (2367) 0x4cd198 ADD	X2, X2, #1

  (2367) 0x4cd19c UBFM	X7, X3, #61, #60

  (2367) 0x4cd1a0 LDR	D0, [X19, X7]

  (2367) 0x4cd1a4 FMADD	D1, D31, D15, D0

  (2367) 0x4cd1a8 STR	D1, [X19, X7]

  (2367) 0x4cd1ac LDR	X30, [X21, X2,LSL #3]

  (2367) 0x4cd1b0 LDR	D2, [X20, X2,LSL #3]

  (2367) 0x4cd1b4 ADD	X2, X2, #1

  (2367) 0x4cd1b8 UBFM	X4, X30, #61, #60

  (2367) 0x4cd1bc LDR	D3, [X19, X4]

  (2367) 0x4cd1c0 FMADD	D4, D31, D2, D3

  (2367) 0x4cd1c4 STR	D4, [X19, X4]

  (2367) 0x4cd1c8 LDR	X15, [X21, X2,LSL #3]

  (2367) 0x4cd1cc LDR	D5, [X20, X2,LSL #3]

  (2367) 0x4cd1d0 ADD	X2, X2, #1

  (2367) 0x4cd1d4 UBFM	X17, X15, #61, #60

  (2367) 0x4cd1d8 LDR	D6, [X19, X17]

  (2367) 0x4cd1dc FMADD	D7, D31, D5, D6

  (2367) 0x4cd1e0 STR	D7, [X19, X17]

  (2367) 0x4cd1e4 LDR	X18, [X21, X2,LSL #3]

  (2367) 0x4cd1e8 LDR	D9, [X20, X2,LSL #3]

  (2367) 0x4cd1ec ADD	X2, X2, #1

  (2367) 0x4cd1f0 UBFM	X16, X18, #61, #60

  (2367) 0x4cd1f4 LDR	D10, [X19, X16]

  (2367) 0x4cd1f8 FMADD	D16, D31, D9, D10

  (2367) 0x4cd1fc STR	D16, [X19, X16]

  (2367) 0x4cd200 LDR	X5, [X21, X2,LSL #3]

  (2367) 0x4cd204 LDR	D17, [X20, X2,LSL #3]

  (2367) 0x4cd208 ADD	X2, X2, #1

  (2367) 0x4cd20c UBFM	X0, X5, #61, #60

  (2367) 0x4cd210 LDR	D18, [X19, X0]

  (2367) 0x4cd214 FMADD	D19, D31, D17, D18

  (2367) 0x4cd218 STR	D19, [X19, X0]

  (2367) 0x4cd21c LDR	X14, [X21, X2,LSL #3]

  (2367) 0x4cd220 LDR	D21, [X20, X2,LSL #3]

  (2367) 0x4cd224 ADD	X2, X2, #1

  (2367) 0x4cd228 UBFM	X3, X14, #61, #60

  (2367) 0x4cd22c LDR	D20, [X19, X3]

  (2367) 0x4cd230 FMADD	D22, D31, D21, D20

  (2367) 0x4cd234 STR	D22, [X19, X3]

  (2367) 0x4cd238 LDR	X7, [X21, X2,LSL #3]

  (2367) 0x4cd23c LDR	D23, [X20, X2,LSL #3]

  (2367) 0x4cd240 ADD	X2, X2, #1

  (2367) 0x4cd244 UBFM	X30, X7, #61, #60

  (2367) 0x4cd248 LDR	D29, [X19, X30]

  (2367) 0x4cd24c FMADD	D24, D31, D23, D29

  (2367) 0x4cd250 STR	D24, [X19, X30]

  (2367) 0x4cd254 CMP	X2, X6

  (2367) 0x4cd258 B.EQ	4cd344

    (2372) 0x4cd25c LDR	X4, [X21, X2,LSL #3]

    (2372) 0x4cd260 ADD	X5, X2, #1

    (2372) 0x4cd264 ADD	X30, X2, #2

    (2372) 0x4cd268 ADD	X18, X2, #3

    (2372) 0x4cd26c ADD	X17, X2, #4

    (2372) 0x4cd270 LDR	D25, [X20, X2,LSL #3]

    (2372) 0x4cd274 ADD	X16, X2, #5

    (2372) 0x4cd278 ADD	X15, X2, #6

    (2372) 0x4cd27c ADD	X14, X2, #7

    (2372) 0x4cd280 ADD	X2, X2, #8

    (2372) 0x4cd284 LDR	X0, [X21, X5,LSL #3]

    (2372) 0x4cd288 UBFM	X7, X4, #61, #60

    (2372) 0x4cd28c LDR	X4, [X21, X30,LSL #3]

    (2372) 0x4cd290 LDR	D26, [X19, X7]

    (2372) 0x4cd294 UBFM	X3, X0, #61, #60

    (2372) 0x4cd298 UBFM	X0, X4, #61, #60

    (2372) 0x4cd29c LDR	X4, [X21, X17,LSL #3]

    (2372) 0x4cd2a0 FMADD	D28, D31, D25, D26

    (2372) 0x4cd2a4 STR	D28, [X19, X7]

    (2372) 0x4cd2a8 LDR	D27, [X20, X5,LSL #3]

    (2372) 0x4cd2ac LDR	D30, [X19, X3]

    (2372) 0x4cd2b0 LDR	X5, [X21, X18,LSL #3]

    (2372) 0x4cd2b4 FMADD	D12, D31, D27, D30

    (2372) 0x4cd2b8 UBFM	X7, X5, #61, #60

    (2372) 0x4cd2bc UBFM	X5, X4, #61, #60

    (2372) 0x4cd2c0 STR	D12, [X19, X3]

    (2372) 0x4cd2c4 LDR	D14, [X20, X30,LSL #3]

    (2372) 0x4cd2c8 LDR	D13, [X19, X0]

    (2372) 0x4cd2cc LDR	X30, [X21, X16,LSL #3]

    (2372) 0x4cd2d0 LDR	X3, [X21, X15,LSL #3]

    (2372) 0x4cd2d4 FMADD	D15, D31, D14, D13

    (2372) 0x4cd2d8 UBFM	X4, X30, #61, #60

    (2372) 0x4cd2dc UBFM	X30, X3, #61, #60

    (2372) 0x4cd2e0 STR	D15, [X19, X0]

    (2372) 0x4cd2e4 LDR	D0, [X20, X18,LSL #3]

    (2372) 0x4cd2e8 LDR	D1, [X19, X7]

    (2372) 0x4cd2ec LDR	X18, [X21, X14,LSL #3]

    (2372) 0x4cd2f0 FMADD	D2, D31, D0, D1

    (2372) 0x4cd2f4 UBFM	X0, X18, #61, #60

    (2372) 0x4cd2f8 STR	D2, [X19, X7]

    (2372) 0x4cd2fc LDR	D3, [X20, X17,LSL #3]

    (2372) 0x4cd300 LDR	D4, [X19, X5]

    (2372) 0x4cd304 FMADD	D5, D31, D3, D4

    (2372) 0x4cd308 STR	D5, [X19, X5]

    (2372) 0x4cd30c LDR	D7, [X20, X16,LSL #3]

    (2372) 0x4cd310 LDR	D6, [X19, X4]

    (2372) 0x4cd314 FMADD	D9, D31, D7, D6

    (2372) 0x4cd318 STR	D9, [X19, X4]

    (2372) 0x4cd31c LDR	D10, [X20, X15,LSL #3]

    (2372) 0x4cd320 LDR	D16, [X19, X30]

    (2372) 0x4cd324 FMADD	D17, D31, D10, D16

    (2372) 0x4cd328 STR	D17, [X19, X30]

    (2372) 0x4cd32c LDR	D18, [X20, X14,LSL #3]

    (2372) 0x4cd330 LDR	D19, [X19, X0]

    (2372) 0x4cd334 FMADD	D21, D31, D18, D19

    (2372) 0x4cd338 STR	D21, [X19, X0]

    (2372) 0x4cd33c CMP	X2, X6

    (2372) 0x4cd340 B.NE	4cd25c

  (2367) 0x4cd344 PTRUE	P6.B, ALL

  (2367) 0x4cd348 ADD	X1, X1, #1

  (2367) 0x4cd34c CMP	X23, X1

  (2367) 0x4cd350 B.NE	4cd0e8

(2366) 0x4cd354 LDR	X8, [SP, #184]

(2366) 0x4cd358 SUB	X23, X23, #1

(2366) 0x4cd35c ADD	X6, X9, #8

(2366) 0x4cd360 PTRUE	P1.B, ALL

  (2368) 0x4cd364 LDR	X1, [X28, X23,LSL #3]

  (2368) 0x4cd368 LDR	X5, [X12, X23,LSL #3]

  (2368) 0x4cd36c LDR	D31, [X27, X23,LSL #3]

  (2368) 0x4cd370 CMP	X1, X5

  (2368) 0x4cd374 B.GE	4cd664

  (2368) 0x4cd378 ADD	X13, X20, X1,LSL #3

  (2368) 0x4cd37c MOVZ	X16, #0

  (2368) 0x4cd380 SUB	X2, X5, X1

  (2368) 0x4cd384 ADD	X17, X21, X1,LSL #3

  (2368) 0x4cd388 WHILELO	P2.D, XZR, X2

  (2368) 0x4cd38c DUP	Z20.D, #0

    (2371) 0x4cd390 LD1D	{Z22.D}, P2/Z, [X17, X16,LSL #3]

    (2371) 0x4cd394 LD1D	{Z23.D}, P2/Z, [X13, X16,LSL #3]

    (2371) 0x4cd398 LD1D	{Z29.D}, P2/Z, [X19, Z22.D,LSL #3]

    (2371) 0x4cd39c ADD	X16, X16, X22

    (2371) 0x4cd3a0 FMLS	Z20.D, P2/M, Z29.D, Z23.D

    (2371) 0x4cd3a4 WHILELO	P2.D, X16, X2

    (2371) 0x4cd3a8 B.NE	4cd390

  (2368) 0x4cd3ac FADDV	D24, P1, Z20.D

  (2368) 0x4cd3b0 FADD	D31, D31, D24

  (2368) 0x4cd3b4 CBNZ	X26, 4cd66c

  (2368) 0x4cd3b8 LDR	D25, [X8, X23,LSL #3]

  (2368) 0x4cd3bc FDIV	D26, D31, D25

  (2368) 0x4cd3c0 SUB	X18, X5, X1

  (2368) 0x4cd3c4 FMUL	D15, D11, D26

  (2368) 0x4cd3c8 ANDS	X0, X18, #0x7

  (2368) 0x4cd3cc B.EQ	4cd4cc

  (2368) 0x4cd3d0 CMP	X0, #1

  (2368) 0x4cd3d4 B.EQ	4cd4a8

  (2368) 0x4cd3d8 CMP	X0, #2

  (2368) 0x4cd3dc B.EQ	4cd48c

  (2368) 0x4cd3e0 CMP	X0, #3

  (2368) 0x4cd3e4 B.EQ	4cd470

  (2368) 0x4cd3e8 CMP	X0, #4

  (2368) 0x4cd3ec B.EQ	4cd454

  (2368) 0x4cd3f0 CMP	X0, #5

  (2368) 0x4cd3f4 B.EQ	4cd438

  (2368) 0x4cd3f8 CMP	X0, #6

  (2368) 0x4cd3fc B.EQ	4cd41c

  (2368) 0x4cd400 LDR	X13, [X21, X1,LSL #3]

  (2368) 0x4cd404 LDR	D0, [X20, X1,LSL #3]

  (2368) 0x4cd408 ADD	X1, X1, #1

  (2368) 0x4cd40c UBFM	X2, X13, #61, #60

  (2368) 0x4cd410 LDR	D1, [X19, X2]

  (2368) 0x4cd414 FMADD	D2, D15, D0, D1

  (2368) 0x4cd418 STR	D2, [X19, X2]

  (2368) 0x4cd41c LDR	X17, [X21, X1,LSL #3]

  (2368) 0x4cd420 LDR	D3, [X20, X1,LSL #3]

  (2368) 0x4cd424 ADD	X1, X1, #1

  (2368) 0x4cd428 UBFM	X16, X17, #61, #60

  (2368) 0x4cd42c LDR	D4, [X19, X16]

  (2368) 0x4cd430 FMADD	D5, D15, D3, D4

  (2368) 0x4cd434 STR	D5, [X19, X16]

  (2368) 0x4cd438 LDR	X15, [X21, X1,LSL #3]

  (2368) 0x4cd43c LDR	D7, [X20, X1,LSL #3]

  (2368) 0x4cd440 ADD	X1, X1, #1

  (2368) 0x4cd444 UBFM	X14, X15, #61, #60

  (2368) 0x4cd448 LDR	D6, [X19, X14]

  (2368) 0x4cd44c FMADD	D9, D15, D7, D6

  (2368) 0x4cd450 STR	D9, [X19, X14]

  (2368) 0x4cd454 LDR	X7, [X21, X1,LSL #3]

  (2368) 0x4cd458 LDR	D10, [X20, X1,LSL #3]

  (2368) 0x4cd45c ADD	X1, X1, #1

  (2368) 0x4cd460 UBFM	X4, X7, #61, #60

  (2368) 0x4cd464 LDR	D16, [X19, X4]

  (2368) 0x4cd468 FMADD	D17, D15, D10, D16

  (2368) 0x4cd46c STR	D17, [X19, X4]

  (2368) 0x4cd470 LDR	X3, [X21, X1,LSL #3]

  (2368) 0x4cd474 LDR	D18, [X20, X1,LSL #3]

  (2368) 0x4cd478 ADD	X1, X1, #1

  (2368) 0x4cd47c UBFM	X30, X3, #61, #60

  (2368) 0x4cd480 LDR	D19, [X19, X30]

  (2368) 0x4cd484 FMADD	D21, D15, D18, D19

  (2368) 0x4cd488 STR	D21, [X19, X30]

  (2368) 0x4cd48c LDR	X18, [X21, X1,LSL #3]

  (2368) 0x4cd490 LDR	D31, [X20, X1,LSL #3]

  (2368) 0x4cd494 ADD	X1, X1, #1

  (2368) 0x4cd498 UBFM	X0, X18, #61, #60

  (2368) 0x4cd49c LDR	D20, [X19, X0]

  (2368) 0x4cd4a0 FMADD	D22, D15, D31, D20

  (2368) 0x4cd4a4 STR	D22, [X19, X0]

  (2368) 0x4cd4a8 LDR	X13, [X21, X1,LSL #3]

  (2368) 0x4cd4ac LDR	D23, [X20, X1,LSL #3]

  (2368) 0x4cd4b0 ADD	X1, X1, #1

  (2368) 0x4cd4b4 UBFM	X2, X13, #61, #60

  (2368) 0x4cd4b8 LDR	D29, [X19, X2]

  (2368) 0x4cd4bc FMADD	D24, D15, D23, D29

  (2368) 0x4cd4c0 STR	D24, [X19, X2]

  (2368) 0x4cd4c4 CMP	X1, X5

  (2368) 0x4cd4c8 B.EQ	4cd5b4

    (2369) 0x4cd4cc LDR	X7, [X21, X1,LSL #3]

    (2369) 0x4cd4d0 ADD	X4, X1, #1

    (2369) 0x4cd4d4 ADD	X30, X1, #2

    (2369) 0x4cd4d8 ADD	X17, X1, #3

    (2369) 0x4cd4dc ADD	X16, X1, #4

    (2369) 0x4cd4e0 LDR	D25, [X20, X1,LSL #3]

    (2369) 0x4cd4e4 ADD	X15, X1, #5

    (2369) 0x4cd4e8 ADD	X14, X1, #6

    (2369) 0x4cd4ec ADD	X18, X1, #7

    (2369) 0x4cd4f0 ADD	X1, X1, #8

    (2369) 0x4cd4f4 LDR	X0, [X21, X4,LSL #3]

    (2369) 0x4cd4f8 UBFM	X3, X7, #61, #60

    (2369) 0x4cd4fc LDR	X2, [X21, X30,LSL #3]

    (2369) 0x4cd500 LDR	D26, [X19, X3]

    (2369) 0x4cd504 UBFM	X13, X0, #61, #60

    (2369) 0x4cd508 LDR	X7, [X21, X17,LSL #3]

    (2369) 0x4cd50c UBFM	X0, X2, #61, #60

    (2369) 0x4cd510 FMADD	D28, D15, D25, D26

    (2369) 0x4cd514 UBFM	X7, X7, #61, #60

    (2369) 0x4cd518 STR	D28, [X19, X3]

    (2369) 0x4cd51c LDR	D27, [X20, X4,LSL #3]

    (2369) 0x4cd520 LDR	D30, [X19, X13]

    (2369) 0x4cd524 LDR	X4, [X21, X16,LSL #3]

    (2369) 0x4cd528 FMADD	D12, D15, D27, D30

    (2369) 0x4cd52c UBFM	X4, X4, #61, #60

    (2369) 0x4cd530 STR	D12, [X19, X13]

    (2369) 0x4cd534 LDR	D14, [X20, X30,LSL #3]

    (2369) 0x4cd538 LDR	D13, [X19, X0]

    (2369) 0x4cd53c LDR	X30, [X21, X15,LSL #3]

    (2369) 0x4cd540 LDR	X13, [X21, X14,LSL #3]

    (2369) 0x4cd544 FMADD	D0, D15, D14, D13

    (2369) 0x4cd548 UBFM	X3, X30, #61, #60

    (2369) 0x4cd54c UBFM	X2, X13, #61, #60

    (2369) 0x4cd550 STR	D0, [X19, X0]

    (2369) 0x4cd554 LDR	D1, [X20, X17,LSL #3]

    (2369) 0x4cd558 LDR	D2, [X19, X7]

    (2369) 0x4cd55c LDR	X17, [X21, X18,LSL #3]

    (2369) 0x4cd560 FMADD	D3, D15, D1, D2

    (2369) 0x4cd564 UBFM	X0, X17, #61, #60

    (2369) 0x4cd568 STR	D3, [X19, X7]

    (2369) 0x4cd56c LDR	D4, [X20, X16,LSL #3]

    (2369) 0x4cd570 LDR	D5, [X19, X4]

    (2369) 0x4cd574 FMADD	D7, D15, D4, D5

    (2369) 0x4cd578 STR	D7, [X19, X4]

    (2369) 0x4cd57c LDR	D6, [X20, X15,LSL #3]

    (2369) 0x4cd580 LDR	D9, [X19, X3]

    (2369) 0x4cd584 FMADD	D10, D15, D6, D9

    (2369) 0x4cd588 STR	D10, [X19, X3]

    (2369) 0x4cd58c LDR	D16, [X20, X14,LSL #3]

    (2369) 0x4cd590 LDR	D17, [X19, X2]

    (2369) 0x4cd594 FMADD	D18, D15, D16, D17

    (2369) 0x4cd598 STR	D18, [X19, X2]

    (2369) 0x4cd59c LDR	D19, [X20, X18,LSL #3]

    (2369) 0x4cd5a0 LDR	D21, [X19, X0]

    (2369) 0x4cd5a4 FMADD	D31, D15, D19, D21

    (2369) 0x4cd5a8 STR	D31, [X19, X0]

    (2369) 0x4cd5ac CMP	X1, X5

    (2369) 0x4cd5b0 B.NE	4cd4cc

  (2368) 0x4cd5b4 SUB	X23, X23, #1

  (2368) 0x4cd5b8 CMN	X23, #1

  (2368) 0x4cd5bc B.NE	4cd364

(2366) 0x4cd5c0 ORR	X0, XZR, X25

(2366) 0x4cd5c4 BL	5294c0

(2366) 0x4cd5c8 LDR	X28, [SP, #192]

(2366) 0x4cd5cc LDR	X21, [SP, #224]

(2366) 0x4cd5d0 ADD	X20, X28, #1

(2366) 0x4cd5d4 STR	X20, [SP, #192]

(2366) 0x4cd5d8 CMP	X20, X21

(2366) 0x4cd5dc B.NE	4cd07c

0x4cd5e0 LDR	D15, [SP, #160]

0x4cd5e4 LDP	X25, X26, [SP, #80]

0x4cd5e8 LDP	D9, D10, [SP, #112]

0x4cd5ec LDP	D11, D12, [SP, #128]

0x4cd5f0 LDP	D13, D14, [SP, #144]

0x4cd5f4 B	4cc07c

  (2367) 0x4cd5f8 PTRUE	P6.B, ALL

  (2367) 0x4cd5fc CBZ	X26, 4cd348

  (2367) 0x4cd600 LDR	X4, [X9, X1,LSL #3]

  (2367) 0x4cd604 LDR	X15, [X13, X1,LSL #3]

  (2367) 0x4cd608 CMP	X4, X15

  (2367) 0x4cd60c B.GE	4cd64c

  (2367) 0x4cd610 ADD	X17, X11, X4,LSL #3

  (2367) 0x4cd614 MOVZ	X5, #0

  (2367) 0x4cd618 SUB	X18, X15, X4

  (2367) 0x4cd61c ADD	X16, X10, X4,LSL #3

  (2367) 0x4cd620 WHILELO	P0.D, XZR, X18

  (2367) 0x4cd624 DUP	Z28.D, #0

    (2373) 0x4cd628 LD1D	{Z27.D}, P0/Z, [X16, X5,LSL #3]

    (2373) 0x4cd62c LD1D	{Z30.D}, P0/Z, [X17, X5,LSL #3]

    (2373) 0x4cd630 LD1D	{Z12.D}, P0/Z, [X25, Z27.D,LSL #3]

    (2373) 0x4cd634 ADD	X5, X5, X22

    (2373) 0x4cd638 FMLS	Z28.D, P0/M, Z12.D, Z30.D

    (2373) 0x4cd63c WHILELO	P0.D, X5, X18

    (2373) 0x4cd640 B.NE	4cd628

  (2367) 0x4cd644 FADDV	D14, P6, Z28.D

  (2367) 0x4cd648 FADD	D21, D21, D14

  (2367) 0x4cd64c LDR	D13, [X8, X1,LSL #3]

  (2367) 0x4cd650 PTRUE	P6.B, ALL

  (2367) 0x4cd654 FDIV	D26, D21, D13

  (2367) 0x4cd658 CMP	X2, X6

  (2367) 0x4cd65c B.LT	4cd150

  (2367) 0x4cd660 B	4cd348

  (2368) 0x4cd664 PTRUE	P1.B, ALL

  (2368) 0x4cd668 CBZ	X26, 4cd5b4

  (2368) 0x4cd66c LDR	X15, [X9, X23,LSL #3]

  (2368) 0x4cd670 LDR	X14, [X6, X23,LSL #3]

  (2368) 0x4cd674 CMP	X15, X14

  (2368) 0x4cd678 B.GE	4cd6c4

  (2368) 0x4cd67c ADD	X7, X11, X15,LSL #3

  (2368) 0x4cd680 MOVZ	X30, #0

  (2368) 0x4cd684 SUB	X4, X14, X15

  (2368) 0x4cd688 ADD	X3, X10, X15,LSL #3

  (2368) 0x4cd68c WHILELO	P3.D, XZR, X4

  (2368) 0x4cd690 DUP	Z28.D, #0

  (2368) 0x4cd694 HINT	#0

  (2368) 0x4cd698 HINT	#0

  (2368) 0x4cd69c HINT	#0

    (2370) 0x4cd6a0 LD1D	{Z27.D}, P3/Z, [X3, X30,LSL #3]

    (2370) 0x4cd6a4 LD1D	{Z30.D}, P3/Z, [X7, X30,LSL #3]

    (2370) 0x4cd6a8 LD1D	{Z12.D}, P3/Z, [X25, Z27.D,LSL #3]

    (2370) 0x4cd6ac ADD	X30, X30, X22

    (2370) 0x4cd6b0 FMLS	Z28.D, P3/M, Z12.D, Z30.D

    (2370) 0x4cd6b4 WHILELO	P3.D, X30, X4

    (2370) 0x4cd6b8 B.NE	4cd6a0

  (2368) 0x4cd6bc FADDV	D14, P1, Z28.D

  (2368) 0x4cd6c0 FADD	D31, D31, D14

  (2368) 0x4cd6c4 LDR	D13, [X8, X23,LSL #3]

  (2368) 0x4cd6c8 FDIV	D26, D31, D13

  (2368) 0x4cd6cc CMP	X1, X5

  (2368) 0x4cd6d0 B.LT	4cd3c0

  (2368) 0x4cd6d4 B	4cd5b4

(2366) 0x4cd6d8 LDR	X18, [X24, #112]

(2366) 0x4cd6dc CBZ	X18, 4cd8dc

(2366) 0x4cd6e0 LDR	X16, [X18, #8]

(2366) 0x4cd6e4 STR	X18, [SP, #216]

(2366) 0x4cd6e8 LDR	X17, [X18, #24]

(2366) 0x4cd6ec STR	X11, [SP, #248]

(2366) 0x4cd6f0 UBFM	X30, X16, #61, #60

(2366) 0x4cd6f4 LDR	X7, [X17, X30]

(2366) 0x4cd6f8 STP	X30, X16, [SP, #200]

(2366) 0x4cd6fc STP	X9, X10, [SP, #232]

(2366) 0x4cd700 UBFM	X0, X7, #61, #60

(2366) 0x4cd704 BL	5293e8

(2366) 0x4cd708 LDP	X14, X6, [SP, #200]

(2366) 0x4cd70c ORR	X2, XZR, X0

(2366) 0x4cd710 LDP	X8, X9, [SP, #232]

(2366) 0x4cd714 LDR	X1, [SP, #216]

(2366) 0x4cd718 LDR	X11, [SP, #248]

(2366) 0x4cd71c CMP	X6, #0

(2366) 0x4cd720 B.LE	4cd8a0

(2366) 0x4cd724 MOVZ	X6, #0

(2366) 0x4cd728 LDR	X5, [X1, #24]

(2366) 0x4cd72c ADD	X10, X14, X5

  (2375) 0x4cd730 LDP	X0, X12, [X5]

  (2375) 0x4cd734 CMP	X0, X12

  (2375) 0x4cd738 B.GE	4cd894

  (2375) 0x4cd73c SUB	X3, XZR, X0,LSL #3

  (2375) 0x4cd740 SUB	X4, X12, X0

  (2375) 0x4cd744 LDR	X7, [X1, #32]

  (2375) 0x4cd748 ANDS	X13, X4, #0x7

  (2375) 0x4cd74c ORR	X14, XZR, X0

  (2375) 0x4cd750 ADD	X15, X3, X6,LSL #3

  (2375) 0x4cd754 ADD	X3, X2, X15

  (2375) 0x4cd758 B.EQ	4cd804

  (2375) 0x4cd75c CMP	X13, #1

  (2375) 0x4cd760 B.EQ	4cd7ec

  (2375) 0x4cd764 CMP	X13, #2

  (2375) 0x4cd768 B.EQ	4cd7dc

  (2375) 0x4cd76c CMP	X13, #3

  (2375) 0x4cd770 B.EQ	4cd7cc

  (2375) 0x4cd774 CMP	X13, #4

  (2375) 0x4cd778 B.EQ	4cd7bc

  (2375) 0x4cd77c CMP	X13, #5

  (2375) 0x4cd780 B.EQ	4cd7ac

  (2375) 0x4cd784 CMP	X13, #6

  (2375) 0x4cd788 B.EQ	4cd79c

  (2375) 0x4cd78c LDR	X18, [X7, X0,LSL #3]

  (2375) 0x4cd790 LDR	D31, [X19, X18,LSL #3]

  (2375) 0x4cd794 STR	D31, [X3, X0,LSL #3]

  (2375) 0x4cd798 ADD	X0, X0, #1

  (2375) 0x4cd79c LDR	X16, [X7, X0,LSL #3]

  (2375) 0x4cd7a0 LDR	D0, [X19, X16,LSL #3]

  (2375) 0x4cd7a4 STR	D0, [X3, X0,LSL #3]

  (2375) 0x4cd7a8 ADD	X0, X0, #1

  (2375) 0x4cd7ac LDR	X17, [X7, X0,LSL #3]

  (2375) 0x4cd7b0 LDR	D1, [X19, X17,LSL #3]

  (2375) 0x4cd7b4 STR	D1, [X3, X0,LSL #3]

  (2375) 0x4cd7b8 ADD	X0, X0, #1

  (2375) 0x4cd7bc LDR	X30, [X7, X0,LSL #3]

  (2375) 0x4cd7c0 LDR	D2, [X19, X30,LSL #3]

  (2375) 0x4cd7c4 STR	D2, [X3, X0,LSL #3]

  (2375) 0x4cd7c8 ADD	X0, X0, #1

  (2375) 0x4cd7cc LDR	X4, [X7, X0,LSL #3]

  (2375) 0x4cd7d0 LDR	D3, [X19, X4,LSL #3]

  (2375) 0x4cd7d4 STR	D3, [X3, X0,LSL #3]

  (2375) 0x4cd7d8 ADD	X0, X0, #1

  (2375) 0x4cd7dc LDR	X13, [X7, X0,LSL #3]

  (2375) 0x4cd7e0 LDR	D4, [X19, X13,LSL #3]

  (2375) 0x4cd7e4 STR	D4, [X3, X0,LSL #3]

  (2375) 0x4cd7e8 ADD	X0, X0, #1

  (2375) 0x4cd7ec LDR	X15, [X7, X0,LSL #3]

  (2375) 0x4cd7f0 LDR	D5, [X19, X15,LSL #3]

  (2375) 0x4cd7f4 STR	D5, [X3, X0,LSL #3]

  (2375) 0x4cd7f8 ADD	X0, X0, #1

  (2375) 0x4cd7fc CMP	X0, X12

  (2375) 0x4cd800 B.EQ	4cd88c

    (2376) 0x4cd804 LDR	X30, [X7, X0,LSL #3]

    (2376) 0x4cd808 ADD	X4, X0, #1

    (2376) 0x4cd80c ADD	X17, X0, #2

    (2376) 0x4cd810 ADD	X16, X0, #3

    (2376) 0x4cd814 ADD	X13, X0, #4

    (2376) 0x4cd818 LDR	X18, [X7, X4,LSL #3]

    (2376) 0x4cd81c LDR	X15, [X7, X17,LSL #3]

    (2376) 0x4cd820 LDR	D6, [X19, X30,LSL #3]

    (2376) 0x4cd824 LDR	X30, [X7, X13,LSL #3]

    (2376) 0x4cd828 STR	D6, [X3, X0,LSL #3]

    (2376) 0x4cd82c LDR	D7, [X19, X18,LSL #3]

    (2376) 0x4cd830 LDR	X18, [X7, X16,LSL #3]

    (2376) 0x4cd834 STR	D7, [X3, X4,LSL #3]

    (2376) 0x4cd838 ADD	X4, X0, #5

    (2376) 0x4cd83c LDR	D9, [X19, X15,LSL #3]

    (2376) 0x4cd840 LDR	X15, [X7, X4,LSL #3]

    (2376) 0x4cd844 STR	D9, [X3, X17,LSL #3]

    (2376) 0x4cd848 ADD	X17, X0, #6

    (2376) 0x4cd84c LDR	D10, [X19, X18,LSL #3]

    (2376) 0x4cd850 LDR	X18, [X7, X17,LSL #3]

    (2376) 0x4cd854 STR	D10, [X3, X16,LSL #3]

    (2376) 0x4cd858 ADD	X16, X0, #7

    (2376) 0x4cd85c ADD	X0, X0, #8

    (2376) 0x4cd860 LDR	D16, [X19, X30,LSL #3]

    (2376) 0x4cd864 STR	D16, [X3, X13,LSL #3]

    (2376) 0x4cd868 LDR	D17, [X19, X15,LSL #3]

    (2376) 0x4cd86c LDR	X13, [X7, X16,LSL #3]

    (2376) 0x4cd870 STR	D17, [X3, X4,LSL #3]

    (2376) 0x4cd874 LDR	D18, [X19, X18,LSL #3]

    (2376) 0x4cd878 STR	D18, [X3, X17,LSL #3]

    (2376) 0x4cd87c LDR	D19, [X19, X13,LSL #3]

    (2376) 0x4cd880 STR	D19, [X3, X16,LSL #3]

    (2376) 0x4cd884 CMP	X0, X12

    (2376) 0x4cd888 B.NE	4cd804

  (2375) 0x4cd88c ADD	X6, X0, X6

  (2375) 0x4cd890 SUB	X6, X6, X14

  (2375) 0x4cd894 ADD	X5, X5, #8

  (2375) 0x4cd898 CMP	X5, X10

  (2375) 0x4cd89c B.NE	4cd730

(2366) 0x4cd8a0 ORR	X3, XZR, X25

(2366) 0x4cd8a4 MOVZ	X0, #1

(2366) 0x4cd8a8 STP	X2, X8, [SP, #200]

(2366) 0x4cd8ac STR	X9, [SP, #216]

(2366) 0x4cd8b0 STR	X11, [SP, #232]

(2366) 0x4cd8b4 BL	4e4f44

(2366) 0x4cd8b8 BL	4e574c

(2366) 0x4cd8bc LDR	X0, [SP, #200]

(2366) 0x4cd8c0 BL	5294c0

(2366) 0x4cd8c4 LDR	X11, [SP, #232]

(2366) 0x4cd8c8 LDP	X9, X10, [SP, #208]

(2366) 0x4cd8cc B	4cd0cc

(2377) 0x4cd8d0 CMP	X25, #16

(2377) 0x4cd8d4 B.NE	4cc02c

(2377) 0x4cd8d8 B	4cc144

(2366) 0x4cd8dc ORR	X0, XZR, X24

(2366) 0x4cd8e0 STR	X9, [SP, #200]

(2366) 0x4cd8e4 STR	X11, [SP, #216]

(2366) 0x4cd8e8 BL	4e6b60

(2366) 0x4cd8ec LDR	X18, [X24, #112]

(2366) 0x4cd8f0 LDP	X9, X10, [SP, #200]

(2366) 0x4cd8f4 LDR	X11, [SP, #216]

(2366) 0x4cd8f8 B	4cd6e0

(2377) 0x4cd8fc CMP	X25, #16

(2377) 0x4cd900 B.NE	4cc02c

(2377) 0x4cd904 B	4cc178

(2377) 0x4cd908 CMP	X25, #16

(2377) 0x4cd90c B.NE	4cc02c

(2377) 0x4cd910 B	4cc1ac

0x4cd914 LDR	X21, [SP, #184]

0x4cd918 ADD	X25, X22, #8

0x4cd91c ADD	X9, X4, #8

0x4cd920 FNEG	D11, D0

0x4cd924 SUB	X10, X19, X25

0x4cd928 MOVZ	X20, #0

0x4cd92c SUB	X11, X19, X9

0x4cd930 ORR	X27, XZR, X20

0x4cd934 STP	X24, X28, [SP, #192]

0x4cd938 ORR	X25, XZR, X3

0x4cd93c ORR	X24, XZR, X10

0x4cd940 ORR	X28, XZR, X11

0x4cd944 STP	D9, D10, [SP, #112]

(2339) 0x4cd948 LDR	X18, [X21, #56]

(2339) 0x4cd94c ORR	X1, XZR, X23

(2339) 0x4cd950 LDR	X0, [SP, #192]

(2339) 0x4cd954 LDR	X20, [X18, #16]

(2339) 0x4cd958 BL	4ff940

(2339) 0x4cd95c LDR	X1, [SP, #200]

(2339) 0x4cd960 FMOV	D1, D12

(2339) 0x4cd964 FMOV	D0, D11

(2339) 0x4cd968 ORR	X2, XZR, X23

(2339) 0x4cd96c ORR	X0, XZR, X21

(2339) 0x4cd970 BL	4fdc20

(2339) 0x4cd974 CMP	X20, #0

(2339) 0x4cd978 B.LE	4cd9c8

(2339) 0x4cd97c CNTB	X4, ALL

(2339) 0x4cd980 CMP	X24, X28

(2339) 0x4cd984 CSEL	X12, X24, X28, #9

(2339) 0x4cd988 SUB	X17, X4, #16

(2339) 0x4cd98c CMP	X12, X17

(2339) 0x4cd990 B.LS	4cd9e4

(2339) 0x4cd994 MOVZ	X8, #0

(2339) 0x4cd998 CNTD	X30, ALL

(2339) 0x4cd99c WHILELO	P7.D, XZR, X20

(2339) 0x4cd9a0 PTRUE	P0.B, ALL

  (2341) 0x4cd9a4 LD1D	{Z9.D}, P7/Z, [X22, X8,LSL #3]

  (2341) 0x4cd9a8 LD1D	{Z5.D}, P7/Z, [X26, X8,LSL #3]

  (2341) 0x4cd9ac LD1D	{Z10.D}, P7/Z, [X19, X8,LSL #3]

  (2341) 0x4cd9b0 FDIVR	Z5.D, P0/M, Z5.D, Z9.D

  (2341) 0x4cd9b4 FADD	Z7.D, Z5.D, Z10.D

  (2341) 0x4cd9b8 ST1D	{Z7.D}, P7, [X19, X8,LSL #3]

  (2341) 0x4cd9bc ADD	X8, X8, X30

  (2341) 0x4cd9c0 WHILELO	P7.D, X8, X20

  (2341) 0x4cd9c4 B.NE	4cd9a4

(2339) 0x4cd9c8 ADD	X27, X27, #1

(2339) 0x4cd9cc CMP	X25, X27

(2339) 0x4cd9d0 B.NE	4cd948

0x4cd9d4 LDP	D9, D10, [SP, #112]

0x4cd9d8 LDP	X25, X26, [SP, #80]

0x4cd9dc LDP	D11, D12, [SP, #128]

0x4cd9e0 B	4cc07c

(2339) 0x4cd9e4 ANDS	X13, X20, #0x7

(2339) 0x4cd9e8 MOVZ	X14, #0

(2339) 0x4cd9ec B.EQ	4cdaec

(2339) 0x4cd9f0 CMP	X13, #1

(2339) 0x4cd9f4 B.EQ	4cdac8

(2339) 0x4cd9f8 CMP	X13, #2

(2339) 0x4cd9fc B.EQ	4cdaac

(2339) 0x4cda00 CMP	X13, #3

(2339) 0x4cda04 B.EQ	4cda90

(2339) 0x4cda08 CMP	X13, #4

(2339) 0x4cda0c B.EQ	4cda74

(2339) 0x4cda10 CMP	X13, #5

(2339) 0x4cda14 B.EQ	4cda58

(2339) 0x4cda18 CMP	X13, #6

(2339) 0x4cda1c B.EQ	4cda3c

(2339) 0x4cda20 LDR	D4, [X22]

(2339) 0x4cda24 MOVZ	X14, #1

(2339) 0x4cda28 LDR	D16, [X26]

(2339) 0x4cda2c LDR	D17, [X19]

(2339) 0x4cda30 FDIV	D18, D4, D16

(2339) 0x4cda34 FADD	D19, D17, D18

(2339) 0x4cda38 STR	D19, [X19]

(2339) 0x4cda3c LDR	D31, [X26, X14,LSL #3]

(2339) 0x4cda40 LDR	D22, [X22, X14,LSL #3]

(2339) 0x4cda44 LDR	D20, [X19, X14,LSL #3]

(2339) 0x4cda48 FDIV	D29, D22, D31

(2339) 0x4cda4c FADD	D24, D20, D29

(2339) 0x4cda50 STR	D24, [X19, X14,LSL #3]

(2339) 0x4cda54 ADD	X14, X14, #1

(2339) 0x4cda58 LDR	D25, [X26, X14,LSL #3]

(2339) 0x4cda5c LDR	D26, [X22, X14,LSL #3]

(2339) 0x4cda60 LDR	D23, [X19, X14,LSL #3]

(2339) 0x4cda64 FDIV	D28, D26, D25

(2339) 0x4cda68 FADD	D27, D23, D28

(2339) 0x4cda6c STR	D27, [X19, X14,LSL #3]

(2339) 0x4cda70 ADD	X14, X14, #1

(2339) 0x4cda74 LDR	D0, [X26, X14,LSL #3]

(2339) 0x4cda78 LDR	D30, [X22, X14,LSL #3]

(2339) 0x4cda7c LDR	D21, [X19, X14,LSL #3]

(2339) 0x4cda80 FDIV	D2, D30, D0

(2339) 0x4cda84 FADD	D1, D21, D2

(2339) 0x4cda88 STR	D1, [X19, X14,LSL #3]

(2339) 0x4cda8c ADD	X14, X14, #1

(2339) 0x4cda90 LDR	D3, [X26, X14,LSL #3]

(2339) 0x4cda94 LDR	D6, [X22, X14,LSL #3]

(2339) 0x4cda98 LDR	D9, [X19, X14,LSL #3]

(2339) 0x4cda9c FDIV	D5, D6, D3

(2339) 0x4cdaa0 FADD	D10, D9, D5

(2339) 0x4cdaa4 STR	D10, [X19, X14,LSL #3]

(2339) 0x4cdaa8 ADD	X14, X14, #1

(2339) 0x4cdaac LDR	D7, [X26, X14,LSL #3]

(2339) 0x4cdab0 LDR	D17, [X22, X14,LSL #3]

(2339) 0x4cdab4 LDR	D4, [X19, X14,LSL #3]

(2339) 0x4cdab8 FDIV	D16, D17, D7

(2339) 0x4cdabc FADD	D18, D4, D16

(2339) 0x4cdac0 STR	D18, [X19, X14,LSL #3]

(2339) 0x4cdac4 ADD	X14, X14, #1

(2339) 0x4cdac8 LDR	D19, [X26, X14,LSL #3]

(2339) 0x4cdacc LDR	D31, [X22, X14,LSL #3]

(2339) 0x4cdad0 LDR	D22, [X19, X14,LSL #3]

(2339) 0x4cdad4 FDIV	D20, D31, D19

(2339) 0x4cdad8 FADD	D29, D22, D20

(2339) 0x4cdadc STR	D29, [X19, X14,LSL #3]

(2339) 0x4cdae0 ADD	X14, X14, #1

(2339) 0x4cdae4 CMP	X20, X14

(2339) 0x4cdae8 B.EQ	4cd9c8

  (2340) 0x4cdaec LDR	D24, [X26, X14,LSL #3]

  (2340) 0x4cdaf0 ADD	X3, X14, #1

  (2340) 0x4cdaf4 ADD	X15, X14, #2

  (2340) 0x4cdaf8 ADD	X16, X14, #3

  (2340) 0x4cdafc ADD	X7, X14, #4

  (2340) 0x4cdb00 LDR	D25, [X22, X14,LSL #3]

  (2340) 0x4cdb04 ADD	X6, X14, #5

  (2340) 0x4cdb08 ADD	X5, X14, #6

  (2340) 0x4cdb0c ADD	X1, X14, #7

  (2340) 0x4cdb10 LDR	D26, [X19, X14,LSL #3]

  (2340) 0x4cdb14 FDIV	D23, D25, D24

  (2340) 0x4cdb18 FADD	D28, D26, D23

  (2340) 0x4cdb1c STR	D28, [X19, X14,LSL #3]

  (2340) 0x4cdb20 ADD	X14, X14, #8

  (2340) 0x4cdb24 LDR	D27, [X26, X3,LSL #3]

  (2340) 0x4cdb28 LDR	D0, [X22, X3,LSL #3]

  (2340) 0x4cdb2c LDR	D30, [X19, X3,LSL #3]

  (2340) 0x4cdb30 FDIV	D21, D0, D27

  (2340) 0x4cdb34 FADD	D2, D30, D21

  (2340) 0x4cdb38 STR	D2, [X19, X3,LSL #3]

  (2340) 0x4cdb3c LDR	D1, [X26, X15,LSL #3]

  (2340) 0x4cdb40 LDR	D3, [X22, X15,LSL #3]

  (2340) 0x4cdb44 LDR	D6, [X19, X15,LSL #3]

  (2340) 0x4cdb48 FDIV	D9, D3, D1

  (2340) 0x4cdb4c FADD	D5, D6, D9

  (2340) 0x4cdb50 STR	D5, [X19, X15,LSL #3]

  (2340) 0x4cdb54 LDR	D10, [X26, X16,LSL #3]

  (2340) 0x4cdb58 LDR	D7, [X22, X16,LSL #3]

  (2340) 0x4cdb5c LDR	D17, [X19, X16,LSL #3]

  (2340) 0x4cdb60 FDIV	D4, D7, D10

  (2340) 0x4cdb64 FADD	D16, D17, D4

  (2340) 0x4cdb68 STR	D16, [X19, X16,LSL #3]

  (2340) 0x4cdb6c LDR	D19, [X26, X7,LSL #3]

  (2340) 0x4cdb70 LDR	D18, [X22, X7,LSL #3]

  (2340) 0x4cdb74 LDR	D31, [X19, X7,LSL #3]

  (2340) 0x4cdb78 FDIV	D22, D18, D19

  (2340) 0x4cdb7c FADD	D20, D31, D22

  (2340) 0x4cdb80 STR	D20, [X19, X7,LSL #3]

  (2340) 0x4cdb84 LDR	D29, [X26, X6,LSL #3]

  (2340) 0x4cdb88 LDR	D24, [X22, X6,LSL #3]

  (2340) 0x4cdb8c LDR	D25, [X19, X6,LSL #3]

  (2340) 0x4cdb90 FDIV	D26, D24, D29

  (2340) 0x4cdb94 FADD	D23, D25, D26

  (2340) 0x4cdb98 STR	D23, [X19, X6,LSL #3]

  (2340) 0x4cdb9c LDR	D28, [X26, X5,LSL #3]

  (2340) 0x4cdba0 LDR	D27, [X22, X5,LSL #3]

  (2340) 0x4cdba4 LDR	D0, [X19, X5,LSL #3]

  (2340) 0x4cdba8 FDIV	D30, D27, D28

  (2340) 0x4cdbac FADD	D21, D0, D30

  (2340) 0x4cdbb0 STR	D21, [X19, X5,LSL #3]

  (2340) 0x4cdbb4 LDR	D2, [X26, X1,LSL #3]

  (2340) 0x4cdbb8 LDR	D1, [X22, X1,LSL #3]

  (2340) 0x4cdbbc LDR	D3, [X19, X1,LSL #3]

  (2340) 0x4cdbc0 FDIV	D6, D1, D2

  (2340) 0x4cdbc4 FADD	D9, D3, D6

  (2340) 0x4cdbc8 STR	D9, [X19, X1,LSL #3]

  (2340) 0x4cdbcc CMP	X20, X14

  (2340) 0x4cdbd0 B.NE	4cdaec

(2339) 0x4cdbd4 B	4cd9c8

0x4cdbd8 HINT	#0

0x4cdbdc HINT	#0

Coverage (%)	Name	Source Location	Module
►95.73+	hypre_BoomerAMGCycle	par_cycle.c:394	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec
►4.27+	hypre_BoomerAMGCycle	par_cycle.c:394	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:424	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	ams.c:63-331
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:63-182,188-316,326-331.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.50 to 7.00 cycles (2.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 34% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 18.50 to 6.73 cycles (2.75x speedup).

Details

18% of VPU instructions are used in vector version (process two or more data elements in vector registers):

41% of VPU loads are used in vector version.
23% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

1: addition or subtraction
2: multiply

The binary function is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 1.00 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	110
loop length	460
used w registers	2
used x registers	25
used b registers	0
used h registers	0
used s registers	2
used d registers	14
used q registers	0
used v registers	0
used z registers	0
nb stack references	48
ADD-SUB / MUL ratio	0.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.75 cycles
front end	13.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	8.50	8.50	8.50	8.50	4.50	4.50	4.50	4.50	18.50	18.17	18.33	7.50	7.50
cycles	4.50	4.50	8.50	8.50	8.50	8.50	4.50	4.50	4.50	4.50	18.50	18.17	18.33	7.50	7.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.75
Dispatch	18.50
Overall L1	18.50

Vectorization ratios

INT

all	21%
load	41%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	18%
load	41%
store	23%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	35%
load	41%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	24%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	34%
load	41%
store	42%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.50 cycles. At this rate:

0% of peak store performance is reached (0.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4cbf28

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X28, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X7, [X1, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X6, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X23, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X19, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4cc07c <hypre_ParCSRRelax+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X0, X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X2, X0, #0x1fffffffc	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X26, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D11, D12, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV D12, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4cd914 <hypre_ParCSRRelax+0x19ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D13, D14, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV D11, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CBZ X2, 4cc394 <hypre_ParCSRRelax+0x46c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D14, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D13, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D15, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
FMOV D15, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP X19, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X27, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X25, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR D15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X25, X26, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D11, D12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADRP X22, <57107c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X0, [X22, #3856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X21, X22, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X26, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4cc06c <hypre_ParCSRRelax+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D20, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP D9, D10, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FMUL D9, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR X25, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X20, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP X27, X4, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
FSUB D22, D20, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR XZR, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X3, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
FMUL D14, D22, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCCMP D1, D20, #0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CSINC W24, WZR, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W24, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP D9, D10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X25, X26, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D11, D12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
B 4cc07c <hypre_ParCSRRelax+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4cc58c <hypre_ParCSRRelax+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X27, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X5, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X22, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP X24, X19, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP D9, D10, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X26, X5, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR D15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X25, X26, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D9, D10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
B 4cc07c <hypre_ParCSRRelax+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X25, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FNEG D11, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X10, X19, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X11, X19, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X27, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X24, X28, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X24, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X28, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D9, D10, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP D9, D10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X25, X26, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D11, D12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
B 4cc07c <hypre_ParCSRRelax+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	ams.c:63-331
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:63-182,188-316,326-331.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.50 to 7.00 cycles (2.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

18% of VPU instructions are used in vector version (process two or more data elements in vector registers):

41% of VPU loads are used in vector version.
23% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

1: addition or subtraction
2: multiply

The binary function is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 1.00 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	110
loop length	460
used w registers	2
used x registers	25
used b registers	0
used h registers	0
used s registers	2
used d registers	14
used q registers	0
used v registers	0
used z registers	0
nb stack references	48
ADD-SUB / MUL ratio	0.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.75 cycles
front end	13.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	8.50	8.50	8.50	8.50	4.50	4.50	4.50	4.50	18.50	18.17	18.33	7.50	7.50
cycles	4.50	4.50	8.50	8.50	8.50	8.50	4.50	4.50	4.50	4.50	18.50	18.17	18.33	7.50	7.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.75
Dispatch	18.50
Overall L1	18.50

Vectorization ratios

INT

all	21%
load	41%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	18%
load	41%
store	23%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	35%
load	41%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	24%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	34%
load	41%
store	42%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.50 cycles. At this rate:

0% of peak store performance is reached (0.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4cbf28

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X28, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X7, [X1, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X6, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X23, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X19, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4cc07c <hypre_ParCSRRelax+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X0, X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X2, X0, #0x1fffffffc	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X26, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D11, D12, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV D12, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4cd914 <hypre_ParCSRRelax+0x19ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D13, D14, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV D11, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CBZ X2, 4cc394 <hypre_ParCSRRelax+0x46c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D14, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D13, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D15, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
FMOV D15, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP X19, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X27, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X25, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR D15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X25, X26, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D11, D12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADRP X22, <57107c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X0, [X22, #3856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X21, X22, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X26, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4cc06c <hypre_ParCSRRelax+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D20, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP D9, D10, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FMUL D9, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR X25, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X20, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP X27, X4, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
FSUB D22, D20, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR XZR, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X3, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
FMUL D14, D22, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCCMP D1, D20, #0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CSINC W24, WZR, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W24, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP D9, D10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X25, X26, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D11, D12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
B 4cc07c <hypre_ParCSRRelax+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4cc58c <hypre_ParCSRRelax+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X27, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X5, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X22, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP X24, X19, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP D9, D10, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X26, X5, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR D15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X25, X26, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D9, D10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
B 4cc07c <hypre_ParCSRRelax+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X25, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FNEG D11, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X10, X19, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X11, X19, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X27, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X24, X28, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X24, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X28, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP D9, D10, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP D9, D10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X25, X26, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D11, D12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
B 4cc07c <hypre_ParCSRRelax+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	5.9699997901917	1.7249381542206
1x2
1x4
1x8
1x16
1x24
1x32
1x40
1x48
1x56
1x64

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelax–	1.72	5.97
▼Loop 2366 - ams.c:70-310 - exec–	0.00	0.00
▼Loop 2375 - ams.c:270-274 - exec–	0.00	0.00
○Loop 2376 - ams.c:273-274 - exec	0.00	0.00
▼Loop 2367 - ams.c:70-293 - exec–	0.00	0.00
○Loop 2372 - ams.c:292-293 - exec	0.00	0.00
○Loop 2373 - ams.c:289-290 - exec	0.00	0.00
○Loop 2374 - ams.c:286-287 - exec	0.00	0.00
▼Loop 2368 - ams.c:292-307 - exec–	0.00	0.00
○Loop 2371 - ams.c:300-301 - exec	0.00	0.00
○Loop 2370 - ams.c:303-304 - exec	0.00	0.00
○Loop 2369 - ams.c:306-307 - exec	0.00	0.00
▼Loop 2339 - ams.c:70-79 - exec–	0.00	0.00
○Loop 2341 - ams.c:78-79 - exec	1.72	5.97
○Loop 2340 - ams.c:78-79 - exec	0.00	0.00
○Loop 2377 - ams.c:70-326 - exec	0.00	0.00
▼Loop 2342 - ams.c:70-226 - exec–	0.00	0.00
▼Loop 2343 - ams.c:192-206 - exec–	0.00	0.00
○Loop 2351 - ams.c:197-201 - exec	0.00	0.00
○Loop 2350 - ams.c:197-201 - exec	0.00	0.00
○Loop 2349 - ams.c:204-205 - exec	0.00	0.00
▼Loop 2359 - ams.c:149-157 - exec–	0.00	0.00
○Loop 2361 - ams.c:152-153 - exec	0.00	0.00
○Loop 2360 - ams.c:155-156 - exec	0.00	0.00
▼Loop 2352 - ams.c:163-171 - exec–	0.00	0.00
○Loop 2357 - ams.c:166-167 - exec	0.00	0.00
○Loop 2356 - ams.c:169-170 - exec	0.00	0.00
▼Loop 2353 - ams.c:174-182 - exec–	0.00	0.00
○Loop 2355 - ams.c:177-178 - exec	0.00	0.00
○Loop 2354 - ams.c:180-181 - exec	0.00	0.00
▼Loop 2358 - ams.c:138-146 - exec–	0.00	0.00
○Loop 2363 - ams.c:141-142 - exec	0.00	0.00
○Loop 2362 - ams.c:144-145 - exec	0.00	0.00
▼Loop 2364 - ams.c:123-127 - exec–	0.00	0.00
○Loop 2365 - ams.c:126-127 - exec	0.00	0.00
○Loop 2348 - ams.c:213-219 - exec	0.00	0.00
▼Loop 2344 - ams.c:209-222 - exec–	0.00	0.00
○Loop 2345 - ams.c:220-221 - exec	0.00	0.00
○Loop 2346 - ams.c:213-217 - exec	0.00	0.00
○Loop 2347 - ams.c:213-217 - exec	0.00	0.00
○Loop 2378 - ams.c:70-316 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency