| Function: hypre_ParCSRComputeL1Norms | Module: exec | Source: ams.c:547-738 [...] | Coverage (incl. loops): 0.40% | (excl. loops): 0.01% |
|---|
| Function: hypre_ParCSRComputeL1Norms | Module: exec | Source: ams.c:547-738 [...] | Coverage (incl. loops): 0.40% | (excl. loops): 0.01% |
|---|
/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 547 - 738 |
-------------------------------------------------------------------------------- |
547: { |
548: HYPRE_Int i, j; |
549: HYPRE_Int num_rows = hypre_ParCSRMatrixNumRows(A); |
550: |
551: hypre_CSRMatrix *A_diag = hypre_ParCSRMatrixDiag(A); |
552: HYPRE_Int *A_diag_I = hypre_CSRMatrixI(A_diag); |
553: HYPRE_Int *A_diag_J = hypre_CSRMatrixJ(A_diag); |
554: HYPRE_Real *A_diag_data = hypre_CSRMatrixData(A_diag); |
555: |
556: hypre_CSRMatrix *A_offd = hypre_ParCSRMatrixOffd(A); |
557: HYPRE_Int *A_offd_I = hypre_CSRMatrixI(A_offd); |
558: HYPRE_Int *A_offd_J = hypre_CSRMatrixJ(A_offd); |
559: HYPRE_Real *A_offd_data = hypre_CSRMatrixData(A_offd); |
560: HYPRE_Int num_cols_offd = hypre_CSRMatrixNumCols(A_offd); |
561: |
562: HYPRE_Real diag; |
563: HYPRE_Real *l1_norm = hypre_TAlloc(HYPRE_Real, num_rows); |
564: |
565: HYPRE_Int *cf_marker_offd = NULL; |
566: HYPRE_Int cf_diag; |
567: |
568: /* collect the cf marker data from other procs */ |
569: if (cf_marker != NULL) |
570: { |
571: HYPRE_Int index; |
572: HYPRE_Int num_sends; |
573: HYPRE_Int start; |
574: HYPRE_Int *int_buf_data = NULL; |
575: |
576: hypre_ParCSRCommPkg *comm_pkg = hypre_ParCSRMatrixCommPkg(A); |
577: hypre_ParCSRCommHandle *comm_handle; |
578: |
579: if (num_cols_offd) |
580: cf_marker_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
581: num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg); |
582: if (hypre_ParCSRCommPkgSendMapStart(comm_pkg, num_sends)) |
583: int_buf_data = hypre_CTAlloc(HYPRE_Int, |
584: hypre_ParCSRCommPkgSendMapStart(comm_pkg, num_sends)); |
585: index = 0; |
586: for (i = 0; i < num_sends; i++) |
587: { |
588: start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i); |
589: for (j = start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++) |
590: { |
591: int_buf_data[index++] = cf_marker[hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j)]; |
592: } |
593: } |
594: comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data, |
595: cf_marker_offd); |
596: hypre_ParCSRCommHandleDestroy(comm_handle); |
597: hypre_TFree(int_buf_data); |
598: } |
599: |
600: if (option == 1) |
601: { |
602: for (i = 0; i < num_rows; i++) |
603: { |
604: l1_norm[i] = 0.0; |
605: if (cf_marker == NULL) |
606: { |
607: /* Add the l1 norm of the diag part of the ith row */ |
608: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
609: l1_norm[i] += fabs(A_diag_data[j]); |
610: /* Add the l1 norm of the offd part of the ith row */ |
611: if (num_cols_offd) |
612: { |
613: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
614: l1_norm[i] += fabs(A_offd_data[j]); |
615: } |
616: } |
617: else |
618: { |
619: cf_diag = cf_marker[i]; |
620: /* Add the CF l1 norm of the diag part of the ith row */ |
621: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
622: if (cf_diag == cf_marker[A_diag_J[j]]) |
623: l1_norm[i] += fabs(A_diag_data[j]); |
624: /* Add the CF l1 norm of the offd part of the ith row */ |
625: if (num_cols_offd) |
626: { |
627: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
628: if (cf_diag == cf_marker_offd[A_offd_J[j]]) |
629: l1_norm[i] += fabs(A_offd_data[j]); |
630: } |
631: } |
632: } |
633: } |
634: else if (option == 2) |
635: { |
636: for (i = 0; i < num_rows; i++) |
637: { |
638: /* Add the diag element of the ith row */ |
639: l1_norm[i] = fabs(A_diag_data[A_diag_I[i]]); |
640: if (cf_marker == NULL) |
641: { |
642: /* Add the l1 norm of the offd part of the ith row */ |
643: if (num_cols_offd) |
644: { |
645: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
646: l1_norm[i] += fabs(A_offd_data[j]); |
647: } |
648: } |
649: else |
650: { |
651: cf_diag = cf_marker[i]; |
652: /* Add the CF l1 norm of the offd part of the ith row */ |
653: if (num_cols_offd) |
654: { |
655: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
656: if (cf_diag == cf_marker_offd[A_offd_J[j]]) |
657: l1_norm[i] += fabs(A_offd_data[j]); |
658: } |
659: } |
660: } |
661: } |
662: else if (option == 3) |
663: { |
664: for (i = 0; i < num_rows; i++) |
665: { |
666: l1_norm[i] = 0.0; |
667: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
668: l1_norm[i] += A_diag_data[j] * A_diag_data[j]; |
669: if (num_cols_offd) |
670: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
671: l1_norm[i] += A_offd_data[j] * A_offd_data[j]; |
672: } |
673: } |
674: else if (option == 4) |
675: { |
676: for (i = 0; i < num_rows; i++) |
677: { |
678: /* Add the diag element of the ith row */ |
679: diag = l1_norm[i] = fabs(A_diag_data[A_diag_I[i]]); |
680: if (cf_marker == NULL) |
681: { |
682: /* Add the scaled l1 norm of the offd part of the ith row */ |
683: if (num_cols_offd) |
684: { |
685: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
686: l1_norm[i] += 0.5*fabs(A_offd_data[j]); |
687: } |
688: } |
689: else |
690: { |
691: cf_diag = cf_marker[i]; |
692: /* Add the scaled CF l1 norm of the offd part of the ith row */ |
693: if (num_cols_offd) |
694: { |
695: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
696: if (cf_diag == cf_marker_offd[A_offd_J[j]]) |
697: l1_norm[i] += 0.5*fabs(A_offd_data[j]); |
698: } |
699: } |
700: |
701: /* Truncate according to Remark 6.2 */ |
702: if (l1_norm[i] <= 4.0/3.0*diag) |
703: l1_norm[i] = diag; |
704: } |
705: } |
706: else if (option == 5) /*stores diagonal of A for Jacobi using matvec, rlx 7 */ |
707: { |
708: for (i = 0; i < num_rows; i++) |
709: { |
710: diag = A_diag_data[A_diag_I[i]]; |
711: if (diag != 0.0) l1_norm[i] = diag; |
[...] |
720: for (i = 0; i < num_rows; i++) |
721: if (A_diag_data[A_diag_I[i]] < 0) |
722: l1_norm[i] = -l1_norm[i]; |
723: |
724: for (i = 0; i < num_rows; i++) |
725: /* if (fabs(l1_norm[i]) < DBL_EPSILON) */ |
726: if (fabs(l1_norm[i]) == 0.0) |
727: { |
728: hypre_error_in_arg(1); |
729: break; |
730: } |
731: |
732: //for (i = 0; i < num_rows; i++) l1_norm[i]=1.0/l1_norm[i]; |
733: hypre_TFree(cf_marker_offd); |
734: |
735: *l1_norm_ptr = l1_norm; |
736: |
737: return hypre_error_flag; |
738: } |
0x4ce530 STP X29, X30, [SP, #880]! |
0x4ce534 ADD X29, SP, #0 |
0x4ce538 STP X19, X20, [SP, #16] |
0x4ce53c STP X21, X22, [SP, #32] |
0x4ce540 ORR X22, XZR, X2 |
0x4ce544 STP X23, X24, [SP, #48] |
0x4ce548 STP X25, X26, [SP, #64] |
0x4ce54c STP X27, X28, [SP, #80] |
0x4ce550 MOVZ X28, #0 |
0x4ce554 LDR X5, [X0, #56] |
0x4ce558 LDR X27, [X5, #16] |
0x4ce55c LDP X26, X25, [X5] |
0x4ce560 STR X1, [SP, #96] |
0x4ce564 LDR X24, [X5, #48] |
0x4ce568 STP X3, X0, [SP, #112] |
0x4ce56c LDR X1, [X0, #64] |
0x4ce570 LDP X0, X20, [X1] |
0x4ce574 LDR X19, [X1, #24] |
0x4ce578 STR X0, [SP, #104] |
0x4ce57c UBFM X0, X27, #61, #60 |
0x4ce580 LDR X21, [X1, #48] |
0x4ce584 BL 5293e8 |
0x4ce588 ORR X23, XZR, X0 |
0x4ce58c CBZ X22, 4ce644 |
0x4ce590 LDR X4, [SP, #120] |
0x4ce594 LDR X10, [X4, #112] |
0x4ce598 CBNZ X19, 4ce9f4 |
0x4ce59c MOVZ X2, #0 |
0x4ce5a0 LDR X3, [X10, #8] |
0x4ce5a4 LDR X6, [X10, #24] |
0x4ce5a8 UBFM X12, X3, #61, #60 |
0x4ce5ac LDR X0, [X6, X12] |
0x4ce5b0 CBNZ X0, 4ce9d4 |
0x4ce5b4 CMP X3, #0 |
0x4ce5b8 B.LE 4ce624 |
0x4ce5bc LDR X7, [X10, #24] |
0x4ce5c0 MOVZ X3, #0 |
0x4ce5c4 ADD X1, X7, #8 |
0x4ce5c8 ADD X8, X1, X12 |
(2407) 0x4ce5cc LDP X0, X9, [X1, #1016] |
(2407) 0x4ce5d0 CMP X0, X9 |
(2407) 0x4ce5d4 B.GE 4ce618 |
(2407) 0x4ce5d8 SUB X14, XZR, X0,LSL #3 |
(2407) 0x4ce5dc LDR X17, [X10, #32] |
(2407) 0x4ce5e0 ORR X13, XZR, X0 |
(2407) 0x4ce5e4 ADD X15, X14, X3,LSL #3 |
(2407) 0x4ce5e8 ADD X16, X2, X15 |
(2408) 0x4ce5ec LDR X18, [X17, X0,LSL #3] |
(2408) 0x4ce5f0 ORR X30, XZR, X0 |
(2408) 0x4ce5f4 LDR X5, [X22, X18,LSL #3] |
(2408) 0x4ce5f8 STR X5, [X16, X0,LSL #3] |
(2408) 0x4ce5fc ADD X0, X0, #1 |
(2408) 0x4ce600 LDR X4, [X1] |
(2408) 0x4ce604 CMP X4, X0 |
(2408) 0x4ce608 B.GT 4ce5ec |
(2407) 0x4ce60c ADD X11, X3, #1 |
(2407) 0x4ce610 SUB X6, X30, X13 |
(2407) 0x4ce614 ADD X3, X11, X6 |
(2407) 0x4ce618 ADD X1, X1, #8 |
(2407) 0x4ce61c CMP X8, X1 |
(2407) 0x4ce620 B.NE 4ce5cc |
0x4ce624 ORR X1, XZR, X10 |
0x4ce628 ORR X3, XZR, X28 |
0x4ce62c STR X2, [SP, #120] |
0x4ce630 MOVZ X0, #11 |
0x4ce634 BL 4e4f44 |
0x4ce638 BL 4e574c |
0x4ce63c LDR X0, [SP, #120] |
0x4ce640 BL 5294c0 |
0x4ce644 LDR X2, [SP, #96] |
0x4ce648 CMP X2, #1 |
0x4ce64c B.EQ 4cebe4 |
0x4ce650 CMP X2, #2 |
0x4ce654 B.EQ 4cea28 |
0x4ce658 CMP X2, #3 |
0x4ce65c B.EQ 4cf8a4 |
0x4ce660 CMP X2, #4 |
0x4ce664 B.EQ 4cf198 |
0x4ce668 CMP X2, #5 |
0x4ce66c B.EQ 4cffb0 |
0x4ce670 CMP X27, #0 |
0x4ce674 B.LE 4ce9a0 |
0x4ce678 HINT #0 |
0x4ce67c HINT #0 |
0x4ce680 ANDS X12, X27, #0x7 |
0x4ce684 MOVZ X8, #0 |
0x4ce688 B.EQ 4ce75c |
0x4ce68c CMP X12, #1 |
0x4ce690 B.EQ 4ce734 |
0x4ce694 CMP X12, #2 |
0x4ce698 B.EQ 4ce720 |
0x4ce69c CMP X12, #3 |
0x4ce6a0 B.EQ 4ce70c |
0x4ce6a4 CMP X12, #4 |
0x4ce6a8 B.EQ 4ce6f8 |
0x4ce6ac CMP X12, #5 |
0x4ce6b0 B.EQ 4ce6e4 |
0x4ce6b4 CMP X12, #6 |
0x4ce6b8 B.EQ 4ce6d0 |
0x4ce6bc LDR X7, [X26] |
0x4ce6c0 LDR D28, [X24, X7,LSL #3] |
0x4ce6c4 FCMPE D28, #0 |
0x4ce6c8 B.MI 4cfe94 |
0x4ce6cc MOVZ X8, #1 |
0x4ce6d0 LDR X9, [X26, X8,LSL #3] |
0x4ce6d4 LDR D0, [X24, X9,LSL #3] |
0x4ce6d8 FCMPE D0, #0 |
0x4ce6dc B.MI 4cf394 |
0x4ce6e0 ADD X8, X8, #1 |
0x4ce6e4 LDR X14, [X26, X8,LSL #3] |
0x4ce6e8 LDR D21, [X24, X14,LSL #3] |
0x4ce6ec FCMPE D21, #0 |
0x4ce6f0 B.MI 4cf170 |
0x4ce6f4 ADD X8, X8, #1 |
0x4ce6f8 LDR X15, [X26, X8,LSL #3] |
0x4ce6fc LDR D25, [X24, X15,LSL #3] |
0x4ce700 FCMPE D25, #0 |
0x4ce704 B.MI 4cf148 |
0x4ce708 ADD X8, X8, #1 |
0x4ce70c LDR X16, [X26, X8,LSL #3] |
0x4ce710 LDR D2, [X24, X16,LSL #3] |
0x4ce714 FCMPE D2, #0 |
0x4ce718 B.MI 4ceed8 |
0x4ce71c ADD X8, X8, #1 |
0x4ce720 LDR X17, [X26, X8,LSL #3] |
0x4ce724 LDR D4, [X24, X17,LSL #3] |
0x4ce728 FCMPE D4, #0 |
0x4ce72c B.MI 4ceec8 |
0x4ce730 ADD X8, X8, #1 |
0x4ce734 LDR X30, [X26, X8,LSL #3] |
0x4ce738 LDR D6, [X24, X30,LSL #3] |
0x4ce73c FCMPE D6, #0 |
0x4ce740 B.GE 4ce750 |
0x4ce744 LDR D19, [X23, X8,LSL #3] |
0x4ce748 FNEG D16, D19 |
0x4ce74c STR D16, [X23, X8,LSL #3] |
0x4ce750 ADD X8, X8, #1 |
0x4ce754 CMP X27, X8 |
0x4ce758 B.EQ 4ce864 |
(2387) 0x4ce75c LDR X13, [X26, X8,LSL #3] |
(2387) 0x4ce760 LDR D31, [X24, X13,LSL #3] |
(2387) 0x4ce764 FCMPE D31, #0 |
(2387) 0x4ce768 B.GE 4ce778 |
(2387) 0x4ce76c LDR D26, [X23, X8,LSL #3] |
(2387) 0x4ce770 FNEG D27, D26 |
(2387) 0x4ce774 STR D27, [X23, X8,LSL #3] |
(2387) 0x4ce778 ADD X6, X8, #1 |
(2387) 0x4ce77c LDR X19, [X26, X6,LSL #3] |
(2387) 0x4ce780 LDR D28, [X24, X19,LSL #3] |
(2387) 0x4ce784 FCMPE D28, #0 |
(2387) 0x4ce788 B.GE 4ce798 |
(2387) 0x4ce78c LDR D17, [X23, X6,LSL #3] |
(2387) 0x4ce790 FNEG D18, D17 |
(2387) 0x4ce794 STR D18, [X23, X6,LSL #3] |
(2387) 0x4ce798 ADD X21, X6, #1 |
(2387) 0x4ce79c LDR X10, [X26, X21,LSL #3] |
(2387) 0x4ce7a0 LDR D0, [X24, X10,LSL #3] |
(2387) 0x4ce7a4 FCMPE D0, #0 |
(2387) 0x4ce7a8 B.GE 4ce7b8 |
(2387) 0x4ce7ac LDR D20, [X23, X21,LSL #3] |
(2387) 0x4ce7b0 FNEG D22, D20 |
(2387) 0x4ce7b4 STR D22, [X23, X21,LSL #3] |
(2387) 0x4ce7b8 ADD X4, X6, #2 |
(2387) 0x4ce7bc LDR X2, [X26, X4,LSL #3] |
(2387) 0x4ce7c0 LDR D21, [X24, X2,LSL #3] |
(2387) 0x4ce7c4 FCMPE D21, #0 |
(2387) 0x4ce7c8 B.GE 4ce7d8 |
(2387) 0x4ce7cc LDR D23, [X23, X4,LSL #3] |
(2387) 0x4ce7d0 FNEG D24, D23 |
(2387) 0x4ce7d4 STR D24, [X23, X4,LSL #3] |
(2387) 0x4ce7d8 ADD X20, X6, #3 |
(2387) 0x4ce7dc LDR X22, [X26, X20,LSL #3] |
(2387) 0x4ce7e0 LDR D25, [X24, X22,LSL #3] |
(2387) 0x4ce7e4 FCMPE D25, #0 |
(2387) 0x4ce7e8 B.GE 4ce7f8 |
(2387) 0x4ce7ec LDR D29, [X23, X20,LSL #3] |
(2387) 0x4ce7f0 FNEG D30, D29 |
(2387) 0x4ce7f4 STR D30, [X23, X20,LSL #3] |
(2387) 0x4ce7f8 ADD X25, X6, #4 |
(2387) 0x4ce7fc LDR X5, [X26, X25,LSL #3] |
(2387) 0x4ce800 LDR D2, [X24, X5,LSL #3] |
(2387) 0x4ce804 FCMPE D2, #0 |
(2387) 0x4ce808 B.GE 4ce818 |
(2387) 0x4ce80c LDR D1, [X23, X25,LSL #3] |
(2387) 0x4ce810 FNEG D3, D1 |
(2387) 0x4ce814 STR D3, [X23, X25,LSL #3] |
(2387) 0x4ce818 ADD X1, X6, #5 |
(2387) 0x4ce81c LDR X18, [X26, X1,LSL #3] |
(2387) 0x4ce820 LDR D4, [X24, X18,LSL #3] |
(2387) 0x4ce824 FCMPE D4, #0 |
(2387) 0x4ce828 B.GE 4ce838 |
(2387) 0x4ce82c LDR D5, [X23, X1,LSL #3] |
(2387) 0x4ce830 FNEG D7, D5 |
(2387) 0x4ce834 STR D7, [X23, X1,LSL #3] |
(2387) 0x4ce838 ADD X11, X6, #6 |
(2387) 0x4ce83c LDR X0, [X26, X11,LSL #3] |
(2387) 0x4ce840 LDR D6, [X24, X0,LSL #3] |
(2387) 0x4ce844 FCMPE D6, #0 |
(2387) 0x4ce848 B.GE 4ce858 |
(2387) 0x4ce84c LDR D19, [X23, X11,LSL #3] |
(2387) 0x4ce850 FNEG D16, D19 |
(2387) 0x4ce854 STR D16, [X23, X11,LSL #3] |
(2387) 0x4ce858 ADD X8, X6, #7 |
(2387) 0x4ce85c CMP X27, X8 |
(2387) 0x4ce860 B.NE 4ce75c |
0x4ce864 ANDS X24, X27, #0x7 |
0x4ce868 MOVZ X16, #0 |
0x4ce86c B.EQ 4ce918 |
0x4ce870 CMP X24, #1 |
0x4ce874 B.EQ 4ce900 |
0x4ce878 CMP X24, #2 |
0x4ce87c B.EQ 4ce8f0 |
0x4ce880 CMP X24, #3 |
0x4ce884 B.EQ 4ce8e0 |
0x4ce888 CMP X24, #4 |
0x4ce88c B.EQ 4ce8d0 |
0x4ce890 CMP X24, #5 |
0x4ce894 B.EQ 4ce8c0 |
0x4ce898 CMP X24, #6 |
0x4ce89c B.EQ 4ce8b0 |
0x4ce8a0 LDR D31, [X23] |
0x4ce8a4 MOVZ X16, #1 |
0x4ce8a8 FCMP D31, #0 |
0x4ce8ac B.EQ 4ceee8 |
0x4ce8b0 LDR D26, [X23, X16,LSL #3] |
0x4ce8b4 ADD X16, X16, #1 |
0x4ce8b8 FCMP D26, #0 |
0x4ce8bc B.EQ 4ceee8 |
0x4ce8c0 LDR D27, [X23, X16,LSL #3] |
0x4ce8c4 ADD X16, X16, #1 |
0x4ce8c8 FCMP D27, #0 |
0x4ce8cc B.EQ 4ceee8 |
0x4ce8d0 LDR D28, [X23, X16,LSL #3] |
0x4ce8d4 ADD X16, X16, #1 |
0x4ce8d8 FCMP D28, #0 |
0x4ce8dc B.EQ 4ceee8 |
0x4ce8e0 LDR D17, [X23, X16,LSL #3] |
0x4ce8e4 ADD X16, X16, #1 |
0x4ce8e8 FCMP D17, #0 |
0x4ce8ec B.EQ 4ceee8 |
0x4ce8f0 LDR D18, [X23, X16,LSL #3] |
0x4ce8f4 ADD X16, X16, #1 |
0x4ce8f8 FCMP D18, #0 |
0x4ce8fc B.EQ 4ceee8 |
0x4ce900 LDR D0, [X23, X16,LSL #3] |
0x4ce904 FCMP D0, #0 |
0x4ce908 B.EQ 4ceee8 |
0x4ce90c ADD X16, X16, #1 |
0x4ce910 CMP X27, X16 |
0x4ce914 B.EQ 4ce9a0 |
(2388) 0x4ce918 LDR D20, [X23, X16,LSL #3] |
(2388) 0x4ce91c ADD X26, X16, #1 |
(2388) 0x4ce920 ADD X3, X16, #3 |
(2388) 0x4ce924 ADD X9, X16, #4 |
(2388) 0x4ce928 ADD X14, X16, #5 |
(2388) 0x4ce92c ADD X15, X16, #6 |
(2388) 0x4ce930 ADD X7, X16, #7 |
(2388) 0x4ce934 ADD X12, X26, #1 |
(2388) 0x4ce938 ADD X16, X16, #8 |
(2388) 0x4ce93c FCMP D20, #0 |
(2388) 0x4ce940 B.EQ 4ceee8 |
(2388) 0x4ce944 LDR D22, [X23, X26,LSL #3] |
(2388) 0x4ce948 FCMP D22, #0 |
(2388) 0x4ce94c B.EQ 4ceee8 |
(2388) 0x4ce950 LDR D21, [X23, X12,LSL #3] |
(2388) 0x4ce954 FCMP D21, #0 |
(2388) 0x4ce958 B.EQ 4ceee8 |
(2388) 0x4ce95c LDR D23, [X23, X3,LSL #3] |
(2388) 0x4ce960 FCMP D23, #0 |
(2388) 0x4ce964 B.EQ 4ceee8 |
(2388) 0x4ce968 LDR D24, [X23, X9,LSL #3] |
(2388) 0x4ce96c FCMP D24, #0 |
(2388) 0x4ce970 B.EQ 4ceee8 |
(2388) 0x4ce974 LDR D25, [X23, X14,LSL #3] |
(2388) 0x4ce978 FCMP D25, #0 |
(2388) 0x4ce97c B.EQ 4ceee8 |
(2388) 0x4ce980 LDR D29, [X23, X15,LSL #3] |
(2388) 0x4ce984 FCMP D29, #0 |
(2388) 0x4ce988 B.EQ 4ceee8 |
(2388) 0x4ce98c LDR D30, [X23, X7,LSL #3] |
(2388) 0x4ce990 FCMP D30, #0 |
(2388) 0x4ce994 B.EQ 4ceee8 |
(2388) 0x4ce998 CMP X27, X16 |
(2388) 0x4ce99c B.NE 4ce918 |
0x4ce9a0 ORR X0, XZR, X28 |
0x4ce9a4 BL 5294c0 |
0x4ce9a8 LDR X30, [SP, #112] |
0x4ce9ac ADRP X17, |
0x4ce9b0 LDR X0, [X17, #3856] |
0x4ce9b4 STR X23, [X30] |
0x4ce9b8 LDP X19, X20, [SP, #16] |
0x4ce9bc LDP X21, X22, [SP, #32] |
0x4ce9c0 LDP X23, X24, [SP, #48] |
0x4ce9c4 LDP X25, X26, [SP, #64] |
0x4ce9c8 LDP X27, X28, [SP, #80] |
0x4ce9cc LDP X29, X30, [SP], #144 |
0x4ce9d0 RET |
0x4ce9d4 MOVZ X1, #8 |
0x4ce9d8 STP X12, X10, [SP, #120] |
0x4ce9dc STR X3, [SP, #136] |
0x4ce9e0 BL 529428 |
0x4ce9e4 LDR X3, [SP, #136] |
0x4ce9e8 ORR X2, XZR, X0 |
0x4ce9ec LDP X12, X10, [SP, #120] |
0x4ce9f0 B 4ce5b4 |
0x4ce9f4 MOVZ X1, #8 |
0x4ce9f8 ORR X0, XZR, X19 |
0x4ce9fc STR X10, [SP, #120] |
0x4cea00 BL 529428 |
0x4cea04 LDR X10, [SP, #120] |
0x4cea08 ORR X28, XZR, X0 |
0x4cea0c MOVZ X2, #0 |
0x4cea10 LDR X3, [X10, #8] |
0x4cea14 LDR X6, [X10, #24] |
0x4cea18 UBFM X12, X3, #61, #60 |
0x4cea1c LDR X0, [X6, X12] |
0x4cea20 CBZ X0, 4ce5b4 |
0x4cea24 B 4ce9d4 |
0x4cea28 CMP X27, #0 |
0x4cea2c B.LE 4ce9a0 |
0x4cea30 LDR X10, [SP, #104] |
0x4cea34 MOVZ X0, #0 |
0x4cea38 ADD X18, X10, #8 |
0x4cea3c B 4cea50 |
(2395) 0x4cea40 CBNZ X19, 4cf3f0 |
(2395) 0x4cea44 ADD X0, X0, #1 |
(2395) 0x4cea48 CMP X27, X0 |
(2395) 0x4cea4c B.EQ 4ce680 |
(2395) 0x4cea50 LDR X30, [X26, X0,LSL #3] |
(2395) 0x4cea54 LDR D7, [X24, X30,LSL #3] |
(2395) 0x4cea58 FABS D31, D7 |
(2395) 0x4cea5c STR D31, [X23, X0,LSL #3] |
(2395) 0x4cea60 CBNZ X22, 4cea40 |
(2395) 0x4cea64 CBZ X19, 4cea44 |
(2395) 0x4cea68 LDR X8, [SP, #104] |
(2395) 0x4cea6c ADD X4, X8, #8 |
(2395) 0x4cea70 LDR X12, [X8, X0,LSL #3] |
(2395) 0x4cea74 LDR X7, [X4, X0,LSL #3] |
(2395) 0x4cea78 CMP X12, X7 |
(2395) 0x4cea7c B.GE 4cea44 |
(2395) 0x4cea80 ADD X9, X21, X7,LSL #3 |
(2395) 0x4cea84 UBFM X14, X12, #61, #60 |
(2395) 0x4cea88 ADD X13, X21, X12,LSL #3 |
(2395) 0x4cea8c SUB X15, X9, X13 |
(2395) 0x4cea90 SUB X16, X15, #8 |
(2395) 0x4cea94 UBFM X17, X16, #3, #63 |
(2395) 0x4cea98 ADD X10, X17, #1 |
(2395) 0x4cea9c ANDS X30, X10, #0x7 |
(2395) 0x4ceaa0 B.EQ 4ceb50 |
(2395) 0x4ceaa4 CMP X30, #1 |
(2395) 0x4ceaa8 B.EQ 4ceb38 |
(2395) 0x4ceaac CMP X30, #2 |
(2395) 0x4ceab0 B.EQ 4ceb28 |
(2395) 0x4ceab4 CMP X30, #3 |
(2395) 0x4ceab8 B.EQ 4ceb18 |
(2395) 0x4ceabc CMP X30, #4 |
(2395) 0x4ceac0 B.EQ 4ceb08 |
(2395) 0x4ceac4 CMP X30, #5 |
(2395) 0x4ceac8 B.EQ 4ceaf8 |
(2395) 0x4ceacc CMP X30, #6 |
(2395) 0x4cead0 B.EQ 4ceae8 |
(2395) 0x4cead4 LDR D24, [X21, X14] |
(2395) 0x4cead8 ADD X13, X13, #8 |
(2395) 0x4ceadc FABS D25, D24 |
(2395) 0x4ceae0 FADD D31, D31, D25 |
(2395) 0x4ceae4 STR D31, [X23, X0,LSL #3] |
(2395) 0x4ceae8 LDR D29, [X13], #8 |
(2395) 0x4ceaec FABS D30, D29 |
(2395) 0x4ceaf0 FADD D31, D31, D30 |
(2395) 0x4ceaf4 STR D31, [X23, X0,LSL #3] |
(2395) 0x4ceaf8 LDR D0, [X13], #8 |
(2395) 0x4ceafc FABS D2, D0 |
(2395) 0x4ceb00 FADD D31, D31, D2 |
(2395) 0x4ceb04 STR D31, [X23, X0,LSL #3] |
(2395) 0x4ceb08 LDR D1, [X13], #8 |
(2395) 0x4ceb0c FABS D3, D1 |
(2395) 0x4ceb10 FADD D31, D31, D3 |
(2395) 0x4ceb14 STR D31, [X23, X0,LSL #3] |
(2395) 0x4ceb18 LDR D4, [X13], #8 |
(2395) 0x4ceb1c FABS D5, D4 |
(2395) 0x4ceb20 FADD D31, D31, D5 |
(2395) 0x4ceb24 STR D31, [X23, X0,LSL #3] |
(2395) 0x4ceb28 LDR D6, [X13], #8 |
(2395) 0x4ceb2c FABS D7, D6 |
(2395) 0x4ceb30 FADD D31, D31, D7 |
(2395) 0x4ceb34 STR D31, [X23, X0,LSL #3] |
(2395) 0x4ceb38 LDR D16, [X13], #8 |
(2395) 0x4ceb3c FABS D19, D16 |
(2395) 0x4ceb40 FADD D31, D31, D19 |
(2395) 0x4ceb44 STR D31, [X23, X0,LSL #3] |
(2395) 0x4ceb48 CMP X13, X9 |
(2395) 0x4ceb4c B.EQ 4cea44 |
(2397) 0x4ceb50 ORR X5, XZR, X13 |
(2397) 0x4ceb54 ADD X13, X13, #64 |
(2397) 0x4ceb58 LDR D26, [X5], #8 |
(2397) 0x4ceb5c FABS D27, D26 |
(2397) 0x4ceb60 FADD D28, D31, D27 |
(2397) 0x4ceb64 STR D28, [X23, X0,LSL #3] |
(2397) 0x4ceb68 LDUR D17, [X13, #456] |
(2397) 0x4ceb6c FABS D18, D17 |
(2397) 0x4ceb70 FADD D20, D28, D18 |
(2397) 0x4ceb74 STR D20, [X23, X0,LSL #3] |
(2397) 0x4ceb78 LDR D22, [X5, #8] |
(2397) 0x4ceb7c FABS D21, D22 |
(2397) 0x4ceb80 FADD D23, D20, D21 |
(2397) 0x4ceb84 STR D23, [X23, X0,LSL #3] |
(2397) 0x4ceb88 LDUR D24, [X13, #472] |
(2397) 0x4ceb8c FABS D25, D24 |
(2397) 0x4ceb90 FADD D29, D23, D25 |
(2397) 0x4ceb94 STR D29, [X23, X0,LSL #3] |
(2397) 0x4ceb98 LDUR D30, [X13, #480] |
(2397) 0x4ceb9c FABS D0, D30 |
(2397) 0x4ceba0 FADD D2, D29, D0 |
(2397) 0x4ceba4 STR D2, [X23, X0,LSL #3] |
(2397) 0x4ceba8 LDUR D1, [X13, #488] |
(2397) 0x4cebac FABS D3, D1 |
(2397) 0x4cebb0 FADD D4, D2, D3 |
(2397) 0x4cebb4 STR D4, [X23, X0,LSL #3] |
(2397) 0x4cebb8 LDUR D5, [X13, #496] |
(2397) 0x4cebbc FABS D6, D5 |
(2397) 0x4cebc0 FADD D7, D4, D6 |
(2397) 0x4cebc4 STR D7, [X23, X0,LSL #3] |
(2397) 0x4cebc8 LDUR D16, [X13, #504] |
(2397) 0x4cebcc FABS D19, D16 |
(2397) 0x4cebd0 FADD D31, D7, D19 |
(2397) 0x4cebd4 STR D31, [X23, X0,LSL #3] |
(2397) 0x4cebd8 CMP X13, X9 |
(2397) 0x4cebdc B.NE 4ceb50 |
(2395) 0x4cebe0 B 4cea44 |
0x4cebe4 CMP X27, #0 |
0x4cebe8 B.LE 4ce9a0 |
0x4cebec STR XZR, [X23] |
0x4cebf0 LDP X0, X4, [X26] |
0x4cebf4 CBZ X22, 4cfb50 |
0x4cebf8 MOVZ X5, #0 |
0x4cebfc MOVZ X3, #0 |
0x4cec00 ADD X6, X26, #8 |
0x4cec04 LDR X18, [SP, #104] |
0x4cec08 ADD X10, X18, #8 |
(2392) 0x4cec0c LDR X1, [X22, X3,LSL #3] |
(2392) 0x4cec10 CMP X4, X0 |
(2392) 0x4cec14 B.LE 4cee44 |
(2392) 0x4cec18 SUB X11, X4, X0 |
(2392) 0x4cec1c ANDS X2, X11, #0x7 |
(2392) 0x4cec20 B.EQ 4cecfc |
(2392) 0x4cec24 CMP X2, #1 |
(2392) 0x4cec28 B.EQ 4ceccc |
(2392) 0x4cec2c CMP X2, #2 |
(2392) 0x4cec30 B.EQ 4cecb8 |
(2392) 0x4cec34 CMP X2, #3 |
(2392) 0x4cec38 B.EQ 4ceca4 |
(2392) 0x4cec3c CMP X2, #4 |
(2392) 0x4cec40 B.EQ 4cec90 |
(2392) 0x4cec44 CMP X2, #5 |
(2392) 0x4cec48 B.EQ 4cec7c |
(2392) 0x4cec4c CMP X2, #6 |
(2392) 0x4cec50 B.EQ 4cec68 |
(2392) 0x4cec54 LDR X8, [X25, X0,LSL #3] |
(2392) 0x4cec58 LDR X12, [X22, X8,LSL #3] |
(2392) 0x4cec5c CMP X1, X12 |
(2392) 0x4cec60 B.EQ 4cf3bc |
(2392) 0x4cec64 ADD X0, X0, #1 |
(2392) 0x4cec68 LDR X7, [X25, X0,LSL #3] |
(2392) 0x4cec6c LDR X9, [X22, X7,LSL #3] |
(2392) 0x4cec70 CMP X1, X9 |
(2392) 0x4cec74 B.EQ 4cf158 |
(2392) 0x4cec78 ADD X0, X0, #1 |
(2392) 0x4cec7c LDR X14, [X25, X0,LSL #3] |
(2392) 0x4cec80 LDR X15, [X22, X14,LSL #3] |
(2392) 0x4cec84 CMP X1, X15 |
(2392) 0x4cec88 B.EQ 4ceeb0 |
(2392) 0x4cec8c ADD X0, X0, #1 |
(2392) 0x4cec90 LDR X16, [X25, X0,LSL #3] |
(2392) 0x4cec94 LDR X17, [X22, X16,LSL #3] |
(2392) 0x4cec98 CMP X1, X17 |
(2392) 0x4cec9c B.EQ 4cee98 |
(2392) 0x4ceca0 ADD X0, X0, #1 |
(2392) 0x4ceca4 LDR X30, [X25, X0,LSL #3] |
(2392) 0x4ceca8 LDR X13, [X22, X30,LSL #3] |
(2392) 0x4cecac CMP X1, X13 |
(2392) 0x4cecb0 B.EQ 4cee80 |
(2392) 0x4cecb4 ADD X0, X0, #1 |
(2392) 0x4cecb8 LDR X18, [X25, X0,LSL #3] |
(2392) 0x4cecbc LDR X11, [X22, X18,LSL #3] |
(2392) 0x4cecc0 CMP X1, X11 |
(2392) 0x4cecc4 B.EQ 4cee68 |
(2392) 0x4cecc8 ADD X0, X0, #1 |
(2392) 0x4ceccc LDR X2, [X25, X0,LSL #3] |
(2392) 0x4cecd0 LDR X8, [X22, X2,LSL #3] |
(2392) 0x4cecd4 CMP X1, X8 |
(2392) 0x4cecd8 B.NE 4cecf0 |
(2392) 0x4cecdc LDR D31, [X24, X0,LSL #3] |
(2392) 0x4cece0 LDR D26, [X23, X3,LSL #3] |
(2392) 0x4cece4 FABS D27, D31 |
(2392) 0x4cece8 FADD D28, D26, D27 |
(2392) 0x4cecec STR D28, [X23, X3,LSL #3] |
(2392) 0x4cecf0 ADD X0, X0, #1 |
(2392) 0x4cecf4 CMP X0, X4 |
(2392) 0x4cecf8 B.EQ 4cee44 |
(2394) 0x4cecfc LDR X12, [X25, X0,LSL #3] |
(2394) 0x4ced00 LDR X7, [X22, X12,LSL #3] |
(2394) 0x4ced04 CMP X1, X7 |
(2394) 0x4ced08 B.NE 4ced20 |
(2394) 0x4ced0c LDR D17, [X24, X0,LSL #3] |
(2394) 0x4ced10 LDR D18, [X23, X3,LSL #3] |
(2394) 0x4ced14 FABS D20, D17 |
(2394) 0x4ced18 FADD D22, D18, D20 |
(2394) 0x4ced1c STR D22, [X23, X3,LSL #3] |
(2394) 0x4ced20 ADD X0, X0, #1 |
(2394) 0x4ced24 LDR X9, [X25, X0,LSL #3] |
(2394) 0x4ced28 LDR X14, [X22, X9,LSL #3] |
(2394) 0x4ced2c CMP X1, X14 |
(2394) 0x4ced30 B.NE 4ced48 |
(2394) 0x4ced34 LDR D21, [X24, X0,LSL #3] |
(2394) 0x4ced38 LDR D23, [X23, X3,LSL #3] |
(2394) 0x4ced3c FABS D24, D21 |
(2394) 0x4ced40 FADD D25, D23, D24 |
(2394) 0x4ced44 STR D25, [X23, X3,LSL #3] |
(2394) 0x4ced48 ADD X15, X0, #1 |
(2394) 0x4ced4c LDR X16, [X25, X15,LSL #3] |
(2394) 0x4ced50 LDR X17, [X22, X16,LSL #3] |
(2394) 0x4ced54 CMP X1, X17 |
(2394) 0x4ced58 B.NE 4ced70 |
(2394) 0x4ced5c LDR D29, [X24, X15,LSL #3] |
(2394) 0x4ced60 LDR D30, [X23, X3,LSL #3] |
(2394) 0x4ced64 FABS D0, D29 |
(2394) 0x4ced68 FADD D2, D30, D0 |
(2394) 0x4ced6c STR D2, [X23, X3,LSL #3] |
(2394) 0x4ced70 ADD X30, X0, #2 |
(2394) 0x4ced74 LDR X13, [X25, X30,LSL #3] |
(2394) 0x4ced78 LDR X18, [X22, X13,LSL #3] |
(2394) 0x4ced7c CMP X1, X18 |
(2394) 0x4ced80 B.NE 4ced98 |
(2394) 0x4ced84 LDR D1, [X24, X30,LSL #3] |
(2394) 0x4ced88 LDR D3, [X23, X3,LSL #3] |
(2394) 0x4ced8c FABS D4, D1 |
(2394) 0x4ced90 FADD D5, D3, D4 |
(2394) 0x4ced94 STR D5, [X23, X3,LSL #3] |
(2394) 0x4ced98 ADD X2, X0, #3 |
(2394) 0x4ced9c LDR X11, [X25, X2,LSL #3] |
(2394) 0x4ceda0 LDR X8, [X22, X11,LSL #3] |
(2394) 0x4ceda4 CMP X1, X8 |
(2394) 0x4ceda8 B.NE 4cedc0 |
(2394) 0x4cedac LDR D7, [X24, X2,LSL #3] |
(2394) 0x4cedb0 LDR D6, [X23, X3,LSL #3] |
(2394) 0x4cedb4 FABS D16, D7 |
(2394) 0x4cedb8 FADD D19, D6, D16 |
(2394) 0x4cedbc STR D19, [X23, X3,LSL #3] |
(2394) 0x4cedc0 ADD X12, X0, #4 |
(2394) 0x4cedc4 LDR X7, [X25, X12,LSL #3] |
(2394) 0x4cedc8 LDR X9, [X22, X7,LSL #3] |
(2394) 0x4cedcc CMP X1, X9 |
(2394) 0x4cedd0 B.NE 4cede8 |
(2394) 0x4cedd4 LDR D31, [X24, X12,LSL #3] |
(2394) 0x4cedd8 LDR D26, [X23, X3,LSL #3] |
(2394) 0x4ceddc FABS D27, D31 |
(2394) 0x4cede0 FADD D28, D26, D27 |
(2394) 0x4cede4 STR D28, [X23, X3,LSL #3] |
(2394) 0x4cede8 ADD X14, X0, #5 |
(2394) 0x4cedec LDR X15, [X25, X14,LSL #3] |
(2394) 0x4cedf0 LDR X16, [X22, X15,LSL #3] |
(2394) 0x4cedf4 CMP X1, X16 |
(2394) 0x4cedf8 B.NE 4cee10 |
(2394) 0x4cedfc LDR D17, [X24, X14,LSL #3] |
(2394) 0x4cee00 LDR D18, [X23, X3,LSL #3] |
(2394) 0x4cee04 FABS D20, D17 |
(2394) 0x4cee08 FADD D22, D18, D20 |
(2394) 0x4cee0c STR D22, [X23, X3,LSL #3] |
(2394) 0x4cee10 ADD X17, X0, #6 |
(2394) 0x4cee14 LDR X30, [X25, X17,LSL #3] |
(2394) 0x4cee18 LDR X13, [X22, X30,LSL #3] |
(2394) 0x4cee1c CMP X1, X13 |
(2394) 0x4cee20 B.NE 4cee38 |
(2394) 0x4cee24 LDR D21, [X24, X17,LSL #3] |
(2394) 0x4cee28 LDR D23, [X23, X3,LSL #3] |
(2394) 0x4cee2c FABS D24, D21 |
(2394) 0x4cee30 FADD D25, D23, D24 |
(2394) 0x4cee34 STR D25, [X23, X3,LSL #3] |
(2394) 0x4cee38 ADD X0, X0, #7 |
(2394) 0x4cee3c CMP X0, X4 |
(2394) 0x4cee40 B.NE 4cecfc |
(2392) 0x4cee44 CBNZ X19, 4cef04 |
(2392) 0x4cee48 ADD X5, X5, #1 |
(2392) 0x4cee4c CMP X27, X5 |
(2392) 0x4cee50 B.EQ 4ce680 |
(2392) 0x4cee54 LDR X0, [X26, X5,LSL #3] |
(2392) 0x4cee58 ORR X3, XZR, X5 |
(2392) 0x4cee5c STR XZR, [X23, X5,LSL #3] |
(2392) 0x4cee60 LDR X4, [X6, X5,LSL #3] |
(2392) 0x4cee64 B 4cec0c |
(2392) 0x4cee68 LDR D7, [X24, X0,LSL #3] |
(2392) 0x4cee6c LDR D6, [X23, X3,LSL #3] |
(2392) 0x4cee70 FABS D16, D7 |
(2392) 0x4cee74 FADD D19, D6, D16 |
(2392) 0x4cee78 STR D19, [X23, X3,LSL #3] |
(2392) 0x4cee7c B 4cecc8 |
(2392) 0x4cee80 LDR D1, [X24, X0,LSL #3] |
(2392) 0x4cee84 LDR D3, [X23, X3,LSL #3] |
(2392) 0x4cee88 FABS D4, D1 |
(2392) 0x4cee8c FADD D5, D3, D4 |
(2392) 0x4cee90 STR D5, [X23, X3,LSL #3] |
(2392) 0x4cee94 B 4cecb4 |
(2392) 0x4cee98 LDR D29, [X24, X0,LSL #3] |
(2392) 0x4cee9c LDR D30, [X23, X3,LSL #3] |
(2392) 0x4ceea0 FABS D0, D29 |
(2392) 0x4ceea4 FADD D2, D30, D0 |
(2392) 0x4ceea8 STR D2, [X23, X3,LSL #3] |
(2392) 0x4ceeac B 4ceca0 |
(2392) 0x4ceeb0 LDR D21, [X24, X0,LSL #3] |
(2392) 0x4ceeb4 LDR D23, [X23, X3,LSL #3] |
(2392) 0x4ceeb8 FABS D24, D21 |
(2392) 0x4ceebc FADD D25, D23, D24 |
(2392) 0x4ceec0 STR D25, [X23, X3,LSL #3] |
(2392) 0x4ceec4 B 4cec8c |
0x4ceec8 LDR D5, [X23, X8,LSL #3] |
0x4ceecc FNEG D7, D5 |
0x4ceed0 STR D7, [X23, X8,LSL #3] |
0x4ceed4 B 4ce730 |
0x4ceed8 LDR D1, [X23, X8,LSL #3] |
0x4ceedc FNEG D3, D1 |
0x4ceee0 STR D3, [X23, X8,LSL #3] |
0x4ceee4 B 4ce71c |
0x4ceee8 ADRP X27, |
0x4ceeec MOVZ X3, #0 |
0x4ceef0 ADD X0, X27, #496 |
0x4ceef4 MOVZ X2, #12 |
0x4ceef8 MOVZ X1, #728 |
0x4ceefc BL 52cf20 |
0x4cef00 B 4ce9a0 |
(2392) 0x4cef04 LDR X18, [SP, #104] |
(2392) 0x4cef08 LDR X4, [X10, X3,LSL #3] |
(2392) 0x4cef0c LDR X0, [X18, X3,LSL #3] |
(2392) 0x4cef10 CMP X0, X4 |
(2392) 0x4cef14 B.GE 4cfe70 |
(2392) 0x4cef18 SUB X2, X4, X0 |
(2392) 0x4cef1c ANDS X11, X2, #0x7 |
(2392) 0x4cef20 B.EQ 4ceffc |
(2392) 0x4cef24 CMP X11, #1 |
(2392) 0x4cef28 B.EQ 4cefcc |
(2392) 0x4cef2c CMP X11, #2 |
(2392) 0x4cef30 B.EQ 4cefb8 |
(2392) 0x4cef34 CMP X11, #3 |
(2392) 0x4cef38 B.EQ 4cefa4 |
(2392) 0x4cef3c CMP X11, #4 |
(2392) 0x4cef40 B.EQ 4cef90 |
(2392) 0x4cef44 CMP X11, #5 |
(2392) 0x4cef48 B.EQ 4cef7c |
(2392) 0x4cef4c CMP X11, #6 |
(2392) 0x4cef50 B.EQ 4cef68 |
(2392) 0x4cef54 LDR X8, [X20, X0,LSL #3] |
(2392) 0x4cef58 LDR X12, [X28, X8,LSL #3] |
(2392) 0x4cef5c CMP X1, X12 |
(2392) 0x4cef60 B.EQ 4cff40 |
(2392) 0x4cef64 ADD X0, X0, #1 |
(2392) 0x4cef68 LDR X7, [X20, X0,LSL #3] |
(2392) 0x4cef6c LDR X9, [X28, X7,LSL #3] |
(2392) 0x4cef70 CMP X1, X9 |
(2392) 0x4cef74 B.EQ 4cfea8 |
(2392) 0x4cef78 ADD X0, X0, #1 |
(2392) 0x4cef7c LDR X14, [X20, X0,LSL #3] |
(2392) 0x4cef80 LDR X15, [X28, X14,LSL #3] |
(2392) 0x4cef84 CMP X1, X15 |
(2392) 0x4cef88 B.EQ 4cf3d4 |
(2392) 0x4cef8c ADD X0, X0, #1 |
(2392) 0x4cef90 LDR X16, [X20, X0,LSL #3] |
(2392) 0x4cef94 LDR X17, [X28, X16,LSL #3] |
(2392) 0x4cef98 CMP X1, X17 |
(2392) 0x4cef9c B.EQ 4cf3a4 |
(2392) 0x4cefa0 ADD X0, X0, #1 |
(2392) 0x4cefa4 LDR X30, [X20, X0,LSL #3] |
(2392) 0x4cefa8 LDR X13, [X28, X30,LSL #3] |
(2392) 0x4cefac CMP X1, X13 |
(2392) 0x4cefb0 B.EQ 4cf37c |
(2392) 0x4cefb4 ADD X0, X0, #1 |
(2392) 0x4cefb8 LDR X18, [X20, X0,LSL #3] |
(2392) 0x4cefbc LDR X2, [X28, X18,LSL #3] |
(2392) 0x4cefc0 CMP X1, X2 |
(2392) 0x4cefc4 B.EQ 4cf180 |
(2392) 0x4cefc8 ADD X0, X0, #1 |
(2392) 0x4cefcc LDR X11, [X20, X0,LSL #3] |
(2392) 0x4cefd0 LDR X8, [X28, X11,LSL #3] |
(2392) 0x4cefd4 CMP X1, X8 |
(2392) 0x4cefd8 B.NE 4ceff0 |
(2392) 0x4cefdc LDR D29, [X21, X0,LSL #3] |
(2392) 0x4cefe0 LDR D30, [X23, X3,LSL #3] |
(2392) 0x4cefe4 FABS D0, D29 |
(2392) 0x4cefe8 FADD D2, D30, D0 |
(2392) 0x4cefec STR D2, [X23, X3,LSL #3] |
(2392) 0x4ceff0 ADD X0, X0, #1 |
(2392) 0x4ceff4 CMP X4, X0 |
(2392) 0x4ceff8 B.EQ 4cee48 |
(2393) 0x4ceffc LDR X12, [X20, X0,LSL #3] |
(2393) 0x4cf000 LDR X7, [X28, X12,LSL #3] |
(2393) 0x4cf004 CMP X1, X7 |
(2393) 0x4cf008 B.NE 4cf020 |
(2393) 0x4cf00c LDR D1, [X21, X0,LSL #3] |
(2393) 0x4cf010 LDR D3, [X23, X3,LSL #3] |
(2393) 0x4cf014 FABS D4, D1 |
(2393) 0x4cf018 FADD D5, D3, D4 |
(2393) 0x4cf01c STR D5, [X23, X3,LSL #3] |
(2393) 0x4cf020 ADD X0, X0, #1 |
(2393) 0x4cf024 LDR X9, [X20, X0,LSL #3] |
(2393) 0x4cf028 LDR X14, [X28, X9,LSL #3] |
(2393) 0x4cf02c CMP X1, X14 |
(2393) 0x4cf030 B.NE 4cf048 |
(2393) 0x4cf034 LDR D7, [X21, X0,LSL #3] |
(2393) 0x4cf038 LDR D6, [X23, X3,LSL #3] |
(2393) 0x4cf03c FABS D16, D7 |
(2393) 0x4cf040 FADD D19, D6, D16 |
(2393) 0x4cf044 STR D19, [X23, X3,LSL #3] |
(2393) 0x4cf048 ADD X15, X0, #1 |
(2393) 0x4cf04c LDR X16, [X20, X15,LSL #3] |
(2393) 0x4cf050 LDR X17, [X28, X16,LSL #3] |
(2393) 0x4cf054 CMP X1, X17 |
(2393) 0x4cf058 B.NE 4cf070 |
(2393) 0x4cf05c LDR D31, [X21, X15,LSL #3] |
(2393) 0x4cf060 LDR D26, [X23, X3,LSL #3] |
(2393) 0x4cf064 FABS D27, D31 |
(2393) 0x4cf068 FADD D28, D26, D27 |
(2393) 0x4cf06c STR D28, [X23, X3,LSL #3] |
(2393) 0x4cf070 ADD X30, X0, #2 |
(2393) 0x4cf074 LDR X13, [X20, X30,LSL #3] |
(2393) 0x4cf078 LDR X18, [X28, X13,LSL #3] |
(2393) 0x4cf07c CMP X1, X18 |
(2393) 0x4cf080 B.NE 4cf098 |
(2393) 0x4cf084 LDR D17, [X21, X30,LSL #3] |
(2393) 0x4cf088 LDR D18, [X23, X3,LSL #3] |
(2393) 0x4cf08c FABS D20, D17 |
(2393) 0x4cf090 FADD D22, D18, D20 |
(2393) 0x4cf094 STR D22, [X23, X3,LSL #3] |
(2393) 0x4cf098 ADD X2, X0, #3 |
(2393) 0x4cf09c LDR X11, [X20, X2,LSL #3] |
(2393) 0x4cf0a0 LDR X8, [X28, X11,LSL #3] |
(2393) 0x4cf0a4 CMP X1, X8 |
(2393) 0x4cf0a8 B.NE 4cf0c0 |
(2393) 0x4cf0ac LDR D21, [X21, X2,LSL #3] |
(2393) 0x4cf0b0 LDR D23, [X23, X3,LSL #3] |
(2393) 0x4cf0b4 FABS D24, D21 |
(2393) 0x4cf0b8 FADD D25, D23, D24 |
(2393) 0x4cf0bc STR D25, [X23, X3,LSL #3] |
(2393) 0x4cf0c0 ADD X12, X0, #4 |
(2393) 0x4cf0c4 LDR X7, [X20, X12,LSL #3] |
(2393) 0x4cf0c8 LDR X9, [X28, X7,LSL #3] |
(2393) 0x4cf0cc CMP X1, X9 |
(2393) 0x4cf0d0 B.NE 4cf0e8 |
(2393) 0x4cf0d4 LDR D29, [X21, X12,LSL #3] |
(2393) 0x4cf0d8 LDR D30, [X23, X3,LSL #3] |
(2393) 0x4cf0dc FABS D0, D29 |
(2393) 0x4cf0e0 FADD D2, D30, D0 |
(2393) 0x4cf0e4 STR D2, [X23, X3,LSL #3] |
(2393) 0x4cf0e8 ADD X14, X0, #5 |
(2393) 0x4cf0ec LDR X15, [X20, X14,LSL #3] |
(2393) 0x4cf0f0 LDR X16, [X28, X15,LSL #3] |
(2393) 0x4cf0f4 CMP X1, X16 |
(2393) 0x4cf0f8 B.NE 4cf110 |
(2393) 0x4cf0fc LDR D1, [X21, X14,LSL #3] |
(2393) 0x4cf100 LDR D3, [X23, X3,LSL #3] |
(2393) 0x4cf104 FABS D4, D1 |
(2393) 0x4cf108 FADD D5, D3, D4 |
(2393) 0x4cf10c STR D5, [X23, X3,LSL #3] |
(2393) 0x4cf110 ADD X17, X0, #6 |
(2393) 0x4cf114 LDR X30, [X20, X17,LSL #3] |
(2393) 0x4cf118 LDR X13, [X28, X30,LSL #3] |
(2393) 0x4cf11c CMP X1, X13 |
(2393) 0x4cf120 B.NE 4cf138 |
(2393) 0x4cf124 LDR D7, [X21, X17,LSL #3] |
(2393) 0x4cf128 LDR D6, [X23, X3,LSL #3] |
(2393) 0x4cf12c FABS D16, D7 |
(2393) 0x4cf130 FADD D19, D6, D16 |
(2393) 0x4cf134 STR D19, [X23, X3,LSL #3] |
(2393) 0x4cf138 ADD X0, X0, #7 |
(2393) 0x4cf13c CMP X4, X0 |
(2393) 0x4cf140 B.NE 4ceffc |
(2392) 0x4cf144 B 4cee48 |
0x4cf148 LDR D29, [X23, X8,LSL #3] |
0x4cf14c FNEG D30, D29 |
0x4cf150 STR D30, [X23, X8,LSL #3] |
0x4cf154 B 4ce708 |
(2392) 0x4cf158 LDR D17, [X24, X0,LSL #3] |
(2392) 0x4cf15c LDR D18, [X23, X3,LSL #3] |
(2392) 0x4cf160 FABS D20, D17 |
(2392) 0x4cf164 FADD D22, D18, D20 |
(2392) 0x4cf168 STR D22, [X23, X3,LSL #3] |
(2392) 0x4cf16c B 4cec78 |
0x4cf170 LDR D23, [X23, X8,LSL #3] |
0x4cf174 FNEG D24, D23 |
0x4cf178 STR D24, [X23, X8,LSL #3] |
0x4cf17c B 4ce6f4 |
(2392) 0x4cf180 LDR D21, [X21, X0,LSL #3] |
(2392) 0x4cf184 LDR D23, [X23, X3,LSL #3] |
(2392) 0x4cf188 FABS D24, D21 |
(2392) 0x4cf18c FADD D25, D23, D24 |
(2392) 0x4cf190 STR D25, [X23, X3,LSL #3] |
(2392) 0x4cf194 B 4cefc8 |
0x4cf198 CMP X27, #0 |
0x4cf19c B.LE 4ce9a0 |
0x4cf1a0 LDR X12, [SP, #104] |
0x4cf1a4 ORR X25, XZR, #0x55 |
0x4cf1a8 FMOV D26, #0.5000000 |
0x4cf1ac MOVK X25, #16373 |
0x4cf1b0 MOVZ X0, #0 |
0x4cf1b4 FMOV D27, X25 |
0x4cf1b8 ADD X10, X12, #8 |
0x4cf1bc B 4cf1e0 |
(2402) 0x4cf1c0 CBNZ X19, 4cf680 |
(2402) 0x4cf1c4 FMUL D19, D28, D27 |
(2402) 0x4cf1c8 FCMPE D19, D31 |
(2402) 0x4cf1cc B.MI 4cf1d4 |
(2402) 0x4cf1d0 STR D28, [X23, X0,LSL #3] |
(2402) 0x4cf1d4 ADD X0, X0, #1 |
(2402) 0x4cf1d8 CMP X27, X0 |
(2402) 0x4cf1dc B.EQ 4ce680 |
(2402) 0x4cf1e0 LDR X7, [X26, X0,LSL #3] |
(2402) 0x4cf1e4 LDR D0, [X24, X7,LSL #3] |
(2402) 0x4cf1e8 FABS D28, D0 |
(2402) 0x4cf1ec STR D28, [X23, X0,LSL #3] |
(2402) 0x4cf1f0 FMOV D31, D28 |
(2402) 0x4cf1f4 CBNZ X22, 4cf1c0 |
(2402) 0x4cf1f8 CBZ X19, 4cf1c4 |
(2402) 0x4cf1fc LDR X8, [SP, #104] |
(2402) 0x4cf200 ADD X13, X8, #8 |
(2402) 0x4cf204 LDR X5, [X8, X0,LSL #3] |
(2402) 0x4cf208 LDR X4, [X13, X0,LSL #3] |
(2402) 0x4cf20c CMP X5, X4 |
(2402) 0x4cf210 B.GE 4cf1c4 |
(2402) 0x4cf214 ADD X11, X21, X4,LSL #3 |
(2402) 0x4cf218 FMOV D19, #0.5000000 |
(2402) 0x4cf21c UBFM X6, X5, #61, #60 |
(2402) 0x4cf220 ADD X9, X21, X5,LSL #3 |
(2402) 0x4cf224 SUB X3, X11, X9 |
(2402) 0x4cf228 SUB X2, X3, #8 |
(2402) 0x4cf22c UBFM X25, X2, #3, #63 |
(2402) 0x4cf230 ADD X12, X25, #1 |
(2402) 0x4cf234 ANDS X7, X12, #0x7 |
(2402) 0x4cf238 B.EQ 4cf2e8 |
(2402) 0x4cf23c CMP X7, #1 |
(2402) 0x4cf240 B.EQ 4cf2d0 |
(2402) 0x4cf244 CMP X7, #2 |
(2402) 0x4cf248 B.EQ 4cf2c0 |
(2402) 0x4cf24c CMP X7, #3 |
(2402) 0x4cf250 B.EQ 4cf2b0 |
(2402) 0x4cf254 CMP X7, #4 |
(2402) 0x4cf258 B.EQ 4cf2a0 |
(2402) 0x4cf25c CMP X7, #5 |
(2402) 0x4cf260 B.EQ 4cf290 |
(2402) 0x4cf264 CMP X7, #6 |
(2402) 0x4cf268 B.EQ 4cf280 |
(2402) 0x4cf26c LDR D20, [X21, X6] |
(2402) 0x4cf270 ADD X9, X9, #8 |
(2402) 0x4cf274 FABS D21, D20 |
(2402) 0x4cf278 FMADD D31, D21, D19, D28 |
(2402) 0x4cf27c STR D31, [X23, X0,LSL #3] |
(2402) 0x4cf280 LDR D22, [X9], #8 |
(2402) 0x4cf284 FABS D23, D22 |
(2402) 0x4cf288 FMADD D31, D23, D19, D31 |
(2402) 0x4cf28c STR D31, [X23, X0,LSL #3] |
(2402) 0x4cf290 LDR D24, [X9], #8 |
(2402) 0x4cf294 FABS D25, D24 |
(2402) 0x4cf298 FMADD D31, D25, D19, D31 |
(2402) 0x4cf29c STR D31, [X23, X0,LSL #3] |
(2402) 0x4cf2a0 LDR D29, [X9], #8 |
(2402) 0x4cf2a4 FABS D30, D29 |
(2402) 0x4cf2a8 FMADD D31, D30, D19, D31 |
(2402) 0x4cf2ac STR D31, [X23, X0,LSL #3] |
(2402) 0x4cf2b0 LDR D0, [X9], #8 |
(2402) 0x4cf2b4 FABS D1, D0 |
(2402) 0x4cf2b8 FMADD D31, D1, D19, D31 |
(2402) 0x4cf2bc STR D31, [X23, X0,LSL #3] |
(2402) 0x4cf2c0 LDR D2, [X9], #8 |
(2402) 0x4cf2c4 FABS D3, D2 |
(2402) 0x4cf2c8 FMADD D31, D3, D19, D31 |
(2402) 0x4cf2cc STR D31, [X23, X0,LSL #3] |
(2402) 0x4cf2d0 LDR D4, [X9], #8 |
(2402) 0x4cf2d4 FABS D5, D4 |
(2402) 0x4cf2d8 FMADD D31, D5, D19, D31 |
(2402) 0x4cf2dc STR D31, [X23, X0,LSL #3] |
(2402) 0x4cf2e0 CMP X9, X11 |
(2402) 0x4cf2e4 B.EQ 4cf1c4 |
(2404) 0x4cf2e8 ORR X14, XZR, X9 |
(2404) 0x4cf2ec ADD X9, X9, #64 |
(2404) 0x4cf2f0 LDR D6, [X14], #8 |
(2404) 0x4cf2f4 FABS D7, D6 |
(2404) 0x4cf2f8 FMADD D16, D7, D19, D31 |
(2404) 0x4cf2fc STR D16, [X23, X0,LSL #3] |
(2404) 0x4cf300 LDUR D17, [X9, #456] |
(2404) 0x4cf304 FABS D18, D17 |
(2404) 0x4cf308 FMADD D20, D18, D19, D16 |
(2404) 0x4cf30c STR D20, [X23, X0,LSL #3] |
(2404) 0x4cf310 LDR D31, [X14, #8] |
(2404) 0x4cf314 FABS D21, D31 |
(2404) 0x4cf318 FMADD D22, D21, D19, D20 |
(2404) 0x4cf31c STR D22, [X23, X0,LSL #3] |
(2404) 0x4cf320 LDUR D23, [X9, #472] |
(2404) 0x4cf324 FABS D24, D23 |
(2404) 0x4cf328 FMADD D25, D24, D19, D22 |
(2404) 0x4cf32c STR D25, [X23, X0,LSL #3] |
(2404) 0x4cf330 LDUR D29, [X9, #480] |
(2404) 0x4cf334 FABS D30, D29 |
(2404) 0x4cf338 FMADD D0, D30, D19, D25 |
(2404) 0x4cf33c STR D0, [X23, X0,LSL #3] |
(2404) 0x4cf340 LDUR D1, [X9, #488] |
(2404) 0x4cf344 FABS D2, D1 |
(2404) 0x4cf348 FMADD D3, D2, D19, D0 |
(2404) 0x4cf34c STR D3, [X23, X0,LSL #3] |
(2404) 0x4cf350 LDUR D4, [X9, #496] |
(2404) 0x4cf354 FABS D5, D4 |
(2404) 0x4cf358 FMADD D6, D5, D19, D3 |
(2404) 0x4cf35c STR D6, [X23, X0,LSL #3] |
(2404) 0x4cf360 LDUR D7, [X9, #504] |
(2404) 0x4cf364 FABS D16, D7 |
(2404) 0x4cf368 FMADD D31, D16, D19, D6 |
(2404) 0x4cf36c STR D31, [X23, X0,LSL #3] |
(2404) 0x4cf370 CMP X9, X11 |
(2404) 0x4cf374 B.NE 4cf2e8 |
(2402) 0x4cf378 B 4cf1c4 |
(2392) 0x4cf37c LDR D17, [X21, X0,LSL #3] |
(2392) 0x4cf380 LDR D18, [X23, X3,LSL #3] |
(2392) 0x4cf384 FABS D20, D17 |
(2392) 0x4cf388 FADD D22, D18, D20 |
(2392) 0x4cf38c STR D22, [X23, X3,LSL #3] |
(2392) 0x4cf390 B 4cefb4 |
0x4cf394 LDR D20, [X23, X8,LSL #3] |
0x4cf398 FNEG D22, D20 |
0x4cf39c STR D22, [X23, X8,LSL #3] |
0x4cf3a0 B 4ce6e0 |
(2392) 0x4cf3a4 LDR D31, [X21, X0,LSL #3] |
(2392) 0x4cf3a8 LDR D26, [X23, X3,LSL #3] |
(2392) 0x4cf3ac FABS D27, D31 |
(2392) 0x4cf3b0 FADD D28, D26, D27 |
(2392) 0x4cf3b4 STR D28, [X23, X3,LSL #3] |
(2392) 0x4cf3b8 B 4cefa0 |
(2392) 0x4cf3bc LDR D31, [X24, X0,LSL #3] |
(2392) 0x4cf3c0 LDR D26, [X23, X3,LSL #3] |
(2392) 0x4cf3c4 FABS D27, D31 |
(2392) 0x4cf3c8 FADD D28, D26, D27 |
(2392) 0x4cf3cc STR D28, [X23, X3,LSL #3] |
(2392) 0x4cf3d0 B 4cec64 |
(2392) 0x4cf3d4 LDR D7, [X21, X0,LSL #3] |
(2392) 0x4cf3d8 ADD X0, X0, #1 |
(2392) 0x4cf3dc LDR D6, [X23, X3,LSL #3] |
(2392) 0x4cf3e0 FABS D16, D7 |
(2392) 0x4cf3e4 FADD D19, D6, D16 |
(2392) 0x4cf3e8 STR D19, [X23, X3,LSL #3] |
(2392) 0x4cf3ec B 4cef90 |
(2395) 0x4cf3f0 LDR X13, [SP, #104] |
(2395) 0x4cf3f4 LDR X8, [X18, X0,LSL #3] |
(2395) 0x4cf3f8 LDR X1, [X13, X0,LSL #3] |
(2395) 0x4cf3fc CMP X1, X8 |
(2395) 0x4cf400 B.GE 4cea44 |
(2395) 0x4cf404 SUB X5, X8, X1 |
(2395) 0x4cf408 LDR X4, [X22, X0,LSL #3] |
(2395) 0x4cf40c ANDS X11, X5, #0x7 |
(2395) 0x4cf410 B.EQ 4cf4ec |
(2395) 0x4cf414 CMP X11, #1 |
(2395) 0x4cf418 B.EQ 4cf4bc |
(2395) 0x4cf41c CMP X11, #2 |
(2395) 0x4cf420 B.EQ 4cf4a8 |
(2395) 0x4cf424 CMP X11, #3 |
(2395) 0x4cf428 B.EQ 4cf494 |
(2395) 0x4cf42c CMP X11, #4 |
(2395) 0x4cf430 B.EQ 4cf480 |
(2395) 0x4cf434 CMP X11, #5 |
(2395) 0x4cf438 B.EQ 4cf46c |
(2395) 0x4cf43c CMP X11, #6 |
(2395) 0x4cf440 B.EQ 4cf458 |
(2395) 0x4cf444 LDR X6, [X20, X1,LSL #3] |
(2395) 0x4cf448 LDR X3, [X28, X6,LSL #3] |
(2395) 0x4cf44c CMP X4, X3 |
(2395) 0x4cf450 B.EQ 4cff58 |
(2395) 0x4cf454 ADD X1, X1, #1 |
(2395) 0x4cf458 LDR X2, [X20, X1,LSL #3] |
(2395) 0x4cf45c LDR X25, [X28, X2,LSL #3] |
(2395) 0x4cf460 CMP X4, X25 |
(2395) 0x4cf464 B.EQ 4cff00 |
(2395) 0x4cf468 ADD X1, X1, #1 |
(2395) 0x4cf46c LDR X12, [X20, X1,LSL #3] |
(2395) 0x4cf470 LDR X7, [X28, X12,LSL #3] |
(2395) 0x4cf474 CMP X4, X7 |
(2395) 0x4cf478 B.EQ 4cfec0 |
(2395) 0x4cf47c ADD X1, X1, #1 |
(2395) 0x4cf480 LDR X9, [X20, X1,LSL #3] |
(2395) 0x4cf484 LDR X14, [X28, X9,LSL #3] |
(2395) 0x4cf488 CMP X4, X14 |
(2395) 0x4cf48c B.EQ 4cf668 |
(2395) 0x4cf490 ADD X1, X1, #1 |
(2395) 0x4cf494 LDR X15, [X20, X1,LSL #3] |
(2395) 0x4cf498 LDR X16, [X28, X15,LSL #3] |
(2395) 0x4cf49c CMP X4, X16 |
(2395) 0x4cf4a0 B.EQ 4cf650 |
(2395) 0x4cf4a4 ADD X1, X1, #1 |
(2395) 0x4cf4a8 LDR X17, [X20, X1,LSL #3] |
(2395) 0x4cf4ac LDR X10, [X28, X17,LSL #3] |
(2395) 0x4cf4b0 CMP X4, X10 |
(2395) 0x4cf4b4 B.EQ 4cf638 |
(2395) 0x4cf4b8 ADD X1, X1, #1 |
(2395) 0x4cf4bc LDR X30, [X20, X1,LSL #3] |
(2395) 0x4cf4c0 LDR X13, [X28, X30,LSL #3] |
(2395) 0x4cf4c4 CMP X4, X13 |
(2395) 0x4cf4c8 B.NE 4cf4e0 |
(2395) 0x4cf4cc LDR D31, [X21, X1,LSL #3] |
(2395) 0x4cf4d0 LDR D16, [X23, X0,LSL #3] |
(2395) 0x4cf4d4 FABS D19, D31 |
(2395) 0x4cf4d8 FADD D26, D16, D19 |
(2395) 0x4cf4dc STR D26, [X23, X0,LSL #3] |
(2395) 0x4cf4e0 ADD X1, X1, #1 |
(2395) 0x4cf4e4 CMP X8, X1 |
(2395) 0x4cf4e8 B.EQ 4cea44 |
(2396) 0x4cf4ec LDR X5, [X20, X1,LSL #3] |
(2396) 0x4cf4f0 LDR X11, [X28, X5,LSL #3] |
(2396) 0x4cf4f4 CMP X4, X11 |
(2396) 0x4cf4f8 B.NE 4cf510 |
(2396) 0x4cf4fc LDR D27, [X21, X1,LSL #3] |
(2396) 0x4cf500 LDR D28, [X23, X0,LSL #3] |
(2396) 0x4cf504 FABS D17, D27 |
(2396) 0x4cf508 FADD D18, D28, D17 |
(2396) 0x4cf50c STR D18, [X23, X0,LSL #3] |
(2396) 0x4cf510 ADD X1, X1, #1 |
(2396) 0x4cf514 LDR X6, [X20, X1,LSL #3] |
(2396) 0x4cf518 LDR X3, [X28, X6,LSL #3] |
(2396) 0x4cf51c CMP X4, X3 |
(2396) 0x4cf520 B.NE 4cf538 |
(2396) 0x4cf524 LDR D20, [X21, X1,LSL #3] |
(2396) 0x4cf528 LDR D22, [X23, X0,LSL #3] |
(2396) 0x4cf52c FABS D21, D20 |
(2396) 0x4cf530 FADD D23, D22, D21 |
(2396) 0x4cf534 STR D23, [X23, X0,LSL #3] |
(2396) 0x4cf538 ADD X2, X1, #1 |
(2396) 0x4cf53c LDR X25, [X20, X2,LSL #3] |
(2396) 0x4cf540 LDR X12, [X28, X25,LSL #3] |
(2396) 0x4cf544 CMP X4, X12 |
(2396) 0x4cf548 B.NE 4cf560 |
(2396) 0x4cf54c LDR D24, [X21, X2,LSL #3] |
(2396) 0x4cf550 LDR D25, [X23, X0,LSL #3] |
(2396) 0x4cf554 FABS D29, D24 |
(2396) 0x4cf558 FADD D30, D25, D29 |
(2396) 0x4cf55c STR D30, [X23, X0,LSL #3] |
(2396) 0x4cf560 ADD X7, X1, #2 |
(2396) 0x4cf564 LDR X9, [X20, X7,LSL #3] |
(2396) 0x4cf568 LDR X14, [X28, X9,LSL #3] |
(2396) 0x4cf56c CMP X4, X14 |
(2396) 0x4cf570 B.NE 4cf588 |
(2396) 0x4cf574 LDR D0, [X21, X7,LSL #3] |
(2396) 0x4cf578 LDR D2, [X23, X0,LSL #3] |
(2396) 0x4cf57c FABS D1, D0 |
(2396) 0x4cf580 FADD D3, D2, D1 |
(2396) 0x4cf584 STR D3, [X23, X0,LSL #3] |
(2396) 0x4cf588 ADD X15, X1, #3 |
(2396) 0x4cf58c LDR X16, [X20, X15,LSL #3] |
(2396) 0x4cf590 LDR X17, [X28, X16,LSL #3] |
(2396) 0x4cf594 CMP X4, X17 |
(2396) 0x4cf598 B.NE 4cf5b0 |
(2396) 0x4cf59c LDR D4, [X21, X15,LSL #3] |
(2396) 0x4cf5a0 LDR D5, [X23, X0,LSL #3] |
(2396) 0x4cf5a4 FABS D6, D4 |
(2396) 0x4cf5a8 FADD D7, D5, D6 |
(2396) 0x4cf5ac STR D7, [X23, X0,LSL #3] |
(2396) 0x4cf5b0 ADD X10, X1, #4 |
(2396) 0x4cf5b4 LDR X30, [X20, X10,LSL #3] |
(2396) 0x4cf5b8 LDR X13, [X28, X30,LSL #3] |
(2396) 0x4cf5bc CMP X4, X13 |
(2396) 0x4cf5c0 B.NE 4cf5d8 |
(2396) 0x4cf5c4 LDR D31, [X21, X10,LSL #3] |
(2396) 0x4cf5c8 LDR D16, [X23, X0,LSL #3] |
(2396) 0x4cf5cc FABS D19, D31 |
(2396) 0x4cf5d0 FADD D26, D16, D19 |
(2396) 0x4cf5d4 STR D26, [X23, X0,LSL #3] |
(2396) 0x4cf5d8 ADD X5, X1, #5 |
(2396) 0x4cf5dc LDR X11, [X20, X5,LSL #3] |
(2396) 0x4cf5e0 LDR X6, [X28, X11,LSL #3] |
(2396) 0x4cf5e4 CMP X4, X6 |
(2396) 0x4cf5e8 B.NE 4cf600 |
(2396) 0x4cf5ec LDR D27, [X21, X5,LSL #3] |
(2396) 0x4cf5f0 LDR D28, [X23, X0,LSL #3] |
(2396) 0x4cf5f4 FABS D17, D27 |
(2396) 0x4cf5f8 FADD D18, D28, D17 |
(2396) 0x4cf5fc STR D18, [X23, X0,LSL #3] |
(2396) 0x4cf600 ADD X3, X1, #6 |
(2396) 0x4cf604 LDR X2, [X20, X3,LSL #3] |
(2396) 0x4cf608 LDR X25, [X28, X2,LSL #3] |
(2396) 0x4cf60c CMP X4, X25 |
(2396) 0x4cf610 B.NE 4cf628 |
(2396) 0x4cf614 LDR D20, [X21, X3,LSL #3] |
(2396) 0x4cf618 LDR D22, [X23, X0,LSL #3] |
(2396) 0x4cf61c FABS D21, D20 |
(2396) 0x4cf620 FADD D23, D22, D21 |
(2396) 0x4cf624 STR D23, [X23, X0,LSL #3] |
(2396) 0x4cf628 ADD X1, X1, #7 |
(2396) 0x4cf62c CMP X8, X1 |
(2396) 0x4cf630 B.NE 4cf4ec |
(2395) 0x4cf634 B 4cea44 |
(2395) 0x4cf638 LDR D4, [X21, X1,LSL #3] |
(2395) 0x4cf63c LDR D5, [X23, X0,LSL #3] |
(2395) 0x4cf640 FABS D6, D4 |
(2395) 0x4cf644 FADD D7, D5, D6 |
(2395) 0x4cf648 STR D7, [X23, X0,LSL #3] |
(2395) 0x4cf64c B 4cf4b8 |
(2395) 0x4cf650 LDR D0, [X21, X1,LSL #3] |
(2395) 0x4cf654 LDR D2, [X23, X0,LSL #3] |
(2395) 0x4cf658 FABS D1, D0 |
(2395) 0x4cf65c FADD D3, D2, D1 |
(2395) 0x4cf660 STR D3, [X23, X0,LSL #3] |
(2395) 0x4cf664 B 4cf4a4 |
(2395) 0x4cf668 LDR D24, [X21, X1,LSL #3] |
(2395) 0x4cf66c LDR D25, [X23, X0,LSL #3] |
(2395) 0x4cf670 FABS D29, D24 |
(2395) 0x4cf674 FADD D30, D25, D29 |
(2395) 0x4cf678 STR D30, [X23, X0,LSL #3] |
(2395) 0x4cf67c B 4cf490 |
(2402) 0x4cf680 LDR X9, [SP, #104] |
(2402) 0x4cf684 LDR X8, [X10, X0,LSL #3] |
(2402) 0x4cf688 LDR X1, [X9, X0,LSL #3] |
(2402) 0x4cf68c CMP X1, X8 |
(2402) 0x4cf690 B.GE 4cf1c4 |
(2402) 0x4cf694 SUB X14, X8, X1 |
(2402) 0x4cf698 LDR X13, [X22, X0,LSL #3] |
(2402) 0x4cf69c ANDS X15, X14, #0x7 |
(2402) 0x4cf6a0 B.EQ 4cf778 |
(2402) 0x4cf6a4 CMP X15, #1 |
(2402) 0x4cf6a8 B.EQ 4cf74c |
(2402) 0x4cf6ac CMP X15, #2 |
(2402) 0x4cf6b0 B.EQ 4cf738 |
(2402) 0x4cf6b4 CMP X15, #3 |
(2402) 0x4cf6b8 B.EQ 4cf724 |
(2402) 0x4cf6bc CMP X15, #4 |
(2402) 0x4cf6c0 B.EQ 4cf710 |
(2402) 0x4cf6c4 CMP X15, #5 |
(2402) 0x4cf6c8 B.EQ 4cf6fc |
(2402) 0x4cf6cc CMP X15, #6 |
(2402) 0x4cf6d0 B.EQ 4cf6e8 |
(2402) 0x4cf6d4 LDR X16, [X20, X1,LSL #3] |
(2402) 0x4cf6d8 LDR X17, [X28, X16,LSL #3] |
(2402) 0x4cf6dc CMP X13, X17 |
(2402) 0x4cf6e0 B.EQ 4cff9c |
(2402) 0x4cf6e4 ADD X1, X1, #1 |
(2402) 0x4cf6e8 LDR X18, [X20, X1,LSL #3] |
(2402) 0x4cf6ec LDR X30, [X28, X18,LSL #3] |
(2402) 0x4cf6f0 CMP X13, X30 |
(2402) 0x4cf6f4 B.EQ 4cff88 |
(2402) 0x4cf6f8 ADD X1, X1, #1 |
(2402) 0x4cf6fc LDR X5, [X20, X1,LSL #3] |
(2402) 0x4cf700 LDR X4, [X28, X5,LSL #3] |
(2402) 0x4cf704 CMP X13, X4 |
(2402) 0x4cf708 B.EQ 4cff70 |
(2402) 0x4cf70c ADD X1, X1, #1 |
(2402) 0x4cf710 LDR X11, [X20, X1,LSL #3] |
(2402) 0x4cf714 LDR X6, [X28, X11,LSL #3] |
(2402) 0x4cf718 CMP X13, X6 |
(2402) 0x4cf71c B.EQ 4cff2c |
(2402) 0x4cf720 ADD X1, X1, #1 |
(2402) 0x4cf724 LDR X3, [X20, X1,LSL #3] |
(2402) 0x4cf728 LDR X2, [X28, X3,LSL #3] |
(2402) 0x4cf72c CMP X13, X2 |
(2402) 0x4cf730 B.EQ 4cff18 |
(2402) 0x4cf734 ADD X1, X1, #1 |
(2402) 0x4cf738 LDR X25, [X20, X1,LSL #3] |
(2402) 0x4cf73c LDR X12, [X28, X25,LSL #3] |
(2402) 0x4cf740 CMP X13, X12 |
(2402) 0x4cf744 B.EQ 4cfeec |
(2402) 0x4cf748 ADD X1, X1, #1 |
(2402) 0x4cf74c LDR X7, [X20, X1,LSL #3] |
(2402) 0x4cf750 LDR X9, [X28, X7,LSL #3] |
(2402) 0x4cf754 CMP X13, X9 |
(2402) 0x4cf758 B.NE 4cf76c |
(2402) 0x4cf75c LDR D21, [X21, X1,LSL #3] |
(2402) 0x4cf760 FABS D22, D21 |
(2402) 0x4cf764 FMADD D31, D22, D26, D31 |
(2402) 0x4cf768 STR D31, [X23, X0,LSL #3] |
(2402) 0x4cf76c ADD X1, X1, #1 |
(2402) 0x4cf770 CMP X8, X1 |
(2402) 0x4cf774 B.EQ 4cf1c4 |
(2403) 0x4cf778 LDR X14, [X20, X1,LSL #3] |
(2403) 0x4cf77c LDR X15, [X28, X14,LSL #3] |
(2403) 0x4cf780 CMP X13, X15 |
(2403) 0x4cf784 B.NE 4cf798 |
(2403) 0x4cf788 LDR D23, [X21, X1,LSL #3] |
(2403) 0x4cf78c FABS D24, D23 |
(2403) 0x4cf790 FMADD D31, D24, D26, D31 |
(2403) 0x4cf794 STR D31, [X23, X0,LSL #3] |
(2403) 0x4cf798 ADD X1, X1, #1 |
(2403) 0x4cf79c LDR X16, [X20, X1,LSL #3] |
(2403) 0x4cf7a0 LDR X17, [X28, X16,LSL #3] |
(2403) 0x4cf7a4 CMP X13, X17 |
(2403) 0x4cf7a8 B.NE 4cf7bc |
(2403) 0x4cf7ac LDR D25, [X21, X1,LSL #3] |
(2403) 0x4cf7b0 FABS D29, D25 |
(2403) 0x4cf7b4 FMADD D31, D29, D26, D31 |
(2403) 0x4cf7b8 STR D31, [X23, X0,LSL #3] |
(2403) 0x4cf7bc ADD X18, X1, #1 |
(2403) 0x4cf7c0 LDR X30, [X20, X18,LSL #3] |
(2403) 0x4cf7c4 LDR X5, [X28, X30,LSL #3] |
(2403) 0x4cf7c8 CMP X13, X5 |
(2403) 0x4cf7cc B.NE 4cf7e0 |
(2403) 0x4cf7d0 LDR D30, [X21, X18,LSL #3] |
(2403) 0x4cf7d4 FABS D0, D30 |
(2403) 0x4cf7d8 FMADD D31, D0, D26, D31 |
(2403) 0x4cf7dc STR D31, [X23, X0,LSL #3] |
(2403) 0x4cf7e0 ADD X4, X1, #2 |
(2403) 0x4cf7e4 LDR X11, [X20, X4,LSL #3] |
(2403) 0x4cf7e8 LDR X6, [X28, X11,LSL #3] |
(2403) 0x4cf7ec CMP X13, X6 |
(2403) 0x4cf7f0 B.NE 4cf804 |
(2403) 0x4cf7f4 LDR D1, [X21, X4,LSL #3] |
(2403) 0x4cf7f8 FABS D2, D1 |
(2403) 0x4cf7fc FMADD D31, D2, D26, D31 |
(2403) 0x4cf800 STR D31, [X23, X0,LSL #3] |
(2403) 0x4cf804 ADD X3, X1, #3 |
(2403) 0x4cf808 LDR X2, [X20, X3,LSL #3] |
(2403) 0x4cf80c LDR X25, [X28, X2,LSL #3] |
(2403) 0x4cf810 CMP X13, X25 |
(2403) 0x4cf814 B.NE 4cf828 |
(2403) 0x4cf818 LDR D3, [X21, X3,LSL #3] |
(2403) 0x4cf81c FABS D4, D3 |
(2403) 0x4cf820 FMADD D31, D4, D26, D31 |
(2403) 0x4cf824 STR D31, [X23, X0,LSL #3] |
(2403) 0x4cf828 ADD X12, X1, #4 |
(2403) 0x4cf82c LDR X7, [X20, X12,LSL #3] |
(2403) 0x4cf830 LDR X9, [X28, X7,LSL #3] |
(2403) 0x4cf834 CMP X13, X9 |
(2403) 0x4cf838 B.NE 4cf84c |
(2403) 0x4cf83c LDR D5, [X21, X12,LSL #3] |
(2403) 0x4cf840 FABS D6, D5 |
(2403) 0x4cf844 FMADD D31, D6, D26, D31 |
(2403) 0x4cf848 STR D31, [X23, X0,LSL #3] |
(2403) 0x4cf84c ADD X14, X1, #5 |
(2403) 0x4cf850 LDR X15, [X20, X14,LSL #3] |
(2403) 0x4cf854 LDR X16, [X28, X15,LSL #3] |
(2403) 0x4cf858 CMP X13, X16 |
(2403) 0x4cf85c B.NE 4cf870 |
(2403) 0x4cf860 LDR D7, [X21, X14,LSL #3] |
(2403) 0x4cf864 FABS D16, D7 |
(2403) 0x4cf868 FMADD D31, D16, D26, D31 |
(2403) 0x4cf86c STR D31, [X23, X0,LSL #3] |
(2403) 0x4cf870 ADD X17, X1, #6 |
(2403) 0x4cf874 LDR X18, [X20, X17,LSL #3] |
(2403) 0x4cf878 LDR X30, [X28, X18,LSL #3] |
(2403) 0x4cf87c CMP X13, X30 |
(2403) 0x4cf880 B.NE 4cf894 |
(2403) 0x4cf884 LDR D17, [X21, X17,LSL #3] |
(2403) 0x4cf888 FABS D18, D17 |
(2403) 0x4cf88c FMADD D31, D18, D26, D31 |
(2403) 0x4cf890 STR D31, [X23, X0,LSL #3] |
(2403) 0x4cf894 ADD X1, X1, #7 |
(2403) 0x4cf898 CMP X8, X1 |
(2403) 0x4cf89c B.NE 4cf778 |
(2402) 0x4cf8a0 B 4cf1c4 |
0x4cf8a4 CMP X27, #0 |
0x4cf8a8 B.LE 4ce9a0 |
0x4cf8ac MOVZ X1, #0 |
0x4cf8b0 ADD X22, X26, #8 |
0x4cf8b4 LDR X20, [SP, #104] |
0x4cf8b8 LDR X15, [X26, X1,LSL #3] |
0x4cf8bc STR XZR, [X23, X1,LSL #3] |
0x4cf8c0 LDR X16, [X22, X1,LSL #3] |
0x4cf8c4 ADD X10, X20, #8 |
0x4cf8c8 CMP X15, X16 |
0x4cf8cc B.GE 4cfa1c |
(2399) 0x4cf8d0 ADD X17, X24, X16,LSL #3 |
(2399) 0x4cf8d4 MOVI D22, #0 |
(2399) 0x4cf8d8 UBFM X18, X15, #61, #60 |
(2399) 0x4cf8dc ADD X11, X24, X15,LSL #3 |
(2399) 0x4cf8e0 SUB X30, X17, X11 |
(2399) 0x4cf8e4 SUB X8, X30, #8 |
(2399) 0x4cf8e8 UBFM X13, X8, #3, #63 |
(2399) 0x4cf8ec ADD X5, X13, #1 |
(2399) 0x4cf8f0 ANDS X4, X5, #0x7 |
(2399) 0x4cf8f4 B.EQ 4cf988 |
(2399) 0x4cf8f8 CMP X4, #1 |
(2399) 0x4cf8fc B.EQ 4cf974 |
(2399) 0x4cf900 CMP X4, #2 |
(2399) 0x4cf904 B.EQ 4cf968 |
(2399) 0x4cf908 CMP X4, #3 |
(2399) 0x4cf90c B.EQ 4cf95c |
(2399) 0x4cf910 CMP X4, #4 |
(2399) 0x4cf914 B.EQ 4cf950 |
(2399) 0x4cf918 CMP X4, #5 |
(2399) 0x4cf91c B.EQ 4cf944 |
(2399) 0x4cf920 CMP X4, #6 |
(2399) 0x4cf924 B.EQ 4cf938 |
(2399) 0x4cf928 LDR D26, [X24, X18] |
(2399) 0x4cf92c ADD X11, X11, #8 |
(2399) 0x4cf930 FMADD D22, D26, D26, D22 |
(2399) 0x4cf934 STR D22, [X23, X1,LSL #3] |
(2399) 0x4cf938 LDR D27, [X11], #8 |
(2399) 0x4cf93c FMADD D22, D27, D27, D22 |
(2399) 0x4cf940 STR D22, [X23, X1,LSL #3] |
(2399) 0x4cf944 LDR D28, [X11], #8 |
(2399) 0x4cf948 FMADD D22, D28, D28, D22 |
(2399) 0x4cf94c STR D22, [X23, X1,LSL #3] |
(2399) 0x4cf950 LDR D17, [X11], #8 |
(2399) 0x4cf954 FMADD D22, D17, D17, D22 |
(2399) 0x4cf958 STR D22, [X23, X1,LSL #3] |
(2399) 0x4cf95c LDR D18, [X11], #8 |
(2399) 0x4cf960 FMADD D22, D18, D18, D22 |
(2399) 0x4cf964 STR D22, [X23, X1,LSL #3] |
(2399) 0x4cf968 LDR D20, [X11], #8 |
(2399) 0x4cf96c FMADD D22, D20, D20, D22 |
(2399) 0x4cf970 STR D22, [X23, X1,LSL #3] |
(2399) 0x4cf974 LDR D31, [X11], #8 |
(2399) 0x4cf978 FMADD D22, D31, D31, D22 |
(2399) 0x4cf97c STR D22, [X23, X1,LSL #3] |
(2399) 0x4cf980 CMP X17, X11 |
(2399) 0x4cf984 B.EQ 4cf9f8 |
(2398) 0x4cf988 ORR X6, XZR, X11 |
(2398) 0x4cf98c ADD X11, X11, #64 |
(2398) 0x4cf990 LDR D21, [X6], #8 |
(2398) 0x4cf994 FMADD D23, D21, D21, D22 |
(2398) 0x4cf998 STR D23, [X23, X1,LSL #3] |
(2398) 0x4cf99c LDUR D24, [X11, #456] |
(2398) 0x4cf9a0 FMADD D25, D24, D24, D23 |
(2398) 0x4cf9a4 STR D25, [X23, X1,LSL #3] |
(2398) 0x4cf9a8 LDR D29, [X6, #8] |
(2398) 0x4cf9ac FMADD D30, D29, D29, D25 |
(2398) 0x4cf9b0 STR D30, [X23, X1,LSL #3] |
(2398) 0x4cf9b4 LDUR D0, [X11, #472] |
(2398) 0x4cf9b8 FMADD D1, D0, D0, D30 |
(2398) 0x4cf9bc STR D1, [X23, X1,LSL #3] |
(2398) 0x4cf9c0 LDUR D2, [X11, #480] |
(2398) 0x4cf9c4 FMADD D3, D2, D2, D1 |
(2398) 0x4cf9c8 STR D3, [X23, X1,LSL #3] |
(2398) 0x4cf9cc LDUR D4, [X11, #488] |
(2398) 0x4cf9d0 FMADD D5, D4, D4, D3 |
(2398) 0x4cf9d4 STR D5, [X23, X1,LSL #3] |
(2398) 0x4cf9d8 LDUR D6, [X11, #496] |
(2398) 0x4cf9dc FMADD D7, D6, D6, D5 |
(2398) 0x4cf9e0 STR D7, [X23, X1,LSL #3] |
(2398) 0x4cf9e4 LDUR D16, [X11, #504] |
(2398) 0x4cf9e8 FMADD D22, D16, D16, D7 |
(2398) 0x4cf9ec STR D22, [X23, X1,LSL #3] |
(2398) 0x4cf9f0 CMP X17, X11 |
(2398) 0x4cf9f4 B.NE 4cf988 |
(2399) 0x4cf9f8 CBNZ X19, 4cfa24 |
(2399) 0x4cf9fc ADD X1, X1, #1 |
(2399) 0x4cfa00 CMP X27, X1 |
(2399) 0x4cfa04 B.EQ 4ce680 |
(2399) 0x4cfa08 LDR X15, [X26, X1,LSL #3] |
(2399) 0x4cfa0c STR XZR, [X23, X1,LSL #3] |
(2399) 0x4cfa10 LDR X16, [X22, X1,LSL #3] |
(2399) 0x4cfa14 CMP X15, X16 |
(2399) 0x4cfa18 B.LT 4cf8d0 |
(2401) 0x4cfa1c MOVI D22, #0 |
(2401) 0x4cfa20 CBZ X19, 4cf9fc |
(2399) 0x4cfa24 LDR X2, [SP, #104] |
(2399) 0x4cfa28 LDR X3, [X10, X1,LSL #3] |
(2399) 0x4cfa2c LDR X25, [X2, X1,LSL #3] |
(2399) 0x4cfa30 CMP X25, X3 |
(2399) 0x4cfa34 B.GE 4cf9fc |
(2399) 0x4cfa38 ADD X12, X21, X3,LSL #3 |
(2399) 0x4cfa3c UBFM X7, X25, #61, #60 |
(2399) 0x4cfa40 ADD X0, X21, X25,LSL #3 |
(2399) 0x4cfa44 SUB X9, X12, X0 |
(2399) 0x4cfa48 SUB X14, X9, #8 |
(2399) 0x4cfa4c UBFM X20, X14, #3, #63 |
(2399) 0x4cfa50 ADD X15, X20, #1 |
(2399) 0x4cfa54 ANDS X16, X15, #0x7 |
(2399) 0x4cfa58 B.EQ 4cfadc |
(2399) 0x4cfa5c CMP X16, #1 |
(2399) 0x4cfa60 B.EQ 4cfac8 |
(2399) 0x4cfa64 CMP X16, #2 |
(2399) 0x4cfa68 B.EQ 4cfabc |
(2399) 0x4cfa6c CMP X16, #3 |
(2399) 0x4cfa70 B.EQ 4cfab0 |
(2399) 0x4cfa74 CMP X16, #4 |
(2399) 0x4cfa78 B.EQ 4cfaa4 |
(2399) 0x4cfa7c CMP X16, #5 |
(2399) 0x4cfa80 B.EQ 4cfa98 |
(2399) 0x4cfa84 CMP X16, #6 |
(2399) 0x4cfa88 B.NE 4cfed8 |
(2399) 0x4cfa8c LDR D26, [X0], #8 |
(2399) 0x4cfa90 FMADD D22, D26, D26, D22 |
(2399) 0x4cfa94 STR D22, [X23, X1,LSL #3] |
(2399) 0x4cfa98 LDR D27, [X0], #8 |
(2399) 0x4cfa9c FMADD D22, D27, D27, D22 |
(2399) 0x4cfaa0 STR D22, [X23, X1,LSL #3] |
(2399) 0x4cfaa4 LDR D28, [X0], #8 |
(2399) 0x4cfaa8 FMADD D22, D28, D28, D22 |
(2399) 0x4cfaac STR D22, [X23, X1,LSL #3] |
(2399) 0x4cfab0 LDR D17, [X0], #8 |
(2399) 0x4cfab4 FMADD D22, D17, D17, D22 |
(2399) 0x4cfab8 STR D22, [X23, X1,LSL #3] |
(2399) 0x4cfabc LDR D18, [X0], #8 |
(2399) 0x4cfac0 FMADD D22, D18, D18, D22 |
(2399) 0x4cfac4 STR D22, [X23, X1,LSL #3] |
(2399) 0x4cfac8 LDR D20, [X0], #8 |
(2399) 0x4cfacc FMADD D22, D20, D20, D22 |
(2399) 0x4cfad0 STR D22, [X23, X1,LSL #3] |
(2399) 0x4cfad4 CMP X0, X12 |
(2399) 0x4cfad8 B.EQ 4cf9fc |
(2400) 0x4cfadc ORR X17, XZR, X0 |
(2400) 0x4cfae0 ADD X0, X0, #64 |
(2400) 0x4cfae4 LDR D31, [X17], #8 |
(2400) 0x4cfae8 FMADD D22, D31, D31, D22 |
(2400) 0x4cfaec STR D22, [X23, X1,LSL #3] |
(2400) 0x4cfaf0 LDUR D21, [X0, #456] |
(2400) 0x4cfaf4 FMADD D23, D21, D21, D22 |
(2400) 0x4cfaf8 STR D23, [X23, X1,LSL #3] |
(2400) 0x4cfafc LDR D24, [X17, #8] |
(2400) 0x4cfb00 FMADD D25, D24, D24, D23 |
(2400) 0x4cfb04 STR D25, [X23, X1,LSL #3] |
(2400) 0x4cfb08 LDUR D29, [X0, #472] |
(2400) 0x4cfb0c FMADD D30, D29, D29, D25 |
(2400) 0x4cfb10 STR D30, [X23, X1,LSL #3] |
(2400) 0x4cfb14 LDUR D0, [X0, #480] |
(2400) 0x4cfb18 FMADD D2, D0, D0, D30 |
(2400) 0x4cfb1c STR D2, [X23, X1,LSL #3] |
(2400) 0x4cfb20 LDUR D1, [X0, #488] |
(2400) 0x4cfb24 FMADD D3, D1, D1, D2 |
(2400) 0x4cfb28 STR D3, [X23, X1,LSL #3] |
(2400) 0x4cfb2c LDUR D4, [X0, #496] |
(2400) 0x4cfb30 FMADD D5, D4, D4, D3 |
(2400) 0x4cfb34 STR D5, [X23, X1,LSL #3] |
(2400) 0x4cfb38 LDUR D6, [X0, #504] |
(2400) 0x4cfb3c FMADD D22, D6, D6, D5 |
(2400) 0x4cfb40 STR D22, [X23, X1,LSL #3] |
(2400) 0x4cfb44 CMP X0, X12 |
(2400) 0x4cfb48 B.NE 4cfadc |
(2399) 0x4cfb4c B 4cf9fc |
0x4cfb50 LDR X1, [SP, #104] |
0x4cfb54 MOVZ X3, #0 |
0x4cfb58 MOVZ X2, #0 |
0x4cfb5c ADD X13, X26, #8 |
0x4cfb60 ADD X6, X1, #8 |
(2389) 0x4cfb64 CMP X4, X0 |
(2389) 0x4cfb68 B.LE 4cfe68 |
(2389) 0x4cfb6c ADD X4, X24, X4,LSL #3 |
(2389) 0x4cfb70 MOVI D0, #0 |
(2389) 0x4cfb74 UBFM X18, X0, #61, #60 |
(2389) 0x4cfb78 ADD X14, X24, X0,LSL #3 |
(2389) 0x4cfb7c SUB X11, X4, X14 |
(2389) 0x4cfb80 SUB X8, X11, #8 |
(2389) 0x4cfb84 UBFM X12, X8, #3, #63 |
(2389) 0x4cfb88 ADD X7, X12, #1 |
(2389) 0x4cfb8c ANDS X9, X7, #0x7 |
(2389) 0x4cfb90 B.EQ 4cfc3c |
(2389) 0x4cfb94 CMP X9, #1 |
(2389) 0x4cfb98 B.EQ 4cfc24 |
(2389) 0x4cfb9c CMP X9, #2 |
(2389) 0x4cfba0 B.EQ 4cfc14 |
(2389) 0x4cfba4 CMP X9, #3 |
(2389) 0x4cfba8 B.EQ 4cfc04 |
(2389) 0x4cfbac CMP X9, #4 |
(2389) 0x4cfbb0 B.EQ 4cfbf4 |
(2389) 0x4cfbb4 CMP X9, #5 |
(2389) 0x4cfbb8 B.EQ 4cfbe4 |
(2389) 0x4cfbbc CMP X9, #6 |
(2389) 0x4cfbc0 B.EQ 4cfbd4 |
(2389) 0x4cfbc4 LDR D31, [X24, X18] |
(2389) 0x4cfbc8 ADD X14, X14, #8 |
(2389) 0x4cfbcc FABS D0, D31 |
(2389) 0x4cfbd0 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfbd4 LDR D26, [X14], #8 |
(2389) 0x4cfbd8 FABS D27, D26 |
(2389) 0x4cfbdc FADD D0, D0, D27 |
(2389) 0x4cfbe0 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfbe4 LDR D28, [X14], #8 |
(2389) 0x4cfbe8 FABS D17, D28 |
(2389) 0x4cfbec FADD D0, D0, D17 |
(2389) 0x4cfbf0 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfbf4 LDR D18, [X14], #8 |
(2389) 0x4cfbf8 FABS D20, D18 |
(2389) 0x4cfbfc FADD D0, D0, D20 |
(2389) 0x4cfc00 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfc04 LDR D22, [X14], #8 |
(2389) 0x4cfc08 FABS D21, D22 |
(2389) 0x4cfc0c FADD D0, D0, D21 |
(2389) 0x4cfc10 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfc14 LDR D23, [X14], #8 |
(2389) 0x4cfc18 FABS D24, D23 |
(2389) 0x4cfc1c FADD D0, D0, D24 |
(2389) 0x4cfc20 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfc24 LDR D25, [X14], #8 |
(2389) 0x4cfc28 FABS D29, D25 |
(2389) 0x4cfc2c FADD D0, D0, D29 |
(2389) 0x4cfc30 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfc34 CMP X14, X4 |
(2389) 0x4cfc38 B.EQ 4cfccc |
(2391) 0x4cfc3c ORR X15, XZR, X14 |
(2391) 0x4cfc40 ADD X14, X14, #64 |
(2391) 0x4cfc44 LDR D30, [X15], #8 |
(2391) 0x4cfc48 FABS D2, D30 |
(2391) 0x4cfc4c FADD D1, D0, D2 |
(2391) 0x4cfc50 STR D1, [X23, X2,LSL #3] |
(2391) 0x4cfc54 LDUR D3, [X14, #456] |
(2391) 0x4cfc58 FABS D4, D3 |
(2391) 0x4cfc5c FADD D5, D1, D4 |
(2391) 0x4cfc60 STR D5, [X23, X2,LSL #3] |
(2391) 0x4cfc64 LDR D7, [X15, #8] |
(2391) 0x4cfc68 FABS D6, D7 |
(2391) 0x4cfc6c FADD D19, D5, D6 |
(2391) 0x4cfc70 STR D19, [X23, X2,LSL #3] |
(2391) 0x4cfc74 LDUR D16, [X14, #472] |
(2391) 0x4cfc78 FABS D31, D16 |
(2391) 0x4cfc7c FADD D26, D19, D31 |
(2391) 0x4cfc80 STR D26, [X23, X2,LSL #3] |
(2391) 0x4cfc84 LDUR D27, [X14, #480] |
(2391) 0x4cfc88 FABS D28, D27 |
(2391) 0x4cfc8c FADD D17, D26, D28 |
(2391) 0x4cfc90 STR D17, [X23, X2,LSL #3] |
(2391) 0x4cfc94 LDUR D18, [X14, #488] |
(2391) 0x4cfc98 FABS D20, D18 |
(2391) 0x4cfc9c FADD D22, D17, D20 |
(2391) 0x4cfca0 STR D22, [X23, X2,LSL #3] |
(2391) 0x4cfca4 LDUR D21, [X14, #496] |
(2391) 0x4cfca8 FABS D23, D21 |
(2391) 0x4cfcac FADD D24, D22, D23 |
(2391) 0x4cfcb0 STR D24, [X23, X2,LSL #3] |
(2391) 0x4cfcb4 LDUR D25, [X14, #504] |
(2391) 0x4cfcb8 FABS D29, D25 |
(2391) 0x4cfcbc FADD D0, D24, D29 |
(2391) 0x4cfcc0 STR D0, [X23, X2,LSL #3] |
(2391) 0x4cfcc4 CMP X14, X4 |
(2391) 0x4cfcc8 B.NE 4cfc3c |
(2389) 0x4cfccc CBNZ X19, 4cfcf0 |
(2389) 0x4cfcd0 ADD X3, X3, #1 |
(2389) 0x4cfcd4 CMP X27, X3 |
(2389) 0x4cfcd8 B.EQ 4ce680 |
(2389) 0x4cfcdc LDR X0, [X26, X3,LSL #3] |
(2389) 0x4cfce0 ORR X2, XZR, X3 |
(2389) 0x4cfce4 STR XZR, [X23, X3,LSL #3] |
(2389) 0x4cfce8 LDR X4, [X13, X3,LSL #3] |
(2389) 0x4cfcec B 4cfb64 |
(2389) 0x4cfcf0 LDR X17, [SP, #104] |
(2389) 0x4cfcf4 LDR X16, [X6, X2,LSL #3] |
(2389) 0x4cfcf8 LDR X30, [X17, X2,LSL #3] |
(2389) 0x4cfcfc CMP X30, X16 |
(2389) 0x4cfd00 B.GE 4d0004 |
(2389) 0x4cfd04 ADD X20, X21, X16,LSL #3 |
(2389) 0x4cfd08 UBFM X22, X30, #61, #60 |
(2389) 0x4cfd0c ADD X0, X21, X30,LSL #3 |
(2389) 0x4cfd10 SUB X25, X20, X0 |
(2389) 0x4cfd14 SUB X5, X25, #8 |
(2389) 0x4cfd18 UBFM X1, X5, #3, #63 |
(2389) 0x4cfd1c ADD X18, X1, #1 |
(2389) 0x4cfd20 ANDS X11, X18, #0x7 |
(2389) 0x4cfd24 B.EQ 4cfdd4 |
(2389) 0x4cfd28 CMP X11, #1 |
(2389) 0x4cfd2c B.EQ 4cfdbc |
(2389) 0x4cfd30 CMP X11, #2 |
(2389) 0x4cfd34 B.EQ 4cfdac |
(2389) 0x4cfd38 CMP X11, #3 |
(2389) 0x4cfd3c B.EQ 4cfd9c |
(2389) 0x4cfd40 CMP X11, #4 |
(2389) 0x4cfd44 B.EQ 4cfd8c |
(2389) 0x4cfd48 CMP X11, #5 |
(2389) 0x4cfd4c B.EQ 4cfd7c |
(2389) 0x4cfd50 CMP X11, #6 |
(2389) 0x4cfd54 B.EQ 4cfd6c |
(2389) 0x4cfd58 LDR D30, [X21, X22] |
(2389) 0x4cfd5c ADD X0, X0, #8 |
(2389) 0x4cfd60 FABS D2, D30 |
(2389) 0x4cfd64 FADD D0, D0, D2 |
(2389) 0x4cfd68 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfd6c LDR D1, [X0], #8 |
(2389) 0x4cfd70 FABS D3, D1 |
(2389) 0x4cfd74 FADD D0, D0, D3 |
(2389) 0x4cfd78 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfd7c LDR D4, [X0], #8 |
(2389) 0x4cfd80 FABS D5, D4 |
(2389) 0x4cfd84 FADD D0, D0, D5 |
(2389) 0x4cfd88 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfd8c LDR D7, [X0], #8 |
(2389) 0x4cfd90 FABS D6, D7 |
(2389) 0x4cfd94 FADD D0, D0, D6 |
(2389) 0x4cfd98 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfd9c LDR D19, [X0], #8 |
(2389) 0x4cfda0 FABS D16, D19 |
(2389) 0x4cfda4 FADD D0, D0, D16 |
(2389) 0x4cfda8 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfdac LDR D31, [X0], #8 |
(2389) 0x4cfdb0 FABS D26, D31 |
(2389) 0x4cfdb4 FADD D0, D0, D26 |
(2389) 0x4cfdb8 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfdbc LDR D27, [X0], #8 |
(2389) 0x4cfdc0 FABS D28, D27 |
(2389) 0x4cfdc4 FADD D0, D0, D28 |
(2389) 0x4cfdc8 STR D0, [X23, X2,LSL #3] |
(2389) 0x4cfdcc CMP X20, X0 |
(2389) 0x4cfdd0 B.EQ 4cfcd0 |
(2390) 0x4cfdd4 ORR X8, XZR, X0 |
(2390) 0x4cfdd8 ADD X0, X0, #64 |
(2390) 0x4cfddc LDR D17, [X8], #8 |
(2390) 0x4cfde0 FABS D18, D17 |
(2390) 0x4cfde4 FADD D0, D0, D18 |
(2390) 0x4cfde8 STR D0, [X23, X2,LSL #3] |
(2390) 0x4cfdec LDUR D20, [X0, #456] |
(2390) 0x4cfdf0 FABS D22, D20 |
(2390) 0x4cfdf4 FADD D21, D0, D22 |
(2390) 0x4cfdf8 STR D21, [X23, X2,LSL #3] |
(2390) 0x4cfdfc LDR D23, [X8, #8] |
(2390) 0x4cfe00 FABS D24, D23 |
(2390) 0x4cfe04 FADD D25, D21, D24 |
(2390) 0x4cfe08 STR D25, [X23, X2,LSL #3] |
(2390) 0x4cfe0c LDUR D29, [X0, #472] |
(2390) 0x4cfe10 FABS D30, D29 |
(2390) 0x4cfe14 FADD D2, D25, D30 |
(2390) 0x4cfe18 STR D2, [X23, X2,LSL #3] |
(2390) 0x4cfe1c LDUR D1, [X0, #480] |
(2390) 0x4cfe20 FABS D3, D1 |
(2390) 0x4cfe24 FADD D4, D2, D3 |
(2390) 0x4cfe28 STR D4, [X23, X2,LSL #3] |
(2390) 0x4cfe2c LDUR D5, [X0, #488] |
(2390) 0x4cfe30 FABS D7, D5 |
(2390) 0x4cfe34 FADD D6, D4, D7 |
(2390) 0x4cfe38 STR D6, [X23, X2,LSL #3] |
(2390) 0x4cfe3c LDUR D19, [X0, #496] |
(2390) 0x4cfe40 FABS D16, D19 |
(2390) 0x4cfe44 FADD D31, D6, D16 |
(2390) 0x4cfe48 STR D31, [X23, X2,LSL #3] |
(2390) 0x4cfe4c LDUR D26, [X0, #504] |
(2390) 0x4cfe50 FABS D27, D26 |
(2390) 0x4cfe54 FADD D0, D31, D27 |
(2390) 0x4cfe58 STR D0, [X23, X2,LSL #3] |
(2390) 0x4cfe5c CMP X20, X0 |
(2390) 0x4cfe60 B.NE 4cfdd4 |
(2389) 0x4cfe64 B 4cfcd0 |
(2389) 0x4cfe68 MOVI D0, #0 |
(2389) 0x4cfe6c B 4cfccc |
(2392) 0x4cfe70 ADD X5, X5, #1 |
(2392) 0x4cfe74 CMP X27, X5 |
(2392) 0x4cfe78 B.EQ 4ce680 |
(2392) 0x4cfe7c ADD X1, X26, #8 |
(2392) 0x4cfe80 LDR X0, [X26, X5,LSL #3] |
(2392) 0x4cfe84 ORR X3, XZR, X5 |
(2392) 0x4cfe88 STR XZR, [X23, X5,LSL #3] |
(2392) 0x4cfe8c LDR X4, [X1, X5,LSL #3] |
(2392) 0x4cfe90 B 4cec0c |
0x4cfe94 LDR D17, [X23] |
0x4cfe98 MOVZ X8, #1 |
0x4cfe9c FNEG D18, D17 |
0x4cfea0 STR D18, [X23] |
0x4cfea4 B 4ce6d0 |
(2392) 0x4cfea8 LDR D1, [X21, X0,LSL #3] |
(2392) 0x4cfeac LDR D3, [X23, X3,LSL #3] |
(2392) 0x4cfeb0 FABS D4, D1 |
(2392) 0x4cfeb4 FADD D5, D3, D4 |
(2392) 0x4cfeb8 STR D5, [X23, X3,LSL #3] |
(2392) 0x4cfebc B 4cef78 |
(2395) 0x4cfec0 LDR D20, [X21, X1,LSL #3] |
(2395) 0x4cfec4 LDR D22, [X23, X0,LSL #3] |
(2395) 0x4cfec8 FABS D21, D20 |
(2395) 0x4cfecc FADD D23, D22, D21 |
(2395) 0x4cfed0 STR D23, [X23, X0,LSL #3] |
(2395) 0x4cfed4 B 4cf47c |
(2399) 0x4cfed8 LDR D19, [X21, X7] |
(2399) 0x4cfedc ADD X0, X0, #8 |
(2399) 0x4cfee0 FMADD D22, D19, D19, D22 |
(2399) 0x4cfee4 STR D22, [X23, X1,LSL #3] |
(2399) 0x4cfee8 B 4cfa8c |
(2402) 0x4cfeec LDR D19, [X21, X1,LSL #3] |
(2402) 0x4cfef0 FABS D20, D19 |
(2402) 0x4cfef4 FMADD D31, D20, D26, D31 |
(2402) 0x4cfef8 STR D31, [X23, X0,LSL #3] |
(2402) 0x4cfefc B 4cf748 |
(2395) 0x4cff00 LDR D27, [X21, X1,LSL #3] |
(2395) 0x4cff04 LDR D28, [X23, X0,LSL #3] |
(2395) 0x4cff08 FABS D17, D27 |
(2395) 0x4cff0c FADD D18, D28, D17 |
(2395) 0x4cff10 STR D18, [X23, X0,LSL #3] |
(2395) 0x4cff14 B 4cf468 |
(2402) 0x4cff18 LDR D17, [X21, X1,LSL #3] |
(2402) 0x4cff1c FABS D18, D17 |
(2402) 0x4cff20 FMADD D31, D18, D26, D31 |
(2402) 0x4cff24 STR D31, [X23, X0,LSL #3] |
(2402) 0x4cff28 B 4cf734 |
(2402) 0x4cff2c LDR D7, [X21, X1,LSL #3] |
(2402) 0x4cff30 FABS D16, D7 |
(2402) 0x4cff34 FMADD D31, D16, D26, D31 |
(2402) 0x4cff38 STR D31, [X23, X0,LSL #3] |
(2402) 0x4cff3c B 4cf720 |
(2392) 0x4cff40 LDR D29, [X21, X0,LSL #3] |
(2392) 0x4cff44 LDR D30, [X23, X3,LSL #3] |
(2392) 0x4cff48 FABS D0, D29 |
(2392) 0x4cff4c FADD D2, D30, D0 |
(2392) 0x4cff50 STR D2, [X23, X3,LSL #3] |
(2392) 0x4cff54 B 4cef64 |
(2395) 0x4cff58 LDR D16, [X21, X1,LSL #3] |
(2395) 0x4cff5c ADD X1, X1, #1 |
(2395) 0x4cff60 FABS D19, D16 |
(2395) 0x4cff64 FADD D26, D31, D19 |
(2395) 0x4cff68 STR D26, [X23, X0,LSL #3] |
(2395) 0x4cff6c B 4cf458 |
(2402) 0x4cff70 LDR D5, [X21, X1,LSL #3] |
(2402) 0x4cff74 ADD X1, X1, #1 |
(2402) 0x4cff78 FABS D6, D5 |
(2402) 0x4cff7c FMADD D31, D6, D26, D31 |
(2402) 0x4cff80 STR D31, [X23, X0,LSL #3] |
(2402) 0x4cff84 B 4cf710 |
(2402) 0x4cff88 LDR D3, [X21, X1,LSL #3] |
(2402) 0x4cff8c FABS D4, D3 |
(2402) 0x4cff90 FMADD D31, D4, D26, D31 |
(2402) 0x4cff94 STR D31, [X23, X0,LSL #3] |
(2402) 0x4cff98 B 4cf6f8 |
(2402) 0x4cff9c LDR D1, [X21, X1,LSL #3] |
(2402) 0x4cffa0 FABS D2, D1 |
(2402) 0x4cffa4 FMADD D31, D2, D26, D28 |
(2402) 0x4cffa8 STR D31, [X23, X0,LSL #3] |
(2402) 0x4cffac B 4cf6e4 |
0x4cffb0 FMOV D30, #1.0000000 |
0x4cffb4 MOVZ X20, #0 |
0x4cffb8 CMP X27, #0 |
0x4cffbc B.LE 4ce9a8 |
(2405) 0x4cffc0 LDR X19, [X26, X20,LSL #3] |
(2405) 0x4cffc4 LDR D31, [X24, X19,LSL #3] |
(2405) 0x4cffc8 FCMP D31, #0 |
(2405) 0x4cffcc B.NE 4cfff0 |
(2406) 0x4cffd0 STR D30, [X23, X20,LSL #3] |
(2406) 0x4cffd4 ADD X20, X20, #1 |
(2406) 0x4cffd8 CMP X27, X20 |
(2406) 0x4cffdc B.EQ 4ce9a8 |
(2406) 0x4cffe0 LDR X19, [X26, X20,LSL #3] |
(2406) 0x4cffe4 LDR D31, [X24, X19,LSL #3] |
(2406) 0x4cffe8 FCMP D31, #0 |
(2406) 0x4cffec B.EQ 4cffd0 |
(2405) 0x4cfff0 STR D31, [X23, X20,LSL #3] |
(2405) 0x4cfff4 ADD X20, X20, #1 |
(2405) 0x4cfff8 CMP X27, X20 |
(2405) 0x4cfffc B.NE 4cffc0 |
0x4d0000 B 4ce9a8 |
(2389) 0x4d0004 ADD X3, X3, #1 |
(2389) 0x4d0008 CMP X3, X27 |
(2389) 0x4d000c B.EQ 4ce680 |
(2389) 0x4d0010 ADD X10, X26, #8 |
(2389) 0x4d0014 LDR X0, [X26, X3,LSL #3] |
(2389) 0x4d0018 ORR X2, XZR, X3 |
(2389) 0x4d001c STR XZR, [X23, X3,LSL #3] |
(2389) 0x4d0020 LDR X4, [X10, X3,LSL #3] |
(2389) 0x4d0024 B 4cfb64 |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►97.14+ | hypre_BoomerAMGSetup | par_amg_setup.c:1381 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | amg.c:253 | exec |
| ►1.79+ | hypre_BoomerAMGSetup | par_amg_setup.c:1385 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | amg.c:253 | exec |
| ►1.07+ | hypre_BoomerAMGSetup | par_amg_setup.c:1381 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | amg.c:253 | exec |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run 1x1
| Source file and lines | ams.c:547-738 |
| Module | exec |
| nb instructions | 275 |
| nb uops | 273 |
| loop length | 1100 |
| used w registers | 0 |
| used x registers | 31 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 1 |
| used d registers | 24 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 0 |
| nb stack references | 31 |
| micro-operation queue | 34.13 cycles |
| front end | 34.13 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 34.50 | 34.50 | 25.00 | 25.00 | 25.00 | 25.00 | 14.00 | 7.00 | 5.00 | 5.00 | 29.83 | 29.50 | 29.67 | 8.00 | 8.00 |
| cycles | 34.50 | 34.50 | 25.00 | 25.00 | 25.00 | 25.00 | 14.00 | 7.00 | 5.00 | 5.00 | 29.83 | 29.50 | 29.67 | 8.00 | 8.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 34.13 |
| Dispatch | 34.50 |
| Overall L1 | 34.50 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 27% |
| load | 25% |
| store | 33% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 25% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 26% |
| load | 25% |
| store | 33% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| STP X29, X30, [SP, #880]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| ORR X22, XZR, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X27, X28, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| MOVZ X28, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X5, [X0, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X27, [X5, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X26, X25, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| STR X1, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X24, [X5, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STP X3, X0, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDR X1, [X0, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X0, X20, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR X19, [X1, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STR X0, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| UBFM X0, X27, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X21, [X1, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| BL 5293e8 <hypre_MAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X23, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CBZ X22, 4ce644 <hypre_ParCSRComputeL1Norms+0x114> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X4, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X10, [X4, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CBNZ X19, 4ce9f4 <hypre_ParCSRComputeL1Norms+0x4c4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ X2, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X3, [X10, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X6, [X10, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| UBFM X12, X3, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X0, [X6, X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CBNZ X0, 4ce9d4 <hypre_ParCSRComputeL1Norms+0x4a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X3, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.LE 4ce624 <hypre_ParCSRComputeL1Norms+0xf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X7, [X10, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| MOVZ X3, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X1, X7, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X8, X1, X12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ORR X1, XZR, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ORR X3, XZR, X28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STR X2, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| MOVZ X0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| BL 4e4f44 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| BL 4e574c <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X0, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| BL 5294c0 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X2, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| CMP X2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4cebe4 <hypre_ParCSRComputeL1Norms+0x6b4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X2, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4cea28 <hypre_ParCSRComputeL1Norms+0x4f8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X2, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4cf8a4 <hypre_ParCSRComputeL1Norms+0x1374> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X2, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4cf198 <hypre_ParCSRComputeL1Norms+0xc68> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X2, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4cffb0 <hypre_ParCSRComputeL1Norms+0x1a80> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.LE 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| ANDS X12, X27, #0x7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| MOVZ X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| B.EQ 4ce75c <hypre_ParCSRComputeL1Norms+0x22c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce734 <hypre_ParCSRComputeL1Norms+0x204> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X12, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce720 <hypre_ParCSRComputeL1Norms+0x1f0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X12, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce70c <hypre_ParCSRComputeL1Norms+0x1dc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X12, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce6f8 <hypre_ParCSRComputeL1Norms+0x1c8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X12, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce6e4 <hypre_ParCSRComputeL1Norms+0x1b4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X12, #6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce6d0 <hypre_ParCSRComputeL1Norms+0x1a0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X7, [X26] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D28, [X24, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D28, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.MI 4cfe94 <hypre_ParCSRComputeL1Norms+0x1964> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X9, [X26, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D0, [X24, X9,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D0, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.MI 4cf394 <hypre_ParCSRComputeL1Norms+0xe64> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X14, [X26, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D21, [X24, X14,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D21, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.MI 4cf170 <hypre_ParCSRComputeL1Norms+0xc40> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X15, [X26, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D25, [X24, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D25, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.MI 4cf148 <hypre_ParCSRComputeL1Norms+0xc18> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X16, [X26, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D2, [X24, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D2, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.MI 4ceed8 <hypre_ParCSRComputeL1Norms+0x9a8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X17, [X26, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D4, [X24, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D4, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.MI 4ceec8 <hypre_ParCSRComputeL1Norms+0x998> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X30, [X26, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D6, [X24, X30,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D6, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.GE 4ce750 <hypre_ParCSRComputeL1Norms+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D19, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNEG D16, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D16, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X27, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce864 <hypre_ParCSRComputeL1Norms+0x334> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ANDS X24, X27, #0x7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| MOVZ X16, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| B.EQ 4ce918 <hypre_ParCSRComputeL1Norms+0x3e8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X24, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce900 <hypre_ParCSRComputeL1Norms+0x3d0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X24, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce8f0 <hypre_ParCSRComputeL1Norms+0x3c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X24, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce8e0 <hypre_ParCSRComputeL1Norms+0x3b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X24, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce8d0 <hypre_ParCSRComputeL1Norms+0x3a0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X24, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce8c0 <hypre_ParCSRComputeL1Norms+0x390> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X24, #6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce8b0 <hypre_ParCSRComputeL1Norms+0x380> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D31, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| MOVZ X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCMP D31, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D26, [X23, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X16, X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCMP D26, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D27, [X23, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X16, X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCMP D27, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D28, [X23, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X16, X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCMP D28, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D17, [X23, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X16, X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCMP D17, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D18, [X23, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X16, X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCMP D18, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D0, [X23, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMP D0, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X16, X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X27, X16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X0, XZR, X28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| BL 5294c0 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X30, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADRP X17, <5719ac> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X0, [X17, #3856] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR X23, [X30] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDP X27, X28, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDP X29, X30, [SP], #144 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ X1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STP X12, X10, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STR X3, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| BL 529428 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X3, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| ORR X2, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDP X12, X10, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| B 4ce5b4 <hypre_ParCSRComputeL1Norms+0x84> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ X1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR X10, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| BL 529428 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X10, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ORR X28, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ X2, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X3, [X10, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X6, [X10, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| UBFM X12, X3, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X0, [X6, X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CBZ X0, 4ce5b4 <hypre_ParCSRComputeL1Norms+0x84> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4ce9d4 <hypre_ParCSRComputeL1Norms+0x4a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.LE 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X10, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| MOVZ X0, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X18, X10, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| B 4cea50 <hypre_ParCSRComputeL1Norms+0x520> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.LE 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR XZR, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDP X0, X4, [X26] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| CBZ X22, 4cfb50 <hypre_ParCSRComputeL1Norms+0x1620> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ X5, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ X3, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X6, X26, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X18, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| ADD X10, X18, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR D5, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNEG D7, D5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D7, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 4ce730 <hypre_ParCSRComputeL1Norms+0x200> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D1, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNEG D3, D1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D3, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 4ce71c <hypre_ParCSRComputeL1Norms+0x1ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADRP X27, <542ee8> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ X3, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X27, #496 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ X2, #12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ X1, #728 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| BL 52cf20 <hypre_error_handler> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D29, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNEG D30, D29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D30, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 4ce708 <hypre_ParCSRComputeL1Norms+0x1d8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D23, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNEG D24, D23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D24, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 4ce6f4 <hypre_ParCSRComputeL1Norms+0x1c4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.LE 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X12, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ORR X25, XZR, #0x55 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| FMOV D26, #0.5000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| MOVK X25, #16373 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ X0, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FMOV D27, X25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| ADD X10, X12, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| B 4cf1e0 <hypre_ParCSRComputeL1Norms+0xcb0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D20, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNEG D22, D20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D22, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 4ce6e0 <hypre_ParCSRComputeL1Norms+0x1b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.LE 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ X1, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X22, X26, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X20, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X15, [X26, X1,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR XZR, [X23, X1,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X16, [X22, X1,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD X10, X20, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X15, X16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.GE 4cfa1c <hypre_ParCSRComputeL1Norms+0x14ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X1, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| MOVZ X3, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ X2, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X13, X26, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X6, X1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR D17, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| MOVZ X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FNEG D18, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D18, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 4ce6d0 <hypre_ParCSRComputeL1Norms+0x1a0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| FMOV D30, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| MOVZ X20, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| CMP X27, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.LE 4ce9a8 <hypre_ParCSRComputeL1Norms+0x478> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4ce9a8 <hypre_ParCSRComputeL1Norms+0x478> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run 1x1
| Source file and lines | ams.c:547-738 |
| Module | exec |
| nb instructions | 275 |
| nb uops | 273 |
| loop length | 1100 |
| used w registers | 0 |
| used x registers | 31 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 1 |
| used d registers | 24 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 0 |
| nb stack references | 31 |
| micro-operation queue | 34.13 cycles |
| front end | 34.13 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 34.50 | 34.50 | 25.00 | 25.00 | 25.00 | 25.00 | 14.00 | 7.00 | 5.00 | 5.00 | 29.83 | 29.50 | 29.67 | 8.00 | 8.00 |
| cycles | 34.50 | 34.50 | 25.00 | 25.00 | 25.00 | 25.00 | 14.00 | 7.00 | 5.00 | 5.00 | 29.83 | 29.50 | 29.67 | 8.00 | 8.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 34.13 |
| Dispatch | 34.50 |
| Overall L1 | 34.50 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 27% |
| load | 25% |
| store | 33% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 25% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 26% |
| load | 25% |
| store | 33% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| STP X29, X30, [SP, #880]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| ORR X22, XZR, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X27, X28, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| MOVZ X28, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X5, [X0, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X27, [X5, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X26, X25, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| STR X1, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X24, [X5, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STP X3, X0, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDR X1, [X0, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X0, X20, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR X19, [X1, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STR X0, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| UBFM X0, X27, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X21, [X1, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| BL 5293e8 <hypre_MAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X23, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CBZ X22, 4ce644 <hypre_ParCSRComputeL1Norms+0x114> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X4, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X10, [X4, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CBNZ X19, 4ce9f4 <hypre_ParCSRComputeL1Norms+0x4c4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ X2, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X3, [X10, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X6, [X10, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| UBFM X12, X3, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X0, [X6, X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CBNZ X0, 4ce9d4 <hypre_ParCSRComputeL1Norms+0x4a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X3, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.LE 4ce624 <hypre_ParCSRComputeL1Norms+0xf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X7, [X10, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| MOVZ X3, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X1, X7, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X8, X1, X12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ORR X1, XZR, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ORR X3, XZR, X28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STR X2, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| MOVZ X0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| BL 4e4f44 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| BL 4e574c <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X0, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| BL 5294c0 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X2, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| CMP X2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4cebe4 <hypre_ParCSRComputeL1Norms+0x6b4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X2, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4cea28 <hypre_ParCSRComputeL1Norms+0x4f8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X2, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4cf8a4 <hypre_ParCSRComputeL1Norms+0x1374> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X2, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4cf198 <hypre_ParCSRComputeL1Norms+0xc68> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X2, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4cffb0 <hypre_ParCSRComputeL1Norms+0x1a80> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.LE 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| ANDS X12, X27, #0x7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| MOVZ X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| B.EQ 4ce75c <hypre_ParCSRComputeL1Norms+0x22c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce734 <hypre_ParCSRComputeL1Norms+0x204> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X12, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce720 <hypre_ParCSRComputeL1Norms+0x1f0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X12, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce70c <hypre_ParCSRComputeL1Norms+0x1dc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X12, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce6f8 <hypre_ParCSRComputeL1Norms+0x1c8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X12, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce6e4 <hypre_ParCSRComputeL1Norms+0x1b4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X12, #6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce6d0 <hypre_ParCSRComputeL1Norms+0x1a0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X7, [X26] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D28, [X24, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D28, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.MI 4cfe94 <hypre_ParCSRComputeL1Norms+0x1964> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X9, [X26, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D0, [X24, X9,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D0, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.MI 4cf394 <hypre_ParCSRComputeL1Norms+0xe64> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X14, [X26, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D21, [X24, X14,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D21, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.MI 4cf170 <hypre_ParCSRComputeL1Norms+0xc40> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X15, [X26, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D25, [X24, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D25, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.MI 4cf148 <hypre_ParCSRComputeL1Norms+0xc18> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X16, [X26, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D2, [X24, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D2, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.MI 4ceed8 <hypre_ParCSRComputeL1Norms+0x9a8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X17, [X26, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D4, [X24, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D4, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.MI 4ceec8 <hypre_ParCSRComputeL1Norms+0x998> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X30, [X26, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D6, [X24, X30,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMPE D6, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.GE 4ce750 <hypre_ParCSRComputeL1Norms+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D19, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNEG D16, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D16, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X27, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce864 <hypre_ParCSRComputeL1Norms+0x334> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ANDS X24, X27, #0x7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| MOVZ X16, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| B.EQ 4ce918 <hypre_ParCSRComputeL1Norms+0x3e8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X24, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce900 <hypre_ParCSRComputeL1Norms+0x3d0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X24, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce8f0 <hypre_ParCSRComputeL1Norms+0x3c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X24, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce8e0 <hypre_ParCSRComputeL1Norms+0x3b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X24, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce8d0 <hypre_ParCSRComputeL1Norms+0x3a0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X24, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce8c0 <hypre_ParCSRComputeL1Norms+0x390> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X24, #6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce8b0 <hypre_ParCSRComputeL1Norms+0x380> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D31, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| MOVZ X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCMP D31, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D26, [X23, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X16, X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCMP D26, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D27, [X23, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X16, X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCMP D27, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D28, [X23, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X16, X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCMP D28, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D17, [X23, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X16, X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCMP D17, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D18, [X23, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD X16, X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FCMP D18, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D0, [X23, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FCMP D0, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.EQ 4ceee8 <hypre_ParCSRComputeL1Norms+0x9b8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD X16, X16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X27, X16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.EQ 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR X0, XZR, X28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| BL 5294c0 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X30, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADRP X17, <5719ac> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X0, [X17, #3856] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR X23, [X30] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDP X27, X28, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDP X29, X30, [SP], #144 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ X1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STP X12, X10, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STR X3, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| BL 529428 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X3, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| ORR X2, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDP X12, X10, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| B 4ce5b4 <hypre_ParCSRComputeL1Norms+0x84> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ X1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR X10, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| BL 529428 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X10, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ORR X28, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ X2, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X3, [X10, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X6, [X10, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| UBFM X12, X3, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X0, [X6, X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CBZ X0, 4ce5b4 <hypre_ParCSRComputeL1Norms+0x84> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4ce9d4 <hypre_ParCSRComputeL1Norms+0x4a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.LE 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X10, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| MOVZ X0, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X18, X10, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| B 4cea50 <hypre_ParCSRComputeL1Norms+0x520> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.LE 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR XZR, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDP X0, X4, [X26] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| CBZ X22, 4cfb50 <hypre_ParCSRComputeL1Norms+0x1620> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ X5, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ X3, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X6, X26, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X18, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| ADD X10, X18, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR D5, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNEG D7, D5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D7, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 4ce730 <hypre_ParCSRComputeL1Norms+0x200> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D1, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNEG D3, D1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D3, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 4ce71c <hypre_ParCSRComputeL1Norms+0x1ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADRP X27, <542ee8> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ X3, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X27, #496 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ X2, #12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ X1, #728 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| BL 52cf20 <hypre_error_handler> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D29, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNEG D30, D29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D30, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 4ce708 <hypre_ParCSRComputeL1Norms+0x1d8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D23, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNEG D24, D23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D24, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 4ce6f4 <hypre_ParCSRComputeL1Norms+0x1c4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.LE 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X12, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ORR X25, XZR, #0x55 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| FMOV D26, #0.5000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| MOVK X25, #16373 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ X0, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FMOV D27, X25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| ADD X10, X12, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| B 4cf1e0 <hypre_ParCSRComputeL1Norms+0xcb0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR D20, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FNEG D22, D20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D22, [X23, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 4ce6e0 <hypre_ParCSRComputeL1Norms+0x1b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CMP X27, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.LE 4ce9a0 <hypre_ParCSRComputeL1Norms+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MOVZ X1, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X22, X26, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X20, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X15, [X26, X1,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR XZR, [X23, X1,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X16, [X22, X1,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD X10, X20, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP X15, X16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (25.0%) |
| B.GE 4cfa1c <hypre_ParCSRComputeL1Norms+0x14ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X1, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| MOVZ X3, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ X2, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X13, X26, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X6, X1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR D17, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| MOVZ X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| FNEG D18, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D18, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 4ce6d0 <hypre_ParCSRComputeL1Norms+0x1a0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| FMOV D30, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| MOVZ X20, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| CMP X27, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.LE 4ce9a8 <hypre_ParCSRComputeL1Norms+0x478> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4ce9a8 <hypre_ParCSRComputeL1Norms+0x478> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| Run 1x1 | Number processes: 1Number nodes: NARun Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads |
|---|---|
| Run 1x2 | Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x4 | Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x8 | Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x16 | Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x24 | Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x32 | Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x40 | Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x48 | Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x56 | Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| Run 1x64 | Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads |
| (1x1) Efficiency | (1x1) Potential Speed-Up (%) | (1x2) Efficiency | (1x2) Potential Speed-Up (%) | (1x4) Efficiency | (1x4) Potential Speed-Up (%) | (1x8) Efficiency | (1x8) Potential Speed-Up (%) | (1x16) Efficiency | (1x16) Potential Speed-Up (%) | (1x24) Efficiency | (1x24) Potential Speed-Up (%) | (1x32) Efficiency | (1x32) Potential Speed-Up (%) | (1x40) Efficiency | (1x40) Potential Speed-Up (%) | (1x48) Efficiency | (1x48) Potential Speed-Up (%) | (1x56) Efficiency | (1x56) Potential Speed-Up (%) | (1x64) Efficiency | (1x64) Potential Speed-Up (%) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | 0 |
| Run | Number of threads | Efficiency (ideal is 1) | Speedup | Ideal Speedup | Time (s) | Coverage (%) |
|---|---|---|---|---|---|---|
| 1x1 | 1 | 1 | 1 | 1 | 1.4000002145767 | 0.40450817346573 |
| 1x2 | ||||||
| 1x4 | ||||||
| 1x8 | ||||||
| 1x16 | ||||||
| 1x24 | ||||||
| 1x32 | ||||||
| 1x40 | ||||||
| 1x48 | ||||||
| 1x56 | ||||||
| 1x64 |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼hypre_ParCSRComputeL1Norms– | 0.40 | 1.40 |
| ▼Loop 2389 - ams.c:602-614 - exec– | 0.09 | 0.31 |
| ○Loop 2391 - ams.c:608-609 - exec | 0.24 | 0.82 |
| ○Loop 2390 - ams.c:613-614 - exec | 0.00 | 0.00 |
| ○Loop 2387 - ams.c:720-722 - exec | 0.07 | 0.24 |
| ▼Loop 2401 - ams.c:664-671 - exec– | 0.00 | 0.00 |
| ▼Loop 2399 - ams.c:664-671 - exec– | 0.00 | 0.00 |
| ○Loop 2398 - ams.c:667-668 - exec | 0.00 | 0.00 |
| ○Loop 2400 - ams.c:670-671 - exec | 0.00 | 0.00 |
| ○Loop 2388 - ams.c:724-726 - exec | 0.00 | 0.00 |
| ▼Loop 2405 - ams.c:708-711 - exec– | 0.00 | 0.00 |
| ○Loop 2406 - ams.c:708-711 - exec | 0.00 | 0.00 |
| ▼Loop 2407 - ams.c:586-591 - exec– | 0.00 | 0.00 |
| ○Loop 2408 - ams.c:589-591 - exec | 0.00 | 0.00 |
| ▼Loop 2392 - ams.c:602-629 - exec– | 0.00 | 0.00 |
| ○Loop 2394 - ams.c:621-623 - exec | 0.00 | 0.00 |
| ○Loop 2393 - ams.c:627-629 - exec | 0.00 | 0.00 |
| ▼Loop 2402 - ams.c:676-703 - exec– | 0.00 | 0.00 |
| ○Loop 2403 - ams.c:695-697 - exec | 0.00 | 0.00 |
| ○Loop 2404 - ams.c:685-686 - exec | 0.00 | 0.00 |
| ▼Loop 2395 - ams.c:636-657 - exec– | 0.00 | 0.00 |
| ○Loop 2396 - ams.c:655-657 - exec | 0.00 | 0.00 |
| ○Loop 2397 - ams.c:645-646 - exec | 0.00 | 0.00 |
